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产品型号LP38691SD-ADJ的概述

LP38691SD-ADJ 芯片概述 LP38691SD-ADJ是一款高性能的线性稳压器（LDO），其设计旨在满足低电源噪声及快速瞬态响应的需求。这款芯片主要用于为后续电路提供稳定、低噪声的直流电源，特别适合于无线通信、便携式设备及高性能射频应用等场合。其可调输出电压范围和内置的过流及过热保护功能，使得LP38691SD-ADJ在多种应用中具有良好的灵活性。详细参数 LP38691SD-ADJ的几个关键参数包括： 1. 输入电压范围：1.8V至20V，这使得该芯片可以在广泛的电源条件下工作。 2. 输出电压：可调输出，范围从1.25V到15V，允许用户根据不同需求进行设置。 3. 输出电流：最大输出电流为1A，适用于大多数中低功耗应用。 4. 静态电流：在未负载条件下的静态电流典型值为650μA。 5. 纹波抑制比（PSRR）：在低频电源噪声下，其PSRR达到了80dB，极大地减少了...

产品型号LP38691SD-ADJ的Datasheet PDF文件预览

PRELIMINARY

January 2005

LP38691-ADJ/LP38693-ADJ

500mA Low Dropout CMOS Linear Regulators with

Adjustable Output

Stable with Ceramic Output Capacitors

General Description

The LP38691/3-ADJ low dropout CMOS linear regulators

provide 2.0% precision reference voltage, extremely low

Features

n Output voltage range of 1.25V - 9V

n 2.0% adjust pin voltage accuracy (25˚C)

dropout voltage (250mV 500mA load current, V_OUT= 5V)

n Low dropout voltage: 250mV 500mA (typ, 5V out)

and excellent AC performance utilizing ultra low ESR ce-

ramic output capacitors.

n Wide input voltage range (2.7V to 10V)

n Precision (trimmed) bandgap reference

n Guaranteed specs for -40˚C to +125˚C

n 1µA off-state quiescent current

n Thermal overload protection

The low thermal resistance of the LLP and SOT-223 pack-

ages allow the full operating current to be used even in high

ambient temperature environments.

The use of a PMOS power transistor means that no DC base

drive current is required to bias it allowing ground pin current

to remain below 100 µA regardless of load current, input

voltage, or operating temperature.

n Foldback current limiting

n SOT-223 and 6-Lead LLP packages

n Enable pin (LP38693-ADJ)

Dropout Voltage: 250 mV (typ) 500mA (typ. 5V out).

Applications

Ground Pin Current: 55 µA (typ) at full load.

Adjust Pin Voltage: 2.0% (25˚C) accuracy.

n Hard Disk Drives

n Notebook Computers

n Battery Powered Devices

n Portable Instrumentation

Typical Application Circuits

20126801

20126802

V_OUT= V_ADJx (1 + R1/R2)

Note: *Minimum value required for stability.

DS201268

www.national.com

Connection Diagrams

20126803

SOT-223, Top View

LP38693MP-ADJ

20126804

20126805

6-Lead LLP, Bottom View

LP38693SD-ADJ

6-Lead LLP, Bottom View

LP38691SD-ADJ

Pin Description

DESCRIPTION

V_IN

This is the input supply voltage to the regulator. For LLP package devices, both V_INpins must be

tied together for full current operation (250mA maximum per pin).

GND

Circuit ground for the regulator. This is connected to the die through the lead frame, and also

functions as the heat sink when the large ground pad is soldered down to a copper plane.

Regulated output voltage.

V_OUT

V_EN

The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

The adjust pin is used to set the regulated output voltage by connecting it to the external

resistors R1 and R2 (see Typical Application Circuit).

ADJ

Ordering Information

Order Number

LP38691SD-ADJ

LP38693SD-ADJ

LP38693MP-ADJ

LP38691SDX-ADJ

LP38693SDX-ADJ

LP38693MPX-ADJ

Package Marking

Package Type

6-Lead LLP

SOT-223

Package Drawing

SDE06A

Supplied As

L117B

L127B

LJUB

1000 Units Tape and Reel

4500 Units Tape and Reel

2000 Units Tape and Reel

SDE06A

MP05A

L117B

L127B

LJUB

6-Lead LLP

SOT-223

SDE06A

MP05A

www.national.com

Absolute Maximum Ratings (Note 1)

I_OUT

Internally Limited

−40˚C to +150˚C

Junction Temperature

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Ratings

V_INSupply Voltage

Operating Junction

Temperature Range

Storage Temperature Range

Lead Temp. (Soldering, 5 seconds)

ESD Rating (Note 3)

−65˚C to +150˚C

260˚C

2.7V to 10V

−40˚C to +125˚C

2 kV

Power Dissipation (Note 2)

Internally Limited

-0.3V to 12V

V(max) All pins (with respect to GND)

Electrical Characteristics Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply

over the full operating temperature range. Unless otherwise specified: V_IN= V_OUT+ 1V, C_IN= C_OUT= 10 µF, I_LOAD= 10mA.

Min/Max limits are guaranteed through testing, statistical correlation, or design.

Typ

(Note 4)

1.25

Symbol

Parameter

Conditions

Min

Max

1.275

1.300

Units

V_IN= 2.7V

3.2V ≤ V_IN≤ 10V

1.225

1.200

V_ADJ

ADJ Pin Voltage

1.25

0.03

1.8

100 µA I_L0.5A

V_O+ 0.5V ≤ V_IN≤ 10V

I_L= 25mA

∆V_O/∆V_IN

∆V_O/∆I_L

Output Voltage Line Regulation

(Note 6)

0.1

%/V

%/A

Output Voltage Load Regulation 1 mA I_L0.5A

(Note 7)

V_IN= V_O+ 1V

(V_O= 2.5V)

I_L= 0.1A

145

725

430

I_L= 0.5A

(V_O= 3.3V)

I_L= 0.1A

110

550

V_IN- V_O

Dropout Voltage (Note 8)

Quiescent Current

330

I_L= 0.5A

(V_O= 5V)

100

450

I_L= 0.1A

250

I_L= 0.5A

I_Q

V_IN≤ 10V, I_L= 100 µA - 0.5A

V_EN≤ 0.4V,

(LP38693-ADJ Only)

V_IN- V_O≤ 4V

100

0.001

µA

I_L(MIN)

I_FB

Minimum Load Current

Foldback Current Limit

100

V_IN- V_O5V

350

850

V_IN- V_O4V

PSRR

T_SD

Ripple Rejection

V_IN= V_O+ 2V(DC), with 1V(p-p)

/ 120Hz Ripple

160

Thermal Shutdown Activation

(Junction Temp)

˚C

T_SD(HYST) Thermal Shutdown Hysteresis

(Junction Temp)

I_ADJ

ADJ Input Leakage Current

V_ADJ= 0 - 1.5V

V_IN= 10V

-100

0.01

100

www.national.com

Electrical Characteristics Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply

over the full operating temperature range. Unless otherwise specified: V_IN= V_OUT+ 1V, C_IN= C_OUT= 10 µF, I_LOAD= 10mA.

Min/Max limits are guaranteed through testing, statistical correlation, or design. (Continued)

Typ

(Note 4)

Symbol

Parameter

Output Noise

Conditions

Min

Max

Units

µV/

e_n

BW = 10Hz to 10kHz

V_O= 3.3V

0.7

V_O(LEAK)

V_EN

Output Leakage Current

Enable Voltage (LP38693-ADJ

Only)

V_O= V_O(NOM) + 1V 10V_IN

Output = OFF

0.5

µA

0.4

Output = ON, V_IN= 4V

Output = ON, V_IN= 6V

Output = ON, V_IN= 10V

V_EN= 0V or 10V, V_IN= 10V

1.8

3.0

4.0

-1

I_EN

Enable Pin Leakage

(LP38693-ADJ Only)

0.001

µA

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device

is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not

apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). The

junction-to-ambient thermal resistance (θ ) for the SOT-223 is approximately 125 ˚C/W for a PC board mounting with the device soldered down to minimum copper

J-A

area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the SOT-223, the θ drops to approximately 70 ˚C/W. The θ values

J-A

for the LLP package are also dependent on trace area, copper thickness, and the number of thermal vias used (refer to application note AN-1187). If power disspation

causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.

Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

www.national.com

Block Diagrams

20126806

FIGURE 1. LP38691-ADJ Functional Diagram (LLP)

20126807

FIGURE 2. LP38693-ADJ Functional Diagram (SOT-223, LLP)

www.national.com

Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693-ADJ only), V_O= 1.25V, V_IN= 2.7V, I_L= 10mA.

Noise vs Frequency

Ripple Rejection

Noise vs Frequency

Ripple Rejection

20126836

20126835

20126817

20126837

20126819

20126821

www.national.com

Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693-ADJ only), V_O= 1.25V, V_IN= 2.7V, I_L= 10mA. (Continued)

V_REFvs Temperature

Line Transient Response

20126823

20126830

Line Transient Response

20126824

20126825

Line Transient Response

20126826

20126827

www.national.com

Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693-ADJ only), V_O= 1.25V, V_IN= 2.7V, I_L= 10mA. (Continued)

Line Transient Response

Load Transient Response

20126828

20126842

Load Transient Response

Enable Voltage vs Temperature

20126844

20126853

Load Regulation vs Temperature

Line Regulation vs Temperature

20126854

20126855

www.national.com

Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693-ADJ only), V_O= 1.25V, V_IN= 2.7V, I_L= 10mA. (Continued)

Dropout Voltage vs I_OUT

MIN V_INvs I_OUT

(V_OUT= 1.8V)

20126857

20126856

www.national.com

Z5U and Y5V dielectric ceramics have capacitance that

drops severely with applied voltage. A typical Z5U or Y5V

capacitor can lose 60% of its rated capacitance with half of

the rated voltage applied to it. The Z5U and Y5V also exhibit

a severe temperature effect, losing more than 50% of nomi-

nal capacitance at high and low limits of the temperature

range.

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are re-

quired to assure stability. These capacitors must be correctly

selected for proper performance.

INPUT CAPACITOR: An input capacitor of at least 1µF is

required (ceramic recommended). The capacitor must be

located not more than one centimeter from the input pin and

returned to a clean analog ground.

X7R and X5R dielectric ceramic capacitors are strongly rec-

ommended if ceramics are used, as they typically maintain a

capacitance range within 20% of nominal over full operat-

ing ratings of temperature and voltage. Of course, they are

typically larger and more costly than Z5U/Y5U types for a

given voltage and capacitance.

OUTPUT CAPACITOR: An output capacitor is required for

loop stability. It must be located less than 1 centimeter from

the device and connected directly to the output and ground

pins using traces which have no other currents flowing

through them.

TANTALUM: Solid Tantalum capacitors have good tempera-

ture stability: a high quality Tantalum will typically show a

capacitance value that varies less than 10-15% across the

full temperature range of -40˚C to 125˚C. ESR will vary only

about 2X going from the high to low temperature limits.

The minimum amount of output capacitance that can be

used for stable operation is 1µF. Ceramic capacitors are

recommended (the LP38691/3-ADJ was designed for use

with ultra low ESR capacitors). The LP38691/3-ADJ is stable

with any output capacitor ESR between zero and 100 Ohms.

The increasing ESR at lower temperatures can cause oscil-

lations when marginal quality capacitors are used (if the ESR

of the capacitor is near the upper limit of the stability range at

room temperature).

SETTING THE OUTPUT VOLTAGE: The output voltage is

set using the external resistors R1 and R2 (see Typical

Application Circuit). The output voltage will be given by the

equation:

PCB LAYOUT

Good PC layout practices must be used or instability can be

induced because of ground loops and voltage drops. The

input and output capacitors must be directly connected to the

input, output, and ground pins of the regulator using traces

which do not have other currents flowing in them (Kelvin

connect).

V_OUT= V_ADJX (1 + R1/R2)

Because the part has a minimum load current requirement of

100 µA, it is recommended that R2 always be 12k Ohms or

less to provide adequate loading. Even if a minimum load is

always provided by other means, it is not recommended that

very high value resistors be used for R1 and R2 because it

can make the ADJ node susceptible to noise pickup. A

maximum Ohmic value of 100k is recommended for R2 to

prevent this from occurring.

The best way to do this is to lay out C_INand C_OUTnear the

device with short traces to the V_IN, V_OUT, and ground pins.

The regulator ground pin should be connected to the exter-

nal circuit ground so that the regulator and its capacitors

have a "single point ground".

ENABLE PIN (LP38693-ADJ only): The LP38693-ADJ has

an enable pin which turns the regulator output on and off.

Pulling the enable pin down to a logic low will turn the part

off. The voltage the pin has to be pulled up to in order to

assure the part is on depends on input voltage (refer to

Electrical Characteristics section). This pin should be tied to

V_INif the enable function is not used.

It should be noted that stability problems have been seen in

applications where "vias" to an internal ground plane were

used at the ground points of the IC and the input and output

capacitors. This was caused by varying ground potentials at

these nodes resulting from current flowing through the

ground plane. Using a single point ground technique for the

regulator and it’s capacitors fixed the problem. Since high

current flows through the traces going into V_INand coming

from V_OUT, Kelvin connect the capacitor leads to these pins

so there is no voltage drop in series with the input and output

capacitors.

FOLDBACK CURRENT LIMITING: Foldback current limit-

ing is built into the LP38691/3-ADJ which reduces the

amount of output current the part can deliver as the output

voltage is reduced. The amount of load current is dependent

on the differential voltage between V_INand V_OUT. Typically,

when this differential voltage exceeds 5V, the load current

will limit at about 350 mA. When the V_IN-V_OUTdifferential is

reduced below 4V, load current is limited to about 850 mA.

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic

interference) can degrade any integrated circuit’s perfor-

mance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high fre-

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and varia-

tion with temperature must be taken into consideration when

selecting a capacitor so that the minimum required amount

of capacitance is provided over the full operating tempera-

ture range.

quency energy content ( 1 MHz), care must be taken to

ensure that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the

output of a switching regulator), good ceramic bypass ca-

pacitors must be used at the input pin of the IC.

Capacitor Characteristics

CERAMIC: For values of capacitance in the 10 to 100 µF

range, ceramics are usually larger and more costly than

tantalums but give superior AC performance for bypassing

high frequency noise because of very low ESR (typically less

than 10 mΩ). However, some dielectric types do not have

good capacitance characteristics as a function of voltage

and temperature.

If a load is connected to the IC output which switches at high

speed (such as a clock), the high-frequency current pulses

required by the load must be supplied by the capacitors on

the IC output. Since the bandwidth of the regulator loop is

less than 100 kHz, the control circuitry cannot respond to

www.national.com

OUTPUT NOISE

Application Hints (Continued)

Noise is specified in two ways- Spot Noise or Output Noise

density is the RMS sum of all noise sources, measured at

the regulator output, at a specific frequency (measured with

a 1Hz bandwidth). This type of noise is usually plotted on a

curve as a function of frequency. Total Output Noise or

Broad-Band Noise is the RMS sum of spot noise over a

specified bandwidth, usually several decades of frequencies.

load changes above that frequency. This means the effective

output impedance of the IC at frequencies above 100 kHz is

determined only by the output capacitor(s).

In applications where the load is switching at high speed, the

output of the IC may need RF isolation from the load. It is

recommended that some inductance be placed between the

output capacitor and the load, and good RF bypass capaci-

tors be placed directly across the load.

Attention should be paid to the units of measurement. Spot

noise is measured in units µV/root-Hz or nV/root-Hz and total

output noise is measured in µV(rms)

PCB layout is also critical in high noise environments, since

RFI/EMI is easily radiated directly into PC traces. Noisy

circuitry should be isolated from "clean" circuits where pos-

sible, and grounded through a separate path. At MHz fre-

quencies, ground planes begin to look inductive and RFI/

EMI can cause ground bounce across the ground plane. In

multi-layer PCB applications, care should be taken in layout

so that noisy power and ground planes do not radiate directly

into adjacent layers which carry analog power and ground.

The primary source of noise in low-dropout regulators is the

internal reference. Noise can be reduced in two ways: by

increasing the transistor area or by increasing the current

drawn by the internal reference. Increasing the area will

decrease the chance of fitting the die into a smaller package.

Increasing the current drawn by the internal reference in-

creases the total supply current (ground pin current).

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

6-lead, LLP Package

NS Package Number SDE06A

SOT-223 Package

NS Package Number MP05A

www.national.com

Notes

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship

Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned

Substances’’ as defined in CSP-9-111S2.

National Semiconductor

Americas Customer

Support Center

National Semiconductor

Europe Customer Support Center

Fax: +49 (0) 180-530 85 86

National Semiconductor

Asia Pacific Customer

Support Center

National Semiconductor

Japan Customer Support Center

Fax: 81-3-5639-7507

Email: new.feedback@nsc.com

Tel: 1-800-272-9959

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

Email: jpn.feedback@nsc.com

Tel: 81-3-5639-7560

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LP38691SD-ADJ相关文章

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LP38691SD-ADJ/NOPB产品参数

型号:	LP38691SD-ADJ/NOPB
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	HVSON, SOLCC6,.13,38
针数：	6
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.72
可调性：	ADJUSTABLE
标称回动电压 1：	0.25 V
最大输入电压：	10 V
最小输入电压：	2.7 V
JESD-30 代码：	S-PDSO-N6
JESD-609代码：	e4
长度：	3 mm
最大电网调整率 (%/V)：	0.1
最大负载调整率 (%)：	2.5%
湿度敏感等级：	1
功能数量：	1
输出次数：	1
端子数量：	6
工作温度TJ-Max：	125 °C
工作温度TJ-Min：	-40 °C
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流 1：	0.5 A
最大输出电压 1：	9 V
最小输出电压 1：	1.25 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVSON
封装等效代码：	SOLCC6,.13,38
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：	TR
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
调节器类型：	ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：	0.8 mm
子类别：	Other Regulators
表面贴装：	YES
技术：	CMOS
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.95 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm
Base Number Matches：	1

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