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产品型号LP3972的Datasheet PDF文件预览

September 2006  
LP3972  
Power Management Unit for Advanced Application  
Processors  
General Description  
Features  
n Compatible with advanced applications processors  
requiring DVM (Dynamic Voltage Management)  
n Three buck regulators for powering high current  
processor functions or I/O’s  
The LP3972 is a multi-function, programmable Power Man-  
agement Unit, designed especially for advanced application  
processors. The LP3972 is optimized for low power hand-  
held applications and provides 6 low dropout, low noise  
linear regulators, three DC/DC magnetic buck regulators, a  
back-up battery charger and two GPIO’s. A high speed serial  
interface is included to program individual regulator output  
voltages as well as on/off control.  
n 6 LDO’s for powering RTC, peripherals, and I/O’s  
n Backup battery charger with automatic switch for  
lithium-manganese coin cell batteries and Super  
capacitors  
n I2C compatible high speed serial interface  
n Software control of regulator functions and settings  
n Precision internal reference  
Key Specifications  
Buck Regulators  
n Thermal overload protection  
n Current overload protection  
n Programmable VOUT from 0.725 to 3.3V  
n Up to 95% efficiency  
n Tiny 40-pin 5x5 mm LLP package  
n Up to 1.6A output current  
n
3% output voltage accuracy  
Applications  
LDO’s  
n PDA phones  
n Programmable VOUT of 1.0V–3.3V  
n Smart phones  
n Personal Media Players  
n Digital cameras  
n Application processors  
— Intel Xscale  
n
3% output voltage accuracy  
n 150/300/400 mA output currents  
— LDO RTC 30 mA  
— LDO 1 300 mA  
— LDO 2 150 mA  
— LDO 3 150 mA  
— Freescale  
— LDO 4 150 mA  
— Samsung  
— LDO 5 400 mA  
n 100 mV (typ) dropout  
© 2006 National Semiconductor Corporation  
DS202076  
www.national.com  
Simplified Application Circuit  
20207601  
www.national.com  
2
Simplified Application Circuit (Continued)  
20207628  
The I2C lines are pulled up via a I/O source  
VINLDO4, 5 can either be powered from main battery source, or by a buck regulator or VIN  
.
3
www.national.com  
Connection Diagrams and Package Mark Information  
40-Pin Leadless Leadframe Package  
NS Package Number SQF40A  
20207602  
Note: Circle marks pin 1 position.  
Package Mark  
20207604  
Top View  
Note: The actual physical placement of the package marking will vary from part to part.  
(*) UZTTYY format: ’U’ — wafer fab code; ’Z’ — assembly code; ’XY’ 2 digit date code; ’TT’ — die run code.  
See http://www.national.com/quality/marking_convertion.html for more information on marking information.  
www.national.com  
4
Ordering Information  
Voltage Option  
Order Number  
Package Type  
NSC Package Package Marking  
Drawing  
Supplied As  
Voltage A514  
Voltage A514  
Voltage A413  
Voltage A413  
Voltage E514  
Voltage E514  
Voltage I514  
Voltage I514  
LP3972SQ-A514  
LP3972SQX-A514  
LP3972SQ-A413  
LP3972SQX-A413  
LP3972SQ-E514  
LP3972SQX-E514  
LP3972SQ-I514  
LP3972SQX-I514  
40 lead LLP  
40 lead LLP  
40 lead LLP  
40 lead LLP  
40 lead LLP  
40 lead LLP  
40 lead LLP  
40 lead LLP  
SQF040A  
SQF040A  
SQF040A  
SQF040A  
SQF040A  
SQF040A  
SQF040A  
SQF040A  
72-A514  
72-A514  
72-A413  
72-A413  
72-E514  
72-E514  
72-I514  
72-I514  
1000 tape & reel  
4500 tape & reel  
1000 tape & reel  
4500 tape & reel  
1000 tape & reel  
4500 tape & reel  
1000 tape & reel  
4500 tape & reel  
20207605  
Default VOUT Coding  
Z
0
1
2
3
4
5
6
7
8
9
Default VOUT  
1.3  
1.8  
2.5  
2.8  
3.0  
3.3  
1.0  
1.4  
1.2  
1.25  
5
www.national.com  
Pin Descriptions  
Pin #  
Name  
I/O  
Type  
Description  
1
PWR_ON  
I
D
CPU Wakeup input, this can be a push button event to indicate the  
device has been turned on. Phone / PDA main power button. Signal  
is debounced internally on the PMIC.  
If the POWER_ON is held low this will indicate to the PMIC to turn  
off. Active high Polarity  
2
3
4
nTEST_JIG  
SPARE  
I
I
D
D
D
This is a input signal used for a turn on event coming from the bed  
of nails tester during production. Active low polarity.  
CPU Wakeup input to indicate that a HW external event has  
occurred, i.e. flipping the cell phone to power up the display.  
This signal is asserted when DC POWER source has been  
asserted, or when the PWR_ON button is held down to turn off the  
PMIC. Wake up on power detection, and power down detection.  
Buck1 input feedback terminal  
EXT_WAKEUP  
O
5
6
7
8
9
FB1  
VIN  
I
I
A
PWR  
PWR  
PWR  
D
Battery Input (Internal circuitry and LDO1-3 power input)  
LDO1 output  
VOUT LDO1  
VOUT LDO2  
nRSTI  
O
O
I
LDO2 output  
Active low Reset pin. Signal used to reset the IC (by default is  
pulled high internally). Typically a push button reset.  
Ground  
10  
11  
12  
13  
14  
GND1  
VREF  
G
O
O
O
I
G
A
Bypass Cap. for the high internal impedance reference.  
LDO3 output  
VOUT LDO3  
VOUT LDO4  
VIN LDO4  
PWR  
PWR  
PWR  
LDO4 output  
Power input to LDO4, this can be connected to either from a 1.8V  
supply to main Battery supply.  
15  
16  
VIN BUBATT  
VOUT  
I
PWR  
PWR  
Back Up Battery input supply.  
O
LDO_RTC output supply to the RTC of the application processor.  
LDO_RTC  
nBATT_FLT  
17  
O
D
Main Battery fault output, indicates the main battery is low  
(discharged) or the dc source has been removed from the system.  
This gives the processor an indicator that the power will shut down.  
During this time the processor will operate from the back up coin  
cell.  
18  
19  
20  
21  
22  
23  
24  
25  
26  
PGND2  
SW2  
G
O
I
G
PWR  
PWR  
D
Buck2 NMOS Power Ground  
Buck2 switcher output  
VIN Buck2  
SDA  
Battery input power to Buck2  
I2C Data (Bidirectional)  
I2C Clock  
I/O  
I
SCL  
D
FB2  
I
A
Buck2 input feedback terminal  
nRSTO  
VOUT LDO5  
VIN LDO5  
O
O
I
D
Reset output from the PMIC to the processor  
LDO5 output  
PWR  
PWR  
Power input to LDO5, this can be connected to VIN or to a separate  
1.8V supply.  
27  
28  
29  
VDDA  
FB3  
I
I
PWR  
A
Analog Power for VREF, BIAS  
Buck3 Feedback  
GPIO1 /  
nCHG_EN  
I/O  
D
General Purpose I/O / Ext. backup battery charger enable pin. This  
pin enables the main battery / DC source power to charge the  
backup battery. This pin toggled via the application processor. By  
grounding this pin the DC source continuously charges the backup  
battery  
30  
31  
GPIO2  
I/O  
I
D
General Purpose I/O  
VIN Buck3  
PWR  
Battery input power to Buck3  
www.national.com  
6
Pin Descriptions (Continued)  
Pin #  
32  
Name  
SW3  
I/O  
O
G
G
I
Type  
PWR  
G
Description  
Buck3 switcher output  
33  
PGND3  
BGND1,2,3  
SYNC  
Buck3 NMOS Power Ground  
34  
G
Bucks 1, 2 and 3 analog Ground  
35  
D
Frequency Synchronization: Connection to an external clock signal  
PLL to synchronize the PMIC internal oscillator.  
Input Digital enable pin for the high voltage power domain supplies.  
Output from the Monahans processor.  
36  
SYS_EN  
I
D
Digital enable pin for the Low Voltage domain supplies. Output  
signal from the Monahans processor  
37  
38  
39  
40  
PWR_EN  
PGND1  
SW1  
I
D
G
O
I
G
Buck1 NMOS Power Ground  
PWR  
Buck1 Switcher output  
VIN Buck1  
PWR  
Battery input power to Buck1  
A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin  
Note: In this document active low logic items are prefixed with a lowercase “n”  
7
www.national.com  
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
ESD Rating (Note 5)  
Human Body Model  
Machine Model  
2 kV  
200V  
All Inputs  
−0.3V to +6.5V  
0.3V  
Operating Ratings  
VIN LDO 4,5  
GND to GND SLUG  
Junction Temperature (TJ-MAX  
Storage Temperature  
Power Dissipation  
2.7V to 5.5V  
1.74 to (VIN  
)
150˚C  
VEN  
−65˚C to +150˚C  
Junction Temperature (TJ)  
Operating Temperature (TA)  
Maximum Power Dissipation  
(TA = 70˚C) (Notes 3, 4)  
−40˚C to +125˚C  
−40˚C to +85˚C  
(TA = 70˚C) (Note 3)  
Junction-to-Ambient Thermal  
Resistance θJA (Note 3)  
3.2W  
2.2W  
25˚C/W  
260˚C  
Maximum Lead Temp (Soldering)  
General Electrical Characteristics Typical values and limits appearing in normal type apply for  
TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C.  
(Notes 2, 6)  
Symbol  
Parameter  
Battery Voltage  
Conditions  
Min  
2.7  
Typ  
3.6  
3.6  
160  
20  
Max  
5.5  
Units  
V
V
IN, VDDA, VIN Buck1, 2 and 3  
INLDO4, VINLDO5  
V
V
Power Supply for LDO 4 and 5  
Thermal Shutdown (Note 14)  
1.74  
5.5  
TSD  
Temperature  
Hysteresis  
˚C  
**No input supply should be higher then VDDA  
Supply Specifications (Notes 2, 5)  
IMAX  
VOUT (Volts)  
Maximum Current  
Supply  
Range  
Resolution  
Current (mA)  
(V)  
(mV)  
30 mA dc source 10 mA backup  
LDO_RTC  
LDO1 (VCC_MVT)  
LDO2  
2.8V  
N/A  
25  
source  
300  
1.7 to 2.0  
1.8 to 3.3  
1.8 to 3.3  
1.0 to 3.3  
100  
150  
LDO3  
100  
150  
LDO4  
50-600  
25  
150  
LDO5 (VCC_SRAM)  
BUCK 1 (VCC_APPS)  
BUCK 2  
0.850 to 1.5  
0.725 to 1.5  
0.8 to 3.3  
400  
25  
1600  
1600  
1600  
50-600  
50-600  
BUCK 3  
0.8 to 3.3  
www.national.com  
8
General Electrical Characteristics Typical values and limits appearing in normal type apply for  
TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C.  
(Notes 2, 6) (Continued)  
Default Voltage Option (Notes 2, 5)  
Version  
Enable  
LDO_RTC  
LDO1  
LP3972SQ-A514  
LP3972SQ-A413  
Version A  
Version A  
2.8  
1.8  
1.8D  
3D  
2.8  
1.8  
1.8D  
3D  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
PWR_EN  
PWR_EN  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
PWR_EN  
PWR_EN  
SYS_EN  
SYS_EN  
LDO2  
LDO3  
LDO4  
3D  
2.8D  
1.4  
1.4  
3
LDO5  
1.4  
1.4  
3.3  
1.8  
BUCK1  
BUCK2  
BUCK3  
1.8  
Version  
Enable  
LDO_RTC  
LDO1  
LP3972SQ-E514  
LP3972SQ-I514  
Version E  
Version I  
2.8  
1.8  
1.8E  
3D  
2.8  
1.8  
1.8E  
3E  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
PWR_EN  
PWR_EN  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
PWR_EN  
PWR_EN  
SYS_EN  
SYS_EN  
LDO2  
LDO3  
LDO4  
3D  
3E  
LDO5  
1.4  
1.4  
3.3  
1.8  
1.4  
1.4  
3.3  
1.8  
BUCK1  
BUCK2  
BUCK3  
Note : E = Regulator is ENABLED during startup  
D = Regulator is DISABLED during startup  
9
www.national.com  
LDO RTC  
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF, COUT (VRTC) = 1.0 µF ceramic. Typical values and limits  
appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature  
range for operation, −40˚C to +125˚C. (Notes 2, 6, 7) and (Note 10)  
Symbol  
VOUT  
Parameter  
Conditions  
VIN Connected, Load Current =  
1 mA  
Min  
Typ  
Max  
Units  
Output Voltage Accuracy  
2.632  
2.8  
2.968  
V
Accuracy  
VOUT  
Line Regulation  
Load Regulation  
VIN = (VOUT nom + 1.0V) to 5.5V  
(Note 11) Load Current = 1 mA  
From Main Battery  
0.15  
0.05  
0.5  
%/V  
Load Current = 1 mA to 30 mA  
From Backup Battery  
VIN = 3.0V  
%/mA  
Load Current = 1 mA to 10 mA  
From Main Battery  
ISC  
Short Circuit Current Limit  
Dropout Voltage  
100  
30  
VIN = VOUT +0.3V to 5.5V  
From Backup Battery  
Load Current = 10 mA  
mA  
mV  
VIN  
-
375  
VOUT  
IQ_Max  
TP1  
Maximum Quiescent Current  
RTC LDO Input Switched from  
Main Battery to Backup Battery  
RTC LDO Input Switched from  
Backup Battery to Main Battery  
Output Capacitor  
IOUT = 0 mA  
VIN Falling  
30  
µA  
V
2.9  
TP2  
CO  
VIN Rising  
3.0  
1.0  
V
Capacitance for Stability  
ESR  
0.7  
5
µF  
500  
mΩ  
www.national.com  
10  
LDO 1 to 5  
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF, COUT (VRTC) = 1.0 µF ceramic. Typical values and limits  
appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature  
range for operation, −40˚C to +125˚C. (Notes 2, 6, 7, 10, 11, 15) and (Note 16).  
Symbol  
Parameter  
Conditions  
Min  
−3  
Typ  
Max  
3
Units  
VOUT  
Output Voltage Accuracy (Default  
Load Current = 1 mA  
%
Accuracy VOUT  
)
VOUT  
Line Regulation  
VIN =3.1V to 5.0V, (Note 11) Load  
Current = 1 mA  
0.15  
%/V  
Load Regulation  
VIN = 3.6V,  
0.011  
%/mA  
Load Current = 1 mA to IMAX  
LDO1–4, VOUT = 0V  
ISC  
Short Circuit Current Limit  
Dropout Voltage  
400  
500  
mA  
mV  
LDO5, VOUT = 0V  
VIN  
-
Load Current = 50 mA (Note 7)  
150  
VOUT  
PSRR  
IQ  
Power Supply Ripple Rejection  
Quiescent Current “On”  
Quiescent Current “On”  
Quiescent Current “Off”  
Turn On Time  
f = 10 kHz, Load Current = IMAX  
IOUT = 0 mA  
45  
40  
dB  
µA  
IOUT = IMAX  
60  
EN is de-asserted  
Start up from Shut-down  
Capacitance for Stability  
0˚C TJ 125˚C  
−40˚C TJ 125˚C  
ESR  
0.03  
300  
0.47  
TON  
µsec  
µF  
COUT  
Output Capacitor  
0.33  
0.68  
5
1.0  
500  
mΩ  
LDO dropout voltage vs. Load Current collect data for all LDO’s  
Dropout Voltage vs. Load Current  
Change in Output Voltage vs. Load Current  
20207629  
20207630  
11  
www.national.com  
LDO 1 to 5 (Continued)  
LDO1 Line Regulation  
LDO1 Load Transient  
VOUT = 1.8 volts VIN 3 to 4 volts Load = 100 mA  
VIN = 4.1 volts VOUT = 1.8 volts no-load-100 mA  
20207631  
20207632  
Enable Start-up time (LDO1)  
LDO1 channel 2 LDO4 Channel 1 Sys_enable from 0  
volts Load = 100mA  
20207633  
www.national.com  
12  
Buck Converters SW1, SW2, SW3  
Unless otherwise noted, VIN = 3.6V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in  
normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for opera-  
tion, −40˚C to +125˚C. (Notes 2, 6, 12) and (Note 13).  
Symbol  
VOUT  
Parameter  
Output Voltage Accuracy  
Efficiency  
Conditions  
Default VOUT  
Min  
Typ  
Max  
Units  
%
−3  
+3  
Eff  
Load Current = 500 mA  
EN is de-asserted  
95  
0.1  
13  
%
ISHDN  
Shutdown Supply Current  
Sync Mode Clock Frequency  
µA  
Synchronized from 13 MHz System  
Clock  
10.4  
15.6  
2.4  
MHz  
fOSC  
IPEAK  
IQ  
Internal Oscillator Frequency  
Peak Switching Current Limit  
Quiescent Current “On”  
2.0  
2.1  
MHz  
A
No Load PFM Mode  
No Load PWM Mode  
21  
µA  
200  
240  
200  
500  
RDSON (P)  
RDSON (N)  
TON  
Pin-Pin Resistance PFET  
Pin-Pin Resistance NFET  
Turn On Time  
mΩ  
mΩ  
µsec  
µF  
Start up from Shut-down  
Capacitance for Stability  
Capacitance for Stability  
CIN  
Input Capacitor  
8
8
CO  
Output Capacitor  
µF  
Buck 1 Output Efficiency vs. Load Current Varied from 1mA to 1.5 Amps  
VIN = 3, 3.5 volts VOUT = 1.4 volts Forced PWM  
VIN = 4.0-4.5 volts VOUT = 1.4 volts Forced PWM  
20207634  
20207635  
Line Transient Response  
VIN = 3, 3.5 volts VOUT = 1.4 volts Forced PWM  
VIN = 3 – 3.6 V, VOUT = 1.2 V, 250 mA load  
20207637  
20207636  
13  
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Buck Converters SW1, SW2, SW3 (Continued)  
Mode Change  
Load Transient  
3.6 VIN, 3.3 VOUT, 0 – 100 mA load  
Load transients 20 mA to 560 mA  
VOUT = 1.4 volts [PFM to PWM] VIN = 4.1 volts  
20207638  
20207639  
Startup  
Startup into PWM Mode 980 mA [channel 2]  
VOUT = 1.4 volts VIN = 4.1 volts  
20207638  
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14  
Back-Up Charger Electrical Characteristics  
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits ap-  
pearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 6) and  
(Note 8).  
Symbol  
VIN  
Parameter  
Conditions  
Voltage at VIN  
Min  
3.3  
Typ  
Max  
5.5  
Units  
V
Operational Voltage Range  
Backup Battery Charging Current  
IOUT  
VIN = 3.6V, Backup_Bat = 2.5V,  
Backup Battery Charger Enabled  
(Note 8)  
190  
µA  
VOUT  
Charger Termination Voltage  
VIN = 5.0V Backup Battery Charger  
Enabled. Programmable  
2.91  
3.1  
9
V
Backup Battery Charger Short  
Circuit Current  
Backup_Bat = 0V, Backup Battery  
Charger Enabled  
mA  
dB  
PSRR  
Power Supply Ripple Rejection  
Ratio  
IOUT 50 µA, VOUT = 3.15V  
VOUT + 0.4 VBATT = VIN 5.0V  
15  
<
f
10 kHz  
<
IQ  
Quiescent Current  
IOUT 50 µA  
25  
µA  
µF  
COUT  
Output Capacitance  
Output Capacitor ESR  
0 µA IOUT 100 µA  
0.1  
5
500  
mΩ  
LP3972 BATTERY SWITCH OPERATION  
The LP3972 has provisions for two battery connections, the main battery Vbat and Backup Battery  
The function of the battery switch is to connect power to the RTC LDO from the appropriate battery, depending on conditions  
described below:  
If only the backup battery is applied, the switch will automatically connect the RTC LDO power to this battery.  
If only the main battery is applied, the switch will automatically connect the RTC LDO power to this battery  
>
If both batteries are applied, and the main battery is sufficiently charged (Vbat 3.1V), the switch will automatically connect  
the RTC LDO power to the main battery.  
As the main battery is discharged a separate circuit called nBATT_FLT will warn the system. Then if no action is taken to  
restore the charge on the main battery, and discharging is continued the battery switch will disconnect the input of the RTC_LDO  
from the main battery and connect to the backup battery.  
The main battery voltage at which the RTC LDO is switched over from main to backup battery is 2.8V typically.  
There is a hysteric voltage in this switch operation so; the RTC LDO will not be reconnected to main battery until main battery  
voltage is greater than 3.1V typically.  
The system designer may wish to disable the battery switch when only a main battery is used. This is accomplished by setting  
the “no back up battery bit” in the control register 8h’0B bit 7 NBUB. With this bit set to “1”, the above described switching will not  
occur, that is the RTC LDO will remain connected to the main battery even as it is discharged below the 2.9V threshold. The  
Backup battery input should also be connected to main battery.  
15  
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Logic Inputs and Outputs DC Operating Conditions (Note 2)  
Logic Inputs (SYS_EN, PWR_EN, SYNC, nRSTI, PWR_ON, nTEST_JIG, SPARE and GPI’s)  
Symbol  
VIL  
Parameter  
Low Level Input Voltage  
High Level Input Voltage  
Conditions  
Min  
Max  
0.5  
Units  
V
V
VIH  
VRTC  
−0.5V  
−1  
ILEAK  
Input Leakage Current  
+1  
µA  
Logic Outputs (nRSTO, EXT_WAKEUP and GPO’s)  
Symbol Parameter  
VOL Output Low Level  
Conditions  
Load = +0.2 mA = IOL Max  
Load = −0.1 mA = IOL Max  
Min  
Max  
0.5  
Units  
V
V
VOH  
Output High Level  
VRTC  
−0.5V  
ILEAK  
Output Leakage Current  
VON = VIN  
+5  
µA  
Logic Output (nBATT_FLT)  
Symbol Parameter  
Conditions  
Programmable via Serial Interface  
Default = 2.8V  
Min  
2.4  
Typ  
Max  
3.4  
Units  
nBATT_FLT Threshold Voltage  
2.8  
V
VOL  
Output Low Level  
Output High Level  
Load = +0.4 mA = IOL Max  
Load = −0.2 mA = IOH Max  
0.5  
+5  
V
V
VOH  
VRTC  
−0.5V  
ILEAK  
Input Leakage Current  
µA  
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16  
I2C Compatible Serial Interface Electrical Specifications (SDA and SCL)  
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in  
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 6) and (Note 9)  
Symbol  
VIL  
Parameter  
Low Level Input Voltage  
High Level Input Voltage  
Low Level Output Voltage  
Low Level Output Current  
Clock Frequency  
Conditions  
Min  
−0.5  
0.7 VRTC  
0
Typ  
Max  
Units  
(Note 14)  
(Note 14)  
(Note 14)  
0.3 VRTC  
VRTC  
V
VIH  
VOL  
0.2 VTRC  
IOL  
VOL = 0.4V (Note 14)  
(Note 14)  
3.0  
mA  
kHz  
µs  
FCLK  
tBF  
400  
Bus-Free Time Between Start and Stop (Note 14)  
1.3  
0.6  
1.3  
0.6  
0.6  
0
tHOLD  
tCLKLP  
tCLKHP  
tSU  
Hold Time Repeated Start Condition  
CLK Low Period  
(Note 14)  
(Note 14)  
(Note 14)  
(Note 14)  
(Note 14)  
(Note 14)  
(Note 14)  
(Note 14)  
µs  
µs  
CLK High Period  
µs  
Set Up Time Repeated Start Condition  
µs  
tDATAHLD Data Hold Time  
µs  
tCLKSU  
TSU  
Data Set Up Time  
100  
0.6  
ns  
Set Up Time for Start Condition  
Maximum Pulse Width of Spikes that  
Must be Suppressed by the Input Filter  
of Both DATA & CLK Signals  
µs  
TTRANS  
50  
ns  
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device  
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical  
Characteristics tables.  
Note 2: All voltages are with respect to the potential at the GND pin.  
Note 3: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be  
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power  
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ ), as given by the  
JA  
following equation: TA-MAX = TJ-MAX-OP – (θ x PD-MAX).  
JA  
Note 4: Junction-to-ambient thermal resistance (θ ) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC  
JA  
standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board  
is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22˚C, still air. Power  
dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation  
exists, special care must be paid to thermal dissipation issues in board design. The value of θ of this product can vary significantly, depending on PCB material,  
JA  
layout, and environmental conditions. In applications where high maximum power dissipation exists (high V , high I  
), special care must be paid to thermal  
IN  
OUT  
dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and  
Power Dissipation section of this datasheet.  
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 k ??? resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200  
pF capacitor discharged directly into each pin. (EAIJ)  
Note 6: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are production  
tested, guaranteed through statistical analysis or guaranteed by design. All limits at temperature extremes are guaranteed via correlation using standard Statistical  
Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).  
Note 7: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.  
2
Note 8: Back-up battery charge current is programmable via the I C compatible interface. Refer to the Application Section for more information.  
2
Note 9: The I C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kto 20 krange.  
Note 10: LDO_RTC voltage can track LDO3 voltage. LP3972 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track LDO3 voltage  
within 200mV down to 2.8V when LDO3 is enabled  
Note 11: V minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages below the minimum  
IN  
input operating voltage.  
Note 12: The input voltage range recommended for ideal applications performance for the specified output voltages is given below:  
<
<
OUT  
V
IN  
V
IN  
= 2.7V to 5.5V for 0.80V  
V
1.8V  
+ 1V) to 5.5V for 1.8V V 3.3V  
OUT  
= (V  
OUT  
Note 13: Test condition: for V  
less than 2.7V, V = 3.6V; for V  
greater than or equal to 2.7V, V = V  
+ 1V.  
OUT  
OUT  
IN  
OUT  
IN  
Note 14: This electrical specification is guaranteed by design.  
Note 15: An increase in the load current results in a slight decrease in the output voltage and vice versa.  
Note 16: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply  
for input voltages below 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5.  
17  
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NFET switch is turned on and the inductor current ramps  
down. The next cycle is initiated by the clock turning off the  
NFET and turning on the PFET.  
Buck Converter Operation  
DEVICE INFORMATION  
The LP3972 includes three high efficiency step down DC-DC  
switching buck converters. Using a voltage mode architec-  
ture with synchronous rectification, the buck converters have  
the ability to deliver up to 1600 mA depending on the input  
voltage, output voltage, ambient temperature and the induc-  
tor chosen.  
There are three modes of operation depending on the cur-  
rent required - PWM, PFM, and shutdown. The device oper-  
ates in PWM mode at load currents of approximately 100 mA  
or higher, having voltage tolerance of 3% with 95% effi-  
ciency or better. Lighter load currents cause the device to  
automatically switch into PFM for reduced current consump-  
tion. Shutdown mode turns off the device, offering the lowest  
current consumption (IQ, SHUTDOWN = 0.01 µA typ).  
Additional features include soft-start, under voltage protec-  
tion, current overload protection, and thermal shutdown  
protection.  
20207611  
The part uses an internal reference voltage of 0.5V. It is  
recommended to keep the part in shutdown until the input  
voltage is 2.7V or higher.  
FIGURE 1. Typical PWM Operation  
Internal Synchronous Rectification  
CIRCUIT OPERATION  
While in PWM mode, the converters uses an internal NFET  
as a synchronous rectifier to reduce rectifier forward voltage  
drop and associated power loss. Synchronous rectification  
provides a significant improvement in efficiency whenever  
the output voltage is relatively low compared to the voltage  
drop across an ordinary rectifier diode.  
The buck converter operates as follows. During the first  
portion of each switching cycle, the control block turns on the  
internal PFET switch. This allows current to flow from the  
input through the inductor to the output filter capacitor and  
load. The inductor limits the current to a ramp with a slope of  
(VIN–VOUT)/L, by storing energy in a magnetic field.  
Current Limiting  
During the second portion of each cycle, the controller turns  
the PFET switch off, blocking current flow from the input, and  
then turns the NFET synchronous rectifier on. The inductor  
draws current from ground through the NFET to the output  
filter capacitor and load, which ramps the inductor current  
down with a slope of –VOUT/L.  
A current limit feature allows the converters to protect itself  
and external components during overload conditions. PWM  
mode implements current limiting using an internal compara-  
tor that trips at 2.0 A (typ). If the output is shorted to ground  
the device enters a timed current limit mode where the NFET  
is turned on for a longer duration until the inductor current  
falls below a low threshold, ensuring inductor current has  
more time to decay, thereby preventing runaway.  
The output filter stores charge when the inductor current is  
high, and releases it when inductor current is low, smoothing  
the voltage across the load.  
The output voltage is regulated by modulating the PFET  
switch on time to control the average current sent to the load.  
The effect is identical to sending a duty-cycle modulated  
rectangular wave formed by the switch and synchronous  
rectifier at the SW pin to a low-pass filter formed by the  
inductor and output filter capacitor. The output voltage is  
equal to the average voltage at the SW pin.  
PFM OPERATION  
At very light loads, the converter enters PFM mode and  
operates with reduced switching frequency and supply cur-  
rent to maintain high efficiency.  
The part will automatically transition into PFM mode when  
either of two conditions occurs for a duration of 32 or more  
clock cycles:  
PWM OPERATION  
A: The inductor current becomes discontinuous.  
During PWM operation the converter operates as a voltage  
mode controller with input voltage feed forward. This allows  
the converter to achieve good load and line regulation. The  
DC gain of the power stage is proportional to the input  
voltage. To eliminate this dependence, feed forward in-  
versely proportional to the input voltage is introduced.  
B: The peak PMOS switch current drops below the IMODE  
<
level, (Typically IMODE 30 mA + VIN/42).  
While in PWM (Pulse Width Modulation) mode, the output  
voltage is regulated by switching at a constant frequency  
and then modulating the energy per cycle to control power to  
the load. At the beginning of each clock cycle the PFET  
switch is turned on and the inductor current ramps up until  
the comparator trips and the control logic turns off the switch.  
The current limit comparator can also turn off the switch in  
case the current limit of the PFET is exceeded. Then the  
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18  
nominal PWM output voltage. If the output voltage is below  
the “high” PFM comparator threshold, the PMOS power  
switch is turned on. It remains on until the output voltage  
reaches the ‘high’ PFM threshold or the peak current ex-  
ceeds the IPFM level set for PFM mode. The typical peak  
current in PFM mode is: IPFM = 112 mA + VIN/27. Once the  
PMOS power switch is turned off, the NMOS power switch is  
turned on until the inductor current ramps to zero. When the  
NMOS zero-current condition is detected, the NMOS power  
switch is turned off. If the output voltage is below the ‘high’  
PFM comparator threshold (see Figure 3), the PMOS switch  
is again turned on and the cycle is repeated until the output  
reaches the desired level. Once the output reaches the ‘high’  
PFM threshold, the NMOS switch is turned on briefly to ramp  
the inductor current to zero and then both output switches  
are turned off and the part enters an extremely low power  
mode. Quiescent supply current during this ‘sleep’ mode is  
21 µA (typ), which allows the part to achieve high efficiencies  
under extremely light load conditions. When the output drops  
below the ‘low’ PFM threshold, the cycle repeats to restore  
the output voltage (average voltage in PFM mode) to  
Buck Converter Operation (Continued)  
20207612  
FIGURE 2. Typical PFM Operation  
<
1.15% above the nominal PWM output voltage. If the load  
current should increase during PFM mode (see Figure 3)  
causing the output voltage to fall below the ‘low2’ PFM  
threshold, the part will automatically transition into fixed-  
frequency PWM mode. Typically when VIN = 3.6V the part  
transitions from PWM to PFM mode at 100 mA output  
current .  
During PFM operation, the converter positions the output  
voltage slightly higher than the nominal output voltage during  
PWM operation, allowing additional headroom for voltage  
drop during a load transient from light to heavy load. The  
PFM comparators sense the output voltage via the feedback  
pin and control the switching of the output FETs such that the  
<
<
output voltage ramps between 0.6% and 1.7% above the  
20207613  
FIGURE 3. Operation in PFM Mode and Transfer to PWM Mode  
SHUTDOWN MODE  
is recommended to disable the converter during the system  
power up and undervoltage conditions when the supply is  
less than 2.7V.  
During shutdown the PFET switch, reference, control and  
bias circuitry of the converters are turned off. The NFET  
switch will be open in shutdown to discharge the output.  
When the converter is enabled, EN, soft start is activated. It  
19  
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lenging in some critical applications to comply with stringent  
regulatory standards or simply to minimize interference to  
sensitive circuits in space limited portable systems. The  
regulator’s switching frequency and harmonics can cause  
“noise” in the signal spectrum. The magnitude of this noise is  
measured by its power spectral density. The power spectral  
density of the switching frequency, FC, is one parameter that  
system designers want to be as low as practical to reduce  
interference to the environment and subsystems within their  
products. The LP3972 has a user selectable function on  
chip, wherein a noise reduction technique known as “spread  
spectrum” can be employed to ease customer’s design and  
production issues.  
Buck Converter Operation (Continued)  
SOFT START  
The buck converter has a soft-start circuit that limits in-rush  
current during start-up. During start-up the switch current  
limit is increased in steps. Soft start is activated only if EN  
goes from logic low to logic high after VIN reaches 2.7V. Soft  
start is implemented by increasing switch current limit in  
steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch  
current limit). The start-up time thereby depends on the  
output capacitor and load current demanded at start-up.  
Typical start-up times with 10 µF output capacitor and 1000  
mA load current is 390 µs and with 1 mA load current  
its 295 µs.  
The principle behind spread spectrum is to modulate the  
switching frequency slightly and slowly, and spread the sig-  
nal frequency over a broader bandwidth. Thus, its power  
spectral density becomes attenuated, and the associated  
interference electro-magnetic energy is reduced. The clock  
used to modulate the LP3972 buck regulator can be used as  
a spread spectrum clock via 2 I2C control register (System  
Control Register 1 (SCR1) 8h’80) bits bk_ssen, and slomod.  
With this feature enabled, the intense energy of the clock  
frequency can be spread across a small band of frequencies  
in the neighborhood of the center frequency. The results in a  
reduction of the peak energy!  
LDO - LOW DROP OUT OPERATION  
The LP3672 can operate at 100% duty cycle (no switching;  
PMOS switch completely on) for low drop out support of the  
output voltage. In this way the output voltage will be con-  
trolled down to the lowest possible input voltage. When the  
device operates near 100% duty cycle, output voltage ripple  
is approximately 25 mV. The minimum input voltage needed  
to support the output voltage is  
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT  
ILOAD  
Load Current  
The LP3972 spread spectrum clock uses a triangular modu-  
lation profile with equal rise and fall slopes. The modulation  
has the following characteristics:  
RDSON, PFET  
Drain to source resistance of PFET  
switch in the triode region  
Inductor resistance  
The center frequency:  
The modulating frequency,  
Peak frequency deviation:  
Modulation index  
FC = 2 MHz, and  
fM = 6.8 kHz or 12 kHz.  
_f = 100 kHz (or 5%)  
β = _f/fM = 14.7 or 8.3  
RINDUCTOR  
SPREAD SPECTRUM FEATURE  
Periodic switching in the buck regulator is inherently a  
noisier function block compared to an LDO. It can be chal-  
Switching Energy RBW = 300 Hz  
20207641  
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20  
I2C Compatible Interface  
I2C DATA VALIDITY  
The data on SDA line must be stable during the HIGH period  
of the clock signal (SCL). In other words, state of the data  
line can only be changed when CLK is LOW.  
20207614  
I2C START and STOP CONDITIONS  
generates START and STOP bits. The I2C bus is considered  
to be busy after START condition and free after STOP con-  
dition. During data transmission, I2C master can generate  
repeated START conditions. First START and repeated  
START conditions are equivalent, function-wise.  
START and STOP bits classify the beginning and the end of  
the I2C session. START condition is defined as SDA signal  
transitioning from HIGH to LOW while SCL line is HIGH.  
STOP condition is defined as the SDA transitioning from  
LOW to HIGH while SCL is HIGH. The I2C master always  
20207615  
TRANSFERRING DATA  
After the START condition, a chip address is sent by the I2C  
master. This address is seven bits long followed by an eighth  
bit which is a data direction bit (R/W). The LP3972 address  
is 34h. For the eighth bit, a “0” indicates a WRITE and a “1”  
indicates a READ. The second byte selects the register to  
which the data will be written. The third byte contains data to  
write to the selected register.  
Every byte put on the SDA line must be eight bits long, with  
the most significant bit (MSB) being transferred first. The  
number of bytes that can be transmitted per transfer is  
unrestricted. Each byte of data has to be followed by an  
acknowledge bit. The acknowledge related clock pulse is  
generated by the master. The transmitter releases the SDA  
line (HIGH) during the acknowledge clock pulse. The re-  
ceiver must pull down the SDA line during the 9th clock  
pulse, signifying an acknowledge. A receiver which has been  
addressed must generate an acknowledge after each byte  
has been received.  
I2C CHIP ADDRESS - 7h’34  
MSB  
ADR6  
Bit7  
0
ADR5  
Bit6  
1
ADR4  
Bit5  
1
ADR3  
Bit4  
0
ADR2  
Bit3  
1
ADR1  
Bit2  
0
ADR0  
Bit1  
0
R/W  
Bit0  
R/W  
21  
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I2C Compatible Interface (Continued)  
Write Cycle  
Write cycle  
20207616  
Read Cycle  
When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.  
Read Cycle  
20207617  
w = write (SDA = “0”)  
r = read (SDA = “1”)  
ack = acknowledge (SDA pulled down by either master or slave)  
rs = repeated start  
id = 34h (Chip Address)  
I2C DVM Timing for VCC_APPS (Buck1)  
20207618  
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22  
I2C Compatible Interface (Continued)  
A Typical Multi-byte random register transfer is outlined  
below:  
MULTI-BYTE I2C COMMAND SEQUENCE  
Device Address, Register A Address, Ach, Register A  
Data, Ach Register M Address, Ach,  
Register M Data, Ach Register X  
Address, Ach, Register X Data, Ach  
Register Z Address, Ach, Register Z  
Data, Ach, Stop  
To correctly function with the Monahan’s Power Manage-  
ment I2C the LP3972’s I2C serial interface shall support  
Random register Multi-byte command sequencing: During a  
multi-byte write the Master sends the Start command fol-  
lowed by the Device address, which is sent only once,  
followed by the 8 Bit register address, then 8-bits of data.  
The I2C slave must then accept the next random register  
address followed by 8 bits of data and continue this process  
until the master sends a valid stop condition.  
Note: the PMIC is not required to see the I2C device address  
for each transaction. A, M, X, and Z are Random numbers.  
20207642  
INCREMENTAL REGISTER I2C COMMAND SEQUENCE  
byte has been sent. Address incrimination may be required  
for non XScale applications. User can define whether multi-  
byte (default) to random address or address incrimination  
will be used.  
The LP3972 supports address increment (burst mode).  
When you have defined register address n data bytes can be  
sent and register address is incremented after each data  
20207643  
23  
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I2C Compatible Interface (Continued)  
LP3972 CONTROL REGISTER  
Register Address  
8h’07  
8h’10  
8h’11  
Register Name  
SCR  
Read/Write  
R/W  
R/W  
R
Register Description  
System Control Register  
OVER1  
Output Voltage Enable Register 1  
Output Voltage Status Register 1  
Output Voltage Enable Register 2  
Output Voltage Status Register 2  
Voltage Change Control Register 1  
BUCK1 Target Voltage 1 Register  
BUCK1 DVM Target Voltage 2 Register  
OVSR1  
8h’12  
8h’13  
8h’20  
8h’23  
8h’24  
8h’25  
8h’26  
8h’27  
8h’29  
8h’2A  
8h’32  
8h’33  
8h’39  
8h’3A  
8h’80  
8h’81  
8h’82  
8h’83  
8h’84  
8h’85  
8h’86  
8h’87  
8h’88  
8h’89  
8h’8E  
8h’8F  
OVER2  
R/W  
R
OVSR2  
V
CC1  
R/W  
R/W  
R/W  
R/W  
W
ADTV1  
ADTV2  
AVRC  
V
CC_APPS Voltage Ramp Control  
CDTC1  
CDTC2  
SDTV1  
SDTV2  
MDTV1  
MDTV2  
L2VCR  
L34VCR  
SCR1  
Dummy Register  
W
Dummy Register  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
LDO5 Target Voltage 1  
LDO5 Target Voltage 2  
LDO1 Target Voltage 1 Register  
LDO1 Voltage 2 Register  
LDO2 Voltage Control Registers  
LDO3 & LDO4 Voltage Control Registers  
System Control Register 1  
System Control Register 2  
Output Voltage Enable Register 3  
Output Voltage Status Register 3  
Output Voltage Enable Register 3  
SCR2  
OEN3  
OSR3  
LOER4  
B2TV  
V
V
CC_Buck2 Target Voltage  
CC_Buck3 Target Voltage  
B3TV  
B32RC  
ISRA  
Buck 32 Voltage Ramp Control  
Interrupt Status Register A  
BCCR  
II1RR  
R/W  
R
Backup Battery Charger Control Register  
Internal 1 Revision Register  
II2RR  
R
Internal 2 Revision Register  
SERIAL INTERFACE REGISTER SELECTION CODES (Bold face voltages are default values)  
System Control Status Register  
Register is an 8 bit register which specifies the control bits for the PMIC clocks. This register works in conjunction with the SYNC  
pin where an external clock PLL buffer operating at 13 MHz is synchronized with the oscillators of the buck converters.  
System Control Register (SCR) 8h’07  
Bit  
7
6
5
4
Reserved  
0
3
2
1
0
CLK_SCL  
0
Designation  
Reset Value  
0
0
0
0
0
0
System Control Register (SCR) 8h’07 Definitions  
Bit  
7-1  
0
Access  
Name  
Description  
Reserved  
R/W  
CLK_SCL  
External Clock Select  
0 = Internal Oscillator clock for Buck Converters  
1 = External 13 MHz Oscillator clock for Buck Converters  
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24  
I2C Compatible Interface (Continued)  
OUTPUT VOLTAGE ENABLE REGISTER 1  
This register enables or disables the low voltage supplies LDO1 and Buck1. See details below.  
Output Voltage Enable Register 1 (OVER1) 8h’10  
Bit  
7
6
5
Reserved  
0
4
3
2
S_EN  
1
1
Reserved  
0
0
A_EN  
1
Designation  
Reset Value  
0
0
0
0
Output Voltage Enable Register 1 (OVER1) 8h’10 Definitions  
Bit  
Access  
Name  
Description  
7-3  
2
Reserved  
R/W  
S_EN  
VCC_SRAM (LDO5) Supply Output Enabled  
0 = VCC_SRAM (LDO5) Supply Output Disabled  
1 = VCC_SRAM (LDO5) Supply Output Enabled  
Reserved  
1
0
R/W  
A_EN  
VCC_APPS (Buck1) Supply Output Enabled  
0 = VCC_APPS (BUCK1) Supply Output Disabled  
1 = VCC_APPS (BUCK1) Supply Output Enabled  
OUTPUT VOLTAGE STATUS REGISTER  
This 8 bit register is used to indicate the status of the low voltage supplies. By polling each of the specify supplies is within its  
specified operating range.  
Output Voltage Status Register 1 (OVSR1) 8h’11  
Bit  
7
LP_OK  
0
6
5
4
3
2
S_OK  
0
1
Reserved  
0
0
A_OK  
0
Designation  
Reset Value  
Reserved  
0
0
0
0
Output Voltage Status Register 1 (OVSR1) 8h’11 Definitions  
Bit  
Access  
Name  
Description  
Low Voltage Supply Output Voltage Status  
7
R
LP_OK  
<
0 - VCC_APPS (Buck1) & VCC_SRAM (LDO5) output voltage 90% of  
selected value  
>
1 - VCC_APPS (Buck1) & VCC_SRAM (LDO5) output voltage 90% of  
selected value  
Reserved  
6:3  
2
R
S_OK  
VCC_SRAM Supply Output Voltage Status  
<
0 - VCC_SRAM (LDO5) output voltage 90% of selected value  
>
1 - VCC_SRAM (LDO5) output voltage 90% of selected value  
1
0
R
Reserved  
A_OK  
VCC_APPS Supply output Voltage Status  
<
0 - VCC_APPS(BUCK1) output voltage 90% of selected value  
>
1 - VCC_APPS(BUCK1) output voltage 90% of selected value  
25  
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I2C Compatible Interface (Continued)  
OUTPUT VOLTAGE ENABLE REGISTER 2  
This 8 bit output register enables and disables the output voltages on the LDO 2,3,4 supplies.  
Output Voltage Enable Register 2 (OVER2) 8h’12  
Bit  
7
6
Reserved  
0
5
4**  
LDO4_EN  
0
3**  
LDO3_EN  
0
2**  
LDO2_EN  
0
1
0
Designation  
Reserved  
Reset Value  
0
0
0
0
Note: ** denotes one time factory programmable EPROM registers for default values  
Output Voltage Enable Register 2 (OVER2) 8h’12 Definitions  
Bit  
7
Access  
Name  
Description  
Reserved  
Reserved  
Reserved  
6
5
4
R/W  
LDO4_EN  
LDO_4 Output Voltage Enable  
0 = LDO4 Supply Output Disabled, Default  
1 = LDO4 Supply Output Enabled  
LDO_3 Output Voltage Enable  
0 = LDO3 Supply Output Disabled, Default  
1 = LDO3 Supply Output Enabled  
LDO_2 Output Voltage Enable  
0 = LDO2 Supply Output Disabled, Default  
1 = LDO2 Supply Output Enabled  
Reserved  
3
2
R/W  
R/W  
LDO3_EN  
LDO2_EN  
1
0
Reserved  
OUTPUT VOLTAGE ENABLE REGISTER 2  
Output Voltage Status Register 2 (OVSR2) 8h’13  
Bit  
7
LDO_OK  
0
6
N/A  
0
5
N/A  
0
4
LDO4_OK  
0
3
LDO3_OK  
0
2
LDO2_OK  
0
1
0
Designation  
Reset Value  
N/A  
N/A  
0
0
Output Voltage Status Register 2 (OVSR2) 8h’13 Definitions  
Bit  
Access  
Name  
Description  
LDO 2-4 Supply Output Voltage Status  
7
R
LDO_OK  
<
0 - (LDO 2-4) output voltage 90% of selected value  
>
1 - (LDO 2-4) output voltage 90% of selected value  
6
5
4
R
Reserved  
Reserved  
LDO4_OK  
LDO_4 Output Voltage Status  
<
0 - (VCC_LDO4) output voltage 90% of selected value  
>
1 - (VCC_LDO4) output voltage 90% of selected value  
3
2
R
R
LDO3_OK  
LDO2_OK  
LDO_3 Output Voltage Status  
<
>
0 - (VCC_LDO3) output voltage 90% of selected value  
1 - (VCC_LDO3) output voltage 90% of selected value  
LDO_2 Output Voltage Status  
<
0 - (VCC_LDO2) output voltage 90% of selected value  
>
1 - (VCC_LDO2) output voltage 90% of selected value  
1
0
Reserved  
Reserved  
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26  
I2C Compatible Interface (Continued)  
DVM VOLTAGE CHANGE CONTROL REGISTER 1  
DVM Voltage Change Control Register 1 (VCC1) 8h’20  
Bit  
7
MVS  
0
6
MGO  
0
5
SVS  
0
4
SGO  
0
3
2
1
AVS  
0
0
AGO  
0
Designation  
Reset Value  
Reserved  
0
0
DVM Voltage Change Control Register 1 (VCC1) 8h’20 Definitions  
Bit  
Access  
Name  
Description  
VCC_MVT (LDO1) Voltage Select  
7
R/W  
MVS  
0 - Change VCC_MVT Output Voltage to MDVT1  
1 - Change VCC_MVT Output Voltage to MDVT2  
Start VCC_MVT (LDO1) Voltage Change  
6
5
4
R/W  
R/W  
R/W  
MGO  
SVS  
0 - Hold VCC_MVT Output Voltage at current Level  
1 - Ramp VCC_MVT Output Voltage as selected by MVS  
CC_SRAM (LDO5) Voltage Select  
V
0 - Change VCC_SRAM Output Voltage to SDTV1  
1 - Change VCC_SRAM Output Voltage to SDTV2  
Start VCC_SRAM (LDO5) Voltage Change  
0 - Hold VCC_SRAM Output Voltage at current Level  
1 - Change VCC_SRAM Output Voltage as selected by SVS  
Reserved  
SGO  
3:2  
1
R/W  
AVS  
VCC_APPS (Buck 1) Voltage Select  
0 - Ramp VCC_APPS Output Voltage to ADVT1  
1 - Ramp VCC_APPS Output Voltage to ADVT2  
Start VCC_APPS(Buck1) Voltage Change  
0
R/W  
AGO  
0 - Hold VCC_APPS Output Voltage at current Level  
1 - Ramp VCC_APPS Output Voltage as selected by AVS  
27  
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I2C Compatible Interface (Continued)  
BUCK1 (VCC_APPS) VOLTAGE 1  
Buck1 (VCC_APPS) Target Voltage 1 Register (ADTV1) 8h’23  
Bit  
7
6
Reserved  
0
5
4**  
3**  
2**  
1**  
0**  
Designation  
Buck 1 Output Voltage (B1OV1)  
Reset Value  
0
0
0
1
0
1
1
Note: ** denotes one time factory programmable  
Buck1 (VCC_APPS) Target Voltage 1 Register (ADTV1) 8h’23 Definitions  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
R/W  
B1OV1  
Data Code  
5h’0  
Output Voltage  
0.725  
Data Code  
5h’10  
5h’11  
Output Voltage  
1.125  
5h’1  
0.750  
1.150  
5h’2  
0.775  
5h’12  
5h’13  
5h’14  
5h’15  
5h’16  
5h’17  
5h’18  
5h’19  
5h’1A  
5h’1B  
5h’1C  
5h’1D  
5h’1E  
5h’1F  
1.175  
5h’3  
0.800  
1.200  
5h’4  
0.825  
1.225  
5h’5  
0.850  
1.250  
5h’6  
0.875  
1.275  
5h’7  
0.900  
1.300  
5h’8  
0.925  
1.325  
5h’9  
0.950  
1.350  
5h’A  
5h’B  
5h’C  
5h’D  
5h’E  
5h’F  
0.975  
1.375  
1.000  
1.400  
1.425  
1.025  
1.050  
1.450  
1.075  
1.475  
1.100  
1.500  
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28  
I2C Compatible Interface (Continued)  
BUCK1 (VCC_APPS) TARGET VOLTAGE 2 REGISTER  
Buck1 (VCC_APPS) Target Voltage 2 Register (ADTV2) 8h’24  
Bit  
7
6
Reserved  
0
5
4
3
2
1
0
Designation  
Reset Value  
Buck 1 Output Voltage (B1OV2)  
0
0
0
1
0
1
1
Buck1 (VCC_APPS) Target Voltage 2 Register (ADTV2) 8h’24 Definitions  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
Data Code  
R/W  
B1OV2  
Output Voltage  
0.725  
Data Code  
5h’10  
5h’11  
Output Voltage  
1.125  
5h’0  
5h’1  
5h’2  
5h’3  
5h’4  
5h’5  
5h’6  
5h’7  
5h’8  
5h’9  
5h’A  
5h’B  
5h’C  
5h’D  
5h’E  
5h’F  
0.750  
1.150  
0.775  
5h’12  
5h’13  
5h’14  
5h’15  
5h’16  
5h’17  
5h’18  
5h’19  
5h’1A  
5h’1B  
5h’1C  
5h’1D  
5h’1E  
5h’1F  
1.175  
0.800  
1.200  
0.825  
1.225  
0.850  
1.250  
0.875  
1.275  
0.900  
1.300  
0.925  
1.325  
0.950  
1.350  
0.975  
1.375  
1.000  
1.400  
1.025  
1.425  
1.050  
1.450  
1.075  
1.475  
1.100  
1.500  
29  
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I2C Compatible Interface (Continued)  
BUCK1 (VCC_APPS) VOLTAGE RAMP CONTROL REGISTER  
Buck1 (VCC_APPS) Voltage Ramp Control Register (AVRC) 8h’25  
Bit  
7
6
Reserved  
0
5
4
3
2
1
0
Designation  
Reset Value  
Ramp Rate (B1RR)  
0
0
0
0
1
1
0
Buck 1 (VCC_APPS) Voltage Ramp Control Register (AVRC) 8h’25 Definitions  
Bit  
Access  
Name  
Description  
7:5  
Reserved  
DVM Ramp Speed  
Data Code  
Ramp Rate (mV/uS)  
5h’0  
5h’1  
Instant  
1
5h’2  
2
5h’3  
3
5h’4  
4
4:0  
R/W  
B1RR  
5h’5  
5
5h’6  
6
5h’7  
7
5h’8  
8
5h’9  
9
10  
Reserved  
5h’A  
4h’B-4h’1F  
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30  
I2C Compatible Interface (Continued)  
V
CC_COMM TARGET VOLTAGE 1 DUMMY REGISTER (CDTV1)  
V
CC_COMM Target Voltage 1 Dummy Register (CDTV1) 8h’26 Write Only  
Bit  
7
6
Reserved  
0
5
4
3
2
1
0
Designation  
Output Voltage  
0
Reset Value  
0
0
0
0
0
0
2
Note: CDTV1 must be writable by an I C controller. This is a dummy register  
VCC_COMM TARGET VOLTAGE 2 DUMMY REGISTER (CDTV2)  
V
CC_COMM Target Voltage 2 Dummy Register (CDTV2) 8h’27 Write Only  
Bit  
7
6
Reserved  
0
5
4
3
2
1
0
Designation  
Output Voltage  
0
Reset Value  
0
0
0
0
0
0
2
Note: CDTV2 must be writable by an I C controller. This is a dummy register and can not be read.  
This is a variable voltage supply to the internal SRAM of the Application processor.  
LDO 5 (VCC_SRAM) TARGET VOLTAGE 1 REGISTER  
LDO 5 (VCC_SRAM) Target Voltage 1 Register (SDTV1) 8H’29  
Bit  
7
6
Reserved  
0
5
4**  
3**  
2**  
1**  
0**  
Designation  
LDO 5 Output Voltage (L5OV)  
Reset Value  
0
0
0
1
0
1
1
Note: ** denotes one time factory programmable EPROM registers for default values  
LDO 5 (VCC_SRAM) Target Voltage 1 Register (SDTV1) 8h’29 Definitions  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
Data Code  
R/W  
B1OV  
Output Voltage  
Data Code  
5h’10  
5h’11  
Output Voltage  
1.125  
5h’0  
5h’1  
5h’2  
5h’3  
5h’4  
5h’5  
5h’6  
5h’7  
5h’8  
5h’9  
5h’A  
5h’B  
5h’C  
5h’D  
5h’E  
5h’F  
1.150  
5h’12  
5h’13  
5h’14  
5h’15  
5h’16  
5h’17  
5h’18  
5h’19  
5h’1A  
5h’1B  
5h’1C  
5h’1D  
5h’1E  
5h’1F  
1.175  
1.200  
1.225  
0.850  
0.875  
0.900  
0.925  
0.950  
0.975  
1.000  
1.025  
1.050  
1.075  
1.100  
1.250  
1.275  
1.300  
1.325  
1.350  
1.375  
1.400  
1.425  
1.450  
1.475  
1.500  
31  
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I2C Compatible Interface (Continued)  
LDO 5 (VCC_SRAM) TARGET VOLTAGE 2 REGISTER  
LDO 5 (VCC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A  
Bit  
7
6
Reserved  
0
5
4
3
2
1
0
Designation  
Reset Value  
LDO 5 Output Voltage (L5OV)  
0
0
0
1
0
1
1
LDO 5 (VCC_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A Definitions  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
Data Code  
R/W  
B1OV  
Output Voltage  
Data Code  
5h’10  
5h’11  
Output Voltage  
1.125  
5h’0  
5h’1  
5h’2  
5h’3  
5h’4  
5h’5  
5h’6  
5h’7  
5h’8  
5h’9  
5h’A  
5h’B  
5h’C  
5h’D  
5h’E  
5h’F  
1.150  
5h’12  
5h’13  
5h’14  
5h’15  
5h’16  
5h’17  
5h’18  
5h’19  
5h’1A  
5h’1B  
5h’1C  
5h’1D  
5h’1E  
5h’1F  
1.175  
1.200  
1.225  
0.850  
0.875  
0.900  
0.925  
0.950  
0.975  
1.000  
1.025  
1.050  
1.075  
1.100  
1.250  
1.275  
1.300  
1.325  
1.350  
1.375  
1.400  
1.425  
1.450  
1.475  
1.500  
VCC_MVT is low tolerance regulated power supply for the application processor ring oscillator and logic for communicating to the  
LP3972. VCC_MVT is enabled when SYS_EN is asserted and disabled when SYS_EN is deasserted.  
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32  
I2C Compatible Interface (Continued)  
LDO 1 (VCC_MVT) TARGET VOLTAGE 1 REGISTER (MDTV1)  
LDO 1 (VCC_MVT) Target Voltage 1 Register (MDTV1) 8h’32  
Bit  
7
6
Reserved  
0
5
4**  
3**  
2**  
1**  
0**  
Designation  
Output Voltage (OV)  
1
Reset Value  
0
0
0
0
0
0
Note: ** denotes one time factory programmable EPROM registers for default values  
LDO 1 (VCC_MVT) Target Voltage 1 Register (MDTV1) 8h’32 Definitions  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
Data Code  
R/W  
L1OV  
Output Voltage  
1.700  
Notes:  
5h’0  
5h’1  
1.725  
5h’2  
1.750  
5h’3  
1.775  
5h’4  
5h’5  
1.800  
1.825  
5h’6  
1.850  
5h’7  
1.875  
5h’8  
1.900  
5h’9  
1.925  
5h’A  
5h’B  
5h’C  
5h’D-5h’F  
1.950  
1.975  
2.000  
Reserved  
33  
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I2C Compatible Interface (Continued)  
LDO 1 (VCC_MVT) TARGET VOLTAGE 2 REGISTER  
LDO 1 (VCC_MVT) Target Voltage 2 Register (MDTV2) 8h’33  
Bit  
7
6
Reserved  
0
5
4
3
2
1
0
Designation  
Reset Value  
Output Voltage (OV)  
0
0
0
0
1
1
1
LDO 1 (VCC_MVT) Target Voltage 2 Register (MDTV2) 8h’33 Definitions  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
Data Code  
R/W  
L1OV  
Output Voltage  
1.700  
Notes:  
5h’0  
5h’1  
1.725  
5h’2  
1.750  
5h’3  
1.775  
5h’4  
5h’5  
1.800  
1.825  
5h’6  
1.850  
5h’7  
1.875  
5h’8  
1.900  
5h’9  
1.925  
5h’A  
5h’B  
5h’C  
5h’D-5h’F  
1.950  
1.975  
2.000  
Reserved  
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34  
I2C Compatible Interface (Continued)  
LDO2 VOLTAGE CONTROL REGISTER (L12VCR)  
LDO2 Voltage Control Register (L12VCR) 8h’39  
Bit  
7**  
6**  
5**  
4**  
3
2
1
0
Designation  
LDO 2 Output Voltage (L2OV)  
Reserved  
Reset Value  
0
0
0
0
0
0
0
0
Note: ** denotes one time factory programmable EPROM registers for default values  
LDO2 Voltage Control Register (L12VCR) 8h’39 Definitions  
Bit  
Access  
Name  
Description  
7:4  
R/W  
L2OV  
Data Code  
4h’0  
Output Voltage  
Notes:  
Default  
1.8  
1.9  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
2.9  
3.0  
3.1  
3.2  
3.3  
4h’1  
4h’2  
4h’3  
4h’4  
4h’5  
4h’6  
4h’7  
4h’8  
4h’9  
4h’A  
4h’B  
4h’C  
4h’D  
4h’E  
4h’F  
3:0  
Reserved  
35  
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I2C Compatible Interface (Continued)  
LDO4 – LDO3 VOLTAGE CONTROL REGISTER (L34VCR)  
LDO4 – LDO3 Voltage Control Register (L34VCR) 8h’3A  
Bit  
7**  
6**  
5**  
4**  
3**  
2**  
1**  
0**  
Designation  
LDO 4 Output Voltage (L4OV)  
LDO 3 Output Voltage (L3OV)  
Reset Value  
0
0
0
0
0
0
0
0
Note: ** denotes one time factory programmable EPROM registers for default values  
LDO4 – LDO3 Voltage Control Register (L34VCR) 8h’3A Definitions  
Bit  
Access  
Name  
Description  
7:4  
R/W  
L4OV  
Data Code  
4h’0  
4h’1  
Output Voltage  
Notes:  
1.00  
1.05  
1.10  
1.15  
1.20  
1.25  
1.30  
1.35  
1.40  
1.50  
1.80  
1.90  
2.50  
2.80  
3.00  
3.30  
Output Voltage  
1.8  
4h’2  
4h’3  
4h’4  
4h’5  
4h’6  
4h’7  
4h’8  
4h’9  
4h’A  
4h’B  
4h’C  
4h’D  
4h’E  
4h’F  
Data Code  
4h’0  
Default  
Notes:  
3:0  
R/W  
L3OV  
4h’1  
1.9  
4h’2  
2.0  
4h’3  
2.1  
4h’4  
2.2  
4h’5  
2.3  
4h’6  
2.4  
4h’7  
2.5  
4h’8  
2.6  
4h’9  
2.7  
4h’A  
4h’B  
4h’C  
4h’D  
4h’E  
4h’F  
2.8  
2.9  
3.0  
3.1  
Default  
3.2  
3.3  
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36  
I2C Compatible Interface (Continued)  
NSC DEFINED CONTROL AND STATUS REGISTERS  
SYSTEM CONTROL REGISTER 1 (SCR1)  
System Control Register 1 (SCR1) 8h’80  
Bit  
7**  
BPSEN  
0
6**  
5**  
4
FPWM3  
0
3
FPWM2  
0
2
FPWM1  
0
1
0
BK_SSEN  
0
Designation  
SENDL  
BK_SLOMOD  
0
Reset Value  
1
0
Note: ** denotes one time factory programmable EPROM registers for default values  
System Control Register 1 (SCR1) 8h’80 Definitions  
Bit  
Access  
Name  
Description  
7
R/W  
BPSEN  
Bypass System enable safety Lock. Prevents activation of  
PWR_EN when SYS_EN is low.  
0 = PWR_EN “AND” with SYS_EN signal, Default  
1 = PWR_EN independent of SYS_EN  
Delay time for High Voltage Power Domains LDO2, LDO3, LDO4,  
Buck2, and Buck3 after activation of SYS_EN. VCC_LDO1 has no  
delay.  
Data Code  
2h’0  
Delay mS  
0.0  
Notes:  
6:5  
R/W  
SENDL  
2h’1  
0.5  
2h’2  
1.0  
Default  
2h’3  
1.4  
4
3
2
1
0
R/W  
R/W  
R/W  
R
FPWM3  
FPWM2  
Buck 3 PWM/PFM Mode select  
0 - Auto Switch between PFM and PWM operation  
1 - PWM Mode Only will not switch to PFM  
Buck 2 PWM/PFM Mode select  
0 - Auto Switch between PFM and PWM operation  
1 - PWM Mode Only will not switch to PFM  
Buck 1 PWM/PFM Mode select  
FPWM1  
0 - Auto Switch between PFM and PWM operation  
1 - PWM Mode Only will not switch to PFM  
Buck Spread Spectrum Modulation Buck 1-3  
BK_SLOMOD  
BK_SSEN  
0 = 10 kHz triangular wave spread spectrum modulation  
1 = 2 kHz triangular wave spread spectrum modulation  
Spread spectrum function Buck 1-3  
0 = SS Output Disabled  
R
1 = SS Output Enabled  
37  
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I2C Compatible Interface (Continued)  
SYSTEM CONTROL REGISTER 2 (SCR2)  
System Control Register 2 (SCR2) 8h’81  
Bit  
7
BBCS  
1
6
SHBU  
0
5**  
BPTR  
1
4
WUP3  
1
3
2
1
0
Designation  
GPIO2  
GPIO1  
Reset Value  
0
0
1
0
Note: ** denotes one time factory programmable EPROM registers for default values  
System Control Register 2 (SCR2) 8h’81 Definitions  
Bit  
Access  
Name  
Description  
7
R/W  
BBCS  
Sets GPIO1 as control input for Back Up battery charger  
0 - Back Up battery Charger GPIO Disabled  
1 - Back Up battery Charger GPIO Pin Enabled  
Shut down Back up battery to prevent battery drain during  
shipping  
6
5
R/W  
R/W  
SHBU  
BPTR  
0 = Back up Battery Enabled  
1 = Back up battery Disabled  
Bypass RTC_LDO Output Voltage to LDO 3 Output Voltage  
Tracking  
0 - RTC-LDO 3 Tracking enabled  
1 - RTC-LDO 3 Tracking disabled, Default  
Spare Wakeup control input  
4
R/W  
R/W  
WUP3  
GPIO2  
0 - Active High  
1 - Active Low  
3:2  
Configure direction and output sense of GPIO2 Pin  
Data Code  
2h’00  
GPIO2  
Hi-Z  
2h’01  
Output Low  
Input  
2h’02  
2h’03  
Output high  
1:0  
R/W  
GPIO1  
Configure direction and output sense of GPIO1 Pin  
Data Code  
2h’00  
GPIO1  
Hi-Z  
2h’01  
Output Low  
Input  
2h’02  
2h’03  
Output high  
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38  
I2C Compatible Interface (Continued)  
OUTPUT ENABLE 3 REGISTER (OEN3) 8H’82  
Bit  
7
6
Reserved  
0
5
4**  
B3EN  
1
3
ENFLAG  
0
2**  
B2EN  
1
1
Reserved  
0
0**  
L1EN  
1
Designation  
Reset Value  
0
0
Note: ** denotes one time factory programmable EPROM registers for default values  
OUTPUT ENABLE 3 REGISTER (OEN3) 8H’82 DEFINITIONS  
Bit  
7:5  
4
Access  
Name  
Description  
Reserved  
VCC_Buck3 Supply Output Enabled  
R/W  
B3EN  
0 = VCC_Buck3 Supply Output Disabled  
1 = VCC_Buck3 Supply Output Enabled, Default  
Enable for Temperature Flags (BCT)  
0 = Temperature Flag Disabled  
3
2
R/W  
R/W  
ENFLAG  
B2EN  
1 = Temperature Flag Enabled  
VCC_Buck2 Supply Output Enabled  
0 = VCC_Buck2 Supply Output Disabled  
1 = VCC_Buck2 Supply Output Enabled, Default  
Reserved  
1
0
R/W  
L1EN  
LDO_1 (MVT)Output Voltage Enable  
0 = LDO1 Supply Output Disabled  
1 = LDO1 Supply Output Enabled, Default  
STATUS REGISTER 3 (OSR3) 8H’83  
Bit  
7
BT_OK  
0
6
B3_OK  
0
5
B2_OK  
0
4
LDO1_OK  
0
3
Reserved  
0
2
BCT2  
0
1
0
BCT0  
0
Designation  
Reset Value  
BCT1  
0
STATUS REGISTER 3 (OSR3) DEFINITIONS 8H’83  
Bit  
Access  
Name  
Description  
Buck 2-3 Supply Output Voltage Status  
7
R
BT_OK  
<
0 - (Buck 1-3) output voltage 90% Default value  
>
1 - (Buck 1-3) output voltage 90% Default value  
6
5
4
3
R
R
B3_OK  
B2_OK  
LDO1_OK  
Buck 3 Supply Output Voltage Status  
<
0 - (Buck 3) output voltage 90% Default value  
>
1 - (Buck 3) output voltage 90% Default value  
Buck 2 Supply Output Voltage Status  
<
0 - (Buck 2) output voltage 90% Default value  
>
1 - (Buck 2) output voltage 90% Default value  
R
LDO_1 Output Voltage Status  
<
0 - (VCC_LDO1) output voltage 90% of selected value  
>
1 - (VCC_LDO1) output voltage 90% of selected value  
Reserved  
39  
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I2C Compatible Interface (Continued)  
Bit  
Access  
Name  
Description  
Binary coded thermal management flag status register  
Temperature  
2:0  
R
BCT  
Data Code  
000  
Ascending ˚C  
40  
60  
001  
010  
80  
011  
100  
100  
120  
101  
140  
110  
160  
111  
Reserved  
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40  
I2C Compatible Interface (Continued)  
LOGIC OUTPUT ENABLE REGISTER (LOER) 8H’84  
Bit  
7
Reserved  
0
6*  
B3ENC  
1
5*  
B2ENC  
1
4*  
B1ENC  
0
3*  
L5EC  
0
2*  
L4EC  
1
1*  
L3EC  
1
0*  
L2EC  
1
Designation  
Reset Value  
Note: ** denotes one time factory programmable EPROM registers for default values  
LOGIC OUTPUT ENABLE REGISTER (LOER) DEFINITIONS 8H’84  
Bit  
7
Access  
Name  
Description  
Reserved  
6
R/W  
B3ENC  
Connects Buck 3 enable to SYS_EN or PWR_EN Logic Control pin  
0 - Buck 3 enable connected to PWR_EN  
1 - Buck 3 enable connected to SYS_EN, Default  
Connects Buck 2 enable to SYS_EN or PWR_EN Logic Control pin  
0 - Buck 2 enable connected to PWR_EN  
5
4
3
2
1
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
B2ENC  
B1ENC  
L5EC  
1 - Buck 2 enable connected to SYS_EN, Default  
Connects Buck 1 enable to SYS_EN or PWR_EN Logic Control pin  
0 - Buck 1 enable connected to PWR_EN, Default  
1 - Buck 1 enable connected to SYS_EN  
Connects LDO5 enable to SYS_EN or PWR_EN Logic Control pin  
0 - LDO 5 enable connected to PWR_EN, Default  
1 - LDO 5 enable connected to SYS_EN  
L4EC  
Connects LDO4 enable to SYS_EN or PWR_EN Logic Control pin  
0 - LDO 4 enable connected to PWR_EN  
1 - LDO 4 enable connected to SYS_EN, Default  
Connects LDO3 enable to SYS_EN or PWR_EN Logic Control pin  
0 - LDO 3 enable connected to PWR_EN  
L3EC  
1 - LDO 3 enable connected to SYS_EN, Default  
Connects LDO2 enable to SYS_EN or PWR_EN Logic Control pin  
0 - LDO 2 enable connected to PWR_EN  
L2EC  
1 - LDO 2 enable connected to SYS_EN, Default  
41  
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I2C Compatible Interface (Continued)  
V
CC_BUCK 2 TARGET VOLTAGE REGISTER (B2TV) 8H’85  
Bit  
7
6
Reserved  
0
5
4**  
3**  
2**  
1**  
0**  
Designation  
Buck 2 Output Voltage (B2OV)  
Reset Value  
0
0
1
1
0
0
1
Note: ** denotes one time factory programmable EPROM registers for default values  
VCC_BUCK 2 TARGET VOLTAGE REGISTER (B2TV) 8H’85 DEFINITIONS  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
Output Voltage  
Data Code  
5h’01  
R/W  
B2OV  
(V)  
Data Code  
(V)  
0.80  
0.85  
0.90  
0.95  
1.00  
1.05  
1.10  
1.15  
1.20  
1.25  
1.30  
1.35  
5h’0D  
5h’0E  
5h’0F  
5h’10  
5h’11  
5h’12  
5h’13  
5h’14  
5h’15  
5h’16  
5h’17  
5h’18  
5h’19  
1.40  
1.45  
1.50  
1.55  
1.60  
1.65  
1.70  
1.80  
1.90  
2.50  
2.80  
3.00  
3.30  
5h’02  
5h’03  
5h’04  
5h’05  
5h’06  
5h’07  
5h’08  
5h’09  
5h’0A  
5h’0B  
5h’0C  
BUCK 3 TARGET VOLTAGE REGISTER (B3TV) 8H’86  
Bit  
7
6
Reserved  
0
5
4**  
3**  
2**  
1**  
0**  
Designation  
Buck 3 Output Voltage (B3OV)  
Reset Value  
0
0
1
0
1
0
0
Note: ** denotes one time factory programmable EPROM registers for default values  
BUCK 3 TARGET VOLTAGE REGISTER (B3TV) 8H’86 DEFINITIONS  
Bit  
7:5  
4:0  
Access  
Name  
Description  
Reserved  
Output Voltage  
Data Code  
5h’01  
R/W  
B3OV  
(V)  
Data Code  
5h’0D  
5h’0E  
5h’0F  
5h’11  
(V)  
0.80  
0.85  
0.90  
0.95  
1.00  
1.05  
1.10  
1.15  
1.20  
1.25  
1.30  
1.35  
1.40  
1.45  
1.50  
1.60  
1.65  
1.70  
1.80  
1.90  
2.50  
2.80  
3.00  
3.30  
5h’02  
5h’03  
5h’04  
5h’05  
5h’12  
5h’13  
5h’14  
5h’15  
5h’16  
5h’17  
5h’18  
5h’19  
5h’06  
5h’07  
Default  
5h’08  
5h’09  
5h’0A  
5h’0B  
5h’0C  
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42  
I2C Compatible Interface (Continued)  
V
CC_BUCK 3:2 VOLTAGE RAMP CONTROL REGISTER (B32RC)  
V
CC_Buck 3:2 Voltage Ramp Control Register (B32RC) 8h’87  
Bit  
7
6
5
4
3
2
1
0
Designation  
Reset Value  
Ramp Rate (B3RR)  
Ramp Rate (B2RR)  
1
0
1
0
1
0
1
0
Buck 3:2 Voltage Ramp Control Register (B3RC) 8h’87 Definitions  
Bit  
Access  
Name  
Description  
7:4  
R/W  
B3RR  
Data Code  
4h’0  
Ramp Rate mV/µS  
Instant  
4h’1  
1
4h’2  
2
4h’3  
3
4h’4  
4
4h’5  
5
4h’6  
6
4h’7  
7
4h’8  
8
4h’9  
9
4h’A  
Data Code  
4h’0  
10  
3:0  
R/W  
B2RR  
Ramp Rate mV/µS  
Instant  
4h’1  
1
2
4h’2  
4h’3  
3
4h’4  
4
4h’5  
5
4h’6  
6
4h’7  
7
4h’8  
8
4h’9  
9
4h’A  
10  
43  
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I2C Compatible Interface (Continued)  
INTERRUPT STATUS REGISTER ISRA  
This register specifies the status bits for the interrupts generated by the PMIC. Thermal warning of the IC, GPIO1, GPIO2,  
PWR_ON pin, TEST_JIG factory programmable on signal, and the SPARE pin.  
Interrupt Status Register ISRA 8h’88  
Bit  
7
Reserved  
0
6
T125  
0
5
GPI2  
0
4
GPI1  
0
3
WU3L  
0
2
WUPS  
0
1
WUPT  
0
0
WUPS  
0
Designation  
Reset Value  
Interrupt Status Register ISRA 8h’88 Definitions  
Bit  
7
Access  
Name  
Description  
R
Reserved  
Status bit for thermal warning PMIC T 125C  
>
6
T125  
<
0 = PMIC Temp. 125˚C  
>
1 = PMIC Temp. 125˚C  
5
4
3
2
1
0
R
R
R
R
R
R
GPI2  
GPI1  
Status bit for the input read in from GPIO 2 when set as Input  
0 = GPI2 Logic Low  
1 = GPI2 Logic High  
Status bit for the input read in from GPIO 1 when set as Input  
0 = GPI1 Logic Low  
1 = GPI1 Logic High  
WU3L  
WUPS  
WUPT  
WUPS  
PWR_ON Pin long pulse Wake Up Status  
0 = No wake up event  
1 = Long pulse wake up event  
PWR_ON Pin Short pulse Wake Up Status  
0 = No wake up event  
1 = Short pulse wake up event  
TEST_JIG Pin Wake Up Status  
0 = No wake up event  
1 = Wake up event  
SPARE Pin Wake Up Status  
0 = No wake up event  
1 = Wake up event  
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44  
I2C Compatible Interface (Continued)  
BACKUP BATTERY CHARGER CONTROL REGISTER (BCCR)  
This register specifies the status of the main battery supply. NBUB bit  
Backup Battery Charger Control Register (BCCR) 8h’89  
Bit  
7**  
NBUB  
0
6
CNBFL  
0
5**  
4**  
nBFLT  
1
3**  
2
BUCEN  
0
1
0
Designation  
IBUC  
Reset Value  
0
0
0
1
Note: ** denotes one time factory programmable EPROM registers for default values  
Backup Battery Charger Control Register (BCCR) 8h’89 Definitions  
Bit  
Access  
Name  
Description  
7
R/W  
NBUB  
No back-up battery default setting. Logic will not allow switch over to  
back-up battery.  
0 = Back up Battery Enabled, Default  
1 = Back up Battery Disabled  
6
R/W  
CNBFL  
Control for nBATT_FLT output signal  
0 = nBATT_FLT Enabled  
1 = nBATT_FLT Disabled  
nBATT_FLT monitors the battery voltage and can be set to the Assert  
voltages listed below.  
Data Code  
3h’01  
Asserted  
2.6  
De-Asserted  
Note:  
2.8  
3.0  
3.2  
3.4  
3.6  
5:3  
2
R/W  
R/W  
BFLT  
3h’02  
2.8  
3.0  
Default  
3h’03  
3h’04  
3.2  
3h’05  
3.4  
BUCEN  
Enables backup battery charger  
0 = Back up Battery Charger Disabled  
1 = Back up Battery Charger Enabled  
Charger current setting for back-up battery  
Data Code  
2h’00  
BU Charger I (µA)  
Note:  
260  
190  
325  
390  
1:0  
R/W  
IBUC  
2h’01  
2h’02  
Default  
2h’03  
45  
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I2C Compatible Interface (Continued)  
INTEL INTERNAL 1 REVISION REGISTER (II1RR) 8H’8E  
Bit  
7
6
5
4
3
2
1
0
Designation  
Reset Value  
II1RR  
0
0
0
0
0
0
0
0
INTEL INTERNAL 1 REVISION REGISTER (II1RR) 8H’8E DEFINITIONS  
Bit  
Access  
Name  
Description  
7:0  
R
II1RR  
Intel internal usage register for revision information.  
INTEL INTERNAL 2 REVISION REGISTER (II2RR) 8H’8F  
Bit  
7
6
5
4
3
2
1
0
Designation  
Reset Value  
II2RR  
0
0
0
0
0
0
0
0
INTEL INTERNAL 2 REVISION REGISTER (II2RR) 8H’8F DEFINITIONS  
Bit  
Access  
Name  
Description  
7:0  
R
II2RR  
Intel internal usage register for revision information.  
REGISTER PROGRAMMING EXAMPLES  
Example 1) Start of Day Sequence  
PMIC Register PMIC Register  
Address  
8h’23  
Name  
ADTVI  
SDTV1  
OVER1  
Register Data  
Description  
00011011  
00011011  
00000111  
Sets the SOD VCC_APPS voltage  
Sets the SOD VCC_SRAM voltage  
8h’29  
8h’10  
Enables VCC_SRAM and VCC_APPS to their programmed values.  
SODl Multi-byte random register transfer is outlined below:  
20207644  
Device Address, Register A Address, Ach, Register A  
Data, Ach Register M Address, Ach,  
Register M Data, Ach Register X  
Address, Ach, Register X Data, Ach  
Register Z Address, Ach, Register Z  
Data, Ach, Stop  
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46  
I2C Compatible Interface (Continued)  
Example 2) Voltage change Sequence  
PMIC Register PMIC Register  
Address  
8h’24  
Name  
ADTV2  
SDTV2  
Register Data  
00010111  
Description  
Sets the VCC_APPS target voltage 2 to 1.3 V  
Sets the VCC_SRAM target voltage 2 to 1.1 V  
Enable VCC_SRAM and VCC_APPS to change to their programmed  
target values.  
8h’2A  
00001111  
8h’20  
V
CC1  
00110011  
I2C DATA EXCHANGE BETWEEN MASTER AND SLAVE DEVICE  
20207645  
47  
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LP3972 Controls  
DIGITAL INTERFACE CONTROL SIGNALS  
Signal  
Definition  
Active State  
High  
Signal Direction  
Input  
SYS_EN  
PWR_EN  
SCL  
High Voltage Power Enable  
Low Voltage Power Enable  
High  
Input  
Serial Bus Clock Line  
Clock  
Input  
SDA  
Serial Bus Data Line  
Bidirectional  
Input  
nRSTI  
Forces an unconditional hardware reset  
Forces an unconditional hardware reset  
Main Battery removed or discharged indicator  
Wakeup Input to CPU  
Low  
Low  
Low  
High  
Low  
High  
High  
nRSTO  
Output  
nBATT_FLT  
PWR_ON  
nTEST_JIG  
SPARE  
Output  
Input  
Wakeup Input to CPU  
Input  
Wakeup Input to CPU  
Input  
EXT_WAKEUP  
Wake-Up Output for application processor  
Output  
GPIO1 / nCHG_EN General Purpose I/O /External Back-up Battery Charger enable  
GPIO2 General Purpose I/O  
Bidirectional /Input  
Bidirectional  
POWER DOMAIN ENABLES  
LDO1 will go off last. This function can be switched off or  
delay can be changed by DELAY bits via serial interface as  
seen on table below.  
PMU Output  
LDO_RTC  
HW Enable  
SW Enable  
LDO 1 (VCC_MVT)  
LDO2  
SYS_EN  
SYS_EN  
SYS_EN  
SYS_EN  
PWR_EN  
PWR_EN  
SYS_EN  
SYS_EN  
LDO1_EN  
LDO2_EN  
LDO3_EN  
LDO4_EN  
S_EN  
8h’80 Bit 5:4  
DELAY bits  
Delay, ms  
‘00’  
0
‘01’  
0.5  
‘10’  
1.0  
‘11’  
1.5  
LDO3  
LDO4  
LDO5 (VCC_SRAM)  
Buck1 (VCC_APPS)  
BUCK2  
LDO_RTC TRACKING (nIO_TRACK)  
A_EN  
LP3972 has a tracking function (nIO_TRACK). When en-  
abled, LDO_RTC voltage will track LDO3 voltage within 200  
mV down to 2.8V when LDO3 is enabled. This function can  
be switched on/off by nIO_TRACK register bit BPTR.  
B2_EN  
BUCK3  
B3_EN  
POWER DOMAINS SEQUENCING (DELAY)  
POWER SUPPLY ENABLE  
By default SYS_EN must be on to have PWR_EN enable but  
this feature can be switched off by register bit BP_SYS.  
SYS_EN and PWR_EN can be changed by programmable  
register bits.  
By default SYS_EN enables LDO1 always first and after a  
typical of 1 ms delay others. Also when SYS_EN is set off the  
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48  
LP3972 Controls (Continued)  
WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG,  
SPARE AND EXT_WAKEUP)  
WAKEUP register bits  
WUP0  
Reason for WAKEUP  
SPARE  
WUP1  
TEST_JIG  
Three input pins can be used to assert wakeup output for 10  
ms for application processor notification to wakeup. SPARE  
Input can be programmed through I2C compatible interface  
to be active low or high (SPARE bit, Default is active low ‘1’).  
A reason for wakeup event can be read through I2C compat-  
ible interface also. Additionally wakeup inputs have 30 ms  
de-bounce filtering. Furthermore PWR_ON have distinguish-  
ing between short and long (1s) pulses (push button input).  
LP3972 also has an internal Thermal Shutdown early warn-  
ing that generates a wakeup to the system also. This is  
generated usually at 125˚C.  
WUP2  
PWR_ON short pulse  
PWR_ON long pulse  
TSD Early Warning  
WUP3  
TSD_EW  
INTERNAL THERMAL SHUTDOWN PROCEDURE  
Thermal shutdown is build to generate early warning (typ.  
125˚C) which triggers the EXT_WAKEUP for the processor  
acknowledge. When  
160˚C) the PMU will reset the system until the device cools  
down.  
a thermal shutdown triggers (typ.  
BATTERY SWITCH AND BACK UP BATTERY CHARGER  
When Back-Up battery is connected but the main battery has  
been removed or its supply voltage too low, LP3972 uses  
Back-Up Battery for generating LDO_RTC voltage. When  
Main Battery is available the battery fet switches over to the  
main battery for LDO_RTC voltage. When Main battery volt-  
age is too low or removed nBATT_FLT is asserted. If no back  
up battery exists, the battery switch to back up can be  
switched off by nBU_BAT_EN bit. User can set the battery  
fault determination voltage and battery charger current via  
I2C compatible interface. Enabling of back up battery  
charger can be done via serial interface (nBAT_CHG_EN) or  
external charger enable pin (nCHG_EN). Pin 29 is set as  
external charger enable input by default.  
20207619  
49  
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input, output or hi-Z mode. Inputs value can be read via  
serial interface (GPI1,2 bits). The pin 29 functionality needs  
to be set to GPIO by serial interface register bit nEXTCH-  
GEN. (GPIO/CHG)  
LP3972 Controls (Continued)  
GENERAL PURPOSE I/O FUNCTIONALITY (GPIO1 AND  
GPIO2)  
LP3972 has 2 general purpose I/Os for system control. I2C  
compatible interface will be used for setting any of the pins to  
Controls  
Port Function  
Reg  
batmonchg  
Function  
< >  
1
< >  
1
GPIO  
GPIO  
Nextchgen_sel  
bucen  
GPIO1  
Input = 0  
Input = 1  
X
Gpin 1  
X
X
1
X
0
1
0
1
X
X
0
X
0
0
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
Enabled  
Not Enabled  
X
1
X
Enabled  
X
X
X
X
HiZ  
>
Input (dig)-  
Input  
Output = 0  
Output = 1  
0
0
< >  
< >  
1
GPIO  
1
GPIO  
Factory fm disabled  
GPIO_tstiob  
GPIO2  
HiZ  
gpin2  
0
1
0
1
0
0
1
1
1
1
1
1
0
input  
0
>
Input (dig)-  
Output = 0  
Output = 1  
0
The LP3972 has provision for two battery connections, the  
main battery Vbat and Backup Battery (See Applications  
Schematic Diagrams 1 & 2 of the LP3972 Data Sheet).  
— There is a hysterisis voltage in this switch operation  
so, the RTC LDO will not be reconnected to main  
battery until main battery voltage is greater than 3.1V  
typically.  
The function of the battery switch is to connect power to the  
RTC LDO from the appropriate battery, depending on con-  
ditions described below:  
Additionally, the user may wish to disable the battery  
switch, such as, in the case when only a main battery is  
used. This is accomplished by setting the “no back up  
battery bit” in the control register 8h’0B bit 7 NBUB. With  
this bit set to “1”, the above described switching will not  
occur, that is the RTC LDO will remain connected to the  
main battery even as it is discharged below the 2.9 Volt  
threshold.  
If only the backup battery is applied, the switch will auto-  
matically connect the RTC LDO power to this battery.  
If only the main battery is applied, the switch will auto-  
matically connect the RTC LDO power to this battery.  
If both batteries are applied, and the main battery is  
>
sufficiently charged (VBAT  
3.1V), the switch will auto-  
matically connect the RTC LDO power to the main bat-  
tery.  
REGULATED VOLTAGES OK  
All the power domains have own register bit (X_OK) that  
processor can read via serial interface to be sure that en-  
abled powers are OK (regulating). Note that these read only  
bits are only valid when regulators are settled (avoid reading  
these bits during voltage change or power up).  
As the main battery is discharged by use, the user will be  
warned by a separate circuit called nBATT_FLT. Then if  
no action is taken to restore the charge on the main  
battery, and discharging is continued the battery switch  
will protect the RTC LDO by disconnecting from the main  
battery and connecting to the backup battery.  
— The main battery voltage at which the RTC LDO is  
switched from main to backup battery is 2.9V typically.  
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50  
register controls may be shifted into the user programmable  
bank; the temperature range and resolution of these flags,  
might also be refined/redefined.  
LP3972 Controls (Continued)  
THERMAL MANAGEMENT  
Application: There is a mode wherein all 6 comparators  
(flags) can be turned on via the “enallflags” control register  
bit. This mode allows the user to interrogate the device or  
system temperature under the set operating conditions.  
Thus, the rate of temperature change can also be estimated.  
The system may then negotiate for speed and power trade  
off, or deploy cooling maneuvers to optimize system perfor-  
mance. The “enallflags” bit needs enabled only when the  
THERMAL WARNING  
2 of 6 low power comparators, each consumes less than 1  
µA, are always enabled to operate the “T=125˚C warning  
flag with hysteresis. This allows continuous monitoring of a  
thermal-warning flag feature with very low power consump-  
tion.  
LP3972 THERMAL FLAGS FUNCTIONAL DIAGRAM,  
DATA FROM INITIAL SILICON  
<
>
“bct 2:0 bits are read to conserve power.  
Note: The thermal management flags have been verified  
functional. Presently these registers are accessible by fac-  
tory only. If there is a demand for this function, the relevant  
The following functions are extra features from the thermal  
shutdown circuit:  
20207646  
51  
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Application Note - LP3972 Reset Sequence  
INITIAL COLD START POWER ON SEQUENCE  
timer set to 125 mS.  
1. The Back up battery is connected to the PMU, power is  
applied to the back-up battery pin, the RTC_LDO turns  
6. The LP3972 enables the high-voltage power supplies.  
— LDO1 power for VCC_MVT (Power for internal logic  
and I/O Blocks), BG (Bandgap reference voltage),  
OSC13M (13 MHz oscillator voltage) and PLL en-  
abled first, followed by others if delay is on.  
on and supplies  
a stable output voltage to the  
VCC_BATT pin of the Applications processor (initiating  
the power-on reset event) with nRSTO asserted from the  
LP3972 to the processor.  
7. Countdown timer expires; the Applications processor  
asserts PWR_EN to enable the low-voltage power sup-  
plies. The processor starts the countdown timer set to  
125 mS period.  
2. nRSTO de-asserts after a minimum of 50 mS.  
3. The Applications processor waits for the de-assertion of  
nBATT_FLT to indicate system power (VIN) is available.  
4. After system power (VIN) is applied, the LP3972 de-  
asserts nBATT_FLT. Note that BOTH nRSTO and  
nBATT_FLT need to be de-asserted before SYS_EN is  
enabled. The sequence of the two signals is indepen-  
dent of each other.  
8. The Applications processor asserts PWR_EN (ext. pin or  
I2C), the LP3972 enables the low-voltage regulators.  
9. Countdown timer expires; If enabled power domains are  
OK (I2C read) the power up sequence continues by  
enabling the processors 13 MHz oscillator and PLL’s.  
5. The Applications processor asserts SYS_EN, the  
LP3972 enables the system high-voltage power sup-  
plies. The Applications processor starts its countdown  
10. The Applications processor begins the execution of  
code.  
20207622  
* Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the two signals is independent of each other and  
can occur is either order.  
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52  
Application Note - LP3972 Reset Sequence (Continued)  
POWER-ON TIMING  
Symbol  
Description  
Min  
Typ  
Max Units  
t1  
t2  
t3  
t4  
t5  
Delay from VCC_RTC assertion to nRSTO de-assertion  
Delay from nBATT_FLT de-assertion to nRSTI assertion  
Delay from nRST de-assertion to SYS_EN assertion  
Delay from SYS_EN assertion to PWR_EN assertion  
Delay from PWR_EN assertion to nRSTO de-assertion  
50  
mS  
µS  
100  
10  
mS  
mS  
mS  
125  
125  
HARDWARE RESET SEQUENCE  
Hardware reset initiates when the nRSTI signal is asserted  
(low). Upon assertion of nRST the processor enters hard-  
ware reset state. The LP3972 holds the nRST low long  
enough (50 ms typ.) to allow the processor time to initiate the  
reset state.  
plies. The Applications processor starts its countdown  
timer.  
6. The LP3972 enables the high-voltage power supplies.  
7. Countdown timer expires; the Applications processor  
asserts PWR_EN to enable the low-voltage power sup-  
plies. The processor starts the countdown timer.  
RESET SEQUENCE  
8. The Applications processor asserts PWR_EN, the  
LP3972 enables the low-voltage regulators.  
1. nRSTI is asserted.  
2. nRSTO is asserted and will de-asserts after a minimum  
of 50 mS  
9. Countdown timer expires; If enabled power domains are  
OK (I2C read) the power up sequence continues by  
enabling the processors 13 MHz oscillator and PLL’s.  
3. The Applications processor waits for the de-assertion of  
nBATT_FLT to indicate system power (VIN) is available.  
10. The Applications processor begins the execution of  
code.  
4. After system power (VIN) is turned on, the LP3972 de-  
asserts nBATT_FLT.  
5. The Applications processor asserts SYS_EN, the  
LP3972 enables the system high-voltage power sup-  
53  
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pending on the operating conditions and capacitor type. In  
particular, the output capacitor selection should take account  
of all the capacitor parameters, to ensure that the specifica-  
tion is met within the application. The capacitance can vary  
with DC bias conditions as well as temperature and fre-  
quency of operation. Capacitor values will also show some  
decrease over time due to aging. The capacitor parameters  
are also dependant on the particular case size, with smaller  
sizes giving poorer performance figures in general. As an  
example, Figure 4 shows a typical graph comparing different  
capacitor case sizes in a Capacitance vs. DC Bias plot. As  
shown in the graph, increasing the DC Bias condition can  
result in the capacitance value falling below the minimum  
value given in the recommended capacitor specifications  
table. Note that the graph shows the capacitance out of spec  
for the 0402 case size capacitor at higher bias voltages. It is  
therefore recommended that the capacitor manufacturers’  
specifications for the nominal value capacitor are consulted  
for all conditions, as some capacitor sizes (e.g. 0402) may  
not be suitable in the actual application.  
Application Hints  
LDO CONSIDERATIONS  
External Capacitors  
The LP3972’s regulators require external capacitors for  
regulator stability. These are specifically designed for por-  
table applications requiring minimum board space and small-  
est components. These capacitors must be correctly se-  
lected for good performance.  
Input Capacitor  
An input capacitor is required for stability. It is recommended  
that a 1.0 µF capacitor be connected between the LDO input  
pin and ground (this capacitance value may be increased  
without limit).  
This capacitor must be located a distance of not more than 1  
cm from the input pin and returned to a clean analogue  
ground. Any good quality ceramic, tantalum, or film capacitor  
may be used at the input.  
Important: Tantalum capacitors can suffer catastrophic fail-  
ures due to surge current when connected to a low imped-  
ance source of power (like a battery or a very large capaci-  
tor). If a tantalum capacitor is used at the input, it must be  
guaranteed by the manufacturer to have a surge current  
rating sufficient for the application.  
There are no requirements for the ESR (Equivalent Series  
Resistance) on the input capacitor, but tolerance and tem-  
perature coefficient must be considered when selecting the  
capacitor to ensure the capacitance will remain approxi-  
mately 1.0 µF over the entire operating temperature range.  
Output Capacitor  
The LDO’s are designed specifically to work with very small  
ceramic output capacitors. A 1.0 µF ceramic capacitor (tem-  
perature types Z5U, Y5V or X7R) with ESR between 5 mto  
500 m, are suitable in the application circuit.  
20207623  
For this device the output capacitor should be connected  
between the VOUT pin and ground.  
FIGURE 4. Graph Showing a Typical Variation in  
Capacitance vs. DC Bias  
It is also possible to use tantalum or film capacitors at the  
device output, COUT (or VOUT), but these are not as attrac-  
tive for reasons of size and cost (see the section Capacitor  
Characteristics).  
The ceramic capacitor’s capacitance can vary with tempera-  
ture. The capacitor type X7R, which operates over a tem-  
perature range of −55˚C to +125˚C, will only vary the capaci-  
tance to within 15%. The capacitor type X5R has a similar  
tolerance over a reduced temperature range of −55˚C to  
+85˚C. Many large value ceramic capacitors, larger than  
1 µF are manufactured with Z5U or Y5V temperature char-  
acteristics. Their capacitance can drop by more than 50% as  
the temperature varies from 25˚C to 85˚C. Therefore X7R is  
recommended over Z5U and Y5V in applications where the  
ambient temperature will change significantly above or be-  
low 25˚C.  
The output capacitor must meet the requirement for the  
minimum value of capacitance and also have an ESR value  
that is within the range 5 mto 500 mfor stability.  
No-Load Stability  
The LDO’s will remain stable and in regulation with no ex-  
ternal load. This is an important consideration in some cir-  
cuits, for example CMOS RAM keep-alive applications.  
Capacitor Characteristics  
Tantalum capacitors are less desirable than ceramic for use  
as output capacitors because they are more expensive when  
comparing equivalent capacitance and voltage ratings in the  
0.47 µF to 4.7 µF range.  
The LDO’s are designed to work with ceramic capacitors on  
the output to take advantage of the benefits they offer. For  
capacitance values in the range of 0.47 µF to 4.7 µF, ceramic  
capacitors are the smallest, least expensive and have the  
lowest ESR values, thus making them best for eliminating  
high frequency noise. The ESR of a typical 1.0 µF ceramic  
capacitor is in the range of 20 mto 40 m, which easily  
meets the ESR requirement for stability for the LDO’s.  
Another important consideration is that tantalum capacitors  
have higher ESR values than equivalent size ceramics. This  
means that while it may be possible to find a tantalum  
capacitor with an ESR value within the stable range, it would  
have to be larger in capacitance (which means bigger and  
more costly) than a ceramic capacitor with the same ESR  
value. It should also be noted that the ESR of a typical  
For both input and output capacitors, careful interpretation of  
the capacitor specification is required to ensure correct de-  
vice operation. The capacitor value can change greatly, de-  
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54  
A 2.2 µH inductor with a saturation current rating of at least  
TBD mA is recommended for most applications. The induc-  
tor’s resistance should be less than 0.3for a good effi-  
ciency. Table 1 lists suggested inductors and suppliers. For  
low-cost applications, an unshielded bobbin inductor could  
be considered. For noise critical applications, a toroidal or  
shielded bobbin inductor should be used. A good practice is  
to lay out the board with overlapping footprints of both types  
for design flexibility. This allows substitution of a low-noise  
shielded inductor, in the event that noise from low-cost bob-  
bin models is unacceptable.  
Application Hints (Continued)  
tantalum will increase about 2:1 as the temperature goes  
from 25˚C down to –40˚C, so some guard band must be  
allowed.  
BUCK CONSIDERATIONS  
Inductor Selection  
There are two main considerations when choosing an induc-  
tor; the inductor should not saturate, and the inductor current  
ripple is small enough to achieve the desired output voltage  
ripple. Different saturation current rating specs are followed  
by different manufacturers so attention must be given to  
details. Saturation current ratings are typically specified at  
25˚C so ratings at max ambient temperature of application  
should be requested from manufacturer.  
Input Capacitor Selection  
A ceramic input capacitor of 10 µF, 6.3V is sufficient for most  
applications. Place the input capacitor as close as possible  
to the VIN pin of the device. A larger value may be used for  
improved input voltage filtering. Use X7R or X5R types, do  
not use Y5V. DC bias characteristics of ceramic capacitors  
must be considered when selecting case sizes like 0805 and  
0603. The input filter capacitor supplies current to the PFET  
switch of the converter in the first half of each cycle and  
reduces voltage ripple imposed on the input power source. A  
ceramic capacitor’s low ESR provides the best noise filtering  
of the input voltage spikes due to this rapidly changing  
current. Select a capacitor with sufficient ripple current rat-  
ing. The input current ripple can be calculated as:  
There are two methods to choose the inductor saturation  
current rating.  
Method 1:  
The saturation current is greater than the sum of the maxi-  
mum load current and the worst case average to peak  
inductor current. This can be written as  
IRIPPLE: Average to peak inductor current  
IOUTMAX: Maximum load current (1500 mA)  
VIN: Maximum input voltage in application  
The worst case is when VIN = 2 * VOUT  
L: Min inductor value including worst case tolerances (30%  
drop can be considered for method 1)  
f: Minimum switching frequency (1.6 MHz)  
VOUT: Output voltage  
Method 2:  
A more conservative and recommended approach is to  
choose an inductor that has saturation current rating greater  
than the max current limit of TBD mA.  
TABLE 1. Suggested Inductors and Their Suppliers  
Vendor Dimensions LxWxH (mm)  
Toko 3.0 x 3.0 x 1.2  
Coilcraft 6.6 x 4.5 x 1.8  
Model  
D.C.R (Typ)  
160 mΩ  
FDSE0312-2R2M  
DO1608C-222  
80 mΩ  
Output Capacitor Selection  
The output voltage ripple is caused by the charging and  
discharging of the output capacitor and also due to its ESR  
and can be calculated as:  
Use a 10 µF, 6.3V ceramic capacitor. Use X7R or X5R types,  
do not use Y5V. DC bias characteristics of ceramic capaci-  
tors must be considered when selecting case sizes like 0805  
and 0603. DC bias characteristics vary from manufacturer to  
manufacturer and dc bias curves should be requested from  
them as part of the capacitor selection process. The output  
filter capacitor smooths out current flow from the inductor to  
the load, helps maintain a steady output voltage during  
transient load changes and reduces output voltage ripple.  
These capacitors must be selected with sufficient capaci-  
tance and sufficiently low ESR to perform these functions.  
Voltage peak-to-peak ripple due to ESR can be expressed  
as follows  
VPP-ESR = (2 * IRIPPLE) * RESR  
Because these two components are out of phase the rms  
value can be used to get an approximate value of peak-to-  
peak ripple.  
55  
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Note that the output voltage ripple is dependent on the  
inductor current ripple and the equivalent series resistance  
of the output capacitor (RESR).  
Application Hints (Continued)  
Voltage peak-to-peak ripple, root mean squared can be ex-  
pressed as follows  
The RESR is frequency dependent (as well as temperature  
dependent); make sure the value used for calculations is at  
the switching frequency of the part.  
TABLE 2. Suggested Capacitor and Their Suppliers  
Case Size  
Inch (mm)  
0805 (2012)  
0805 (2012)  
0805 (2012)  
Model  
Type  
Vendor  
Voltage  
GRM21BR60J106K  
JMK212BJ106K  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Murata  
Taiyo-Yuden  
TDK  
6.3V  
6.3V  
6.3V  
C2012X5R0J106K  
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56  
Application Hints (Continued)  
Buck Output Ripple Management  
If VIN and ILOAD increase, the output ripple associated with  
the Buck Regulators also increases. The figure below shows  
the safe operating area. To ensure operation in the area of  
concern it is recommended that the system designer circum-  
vents the output ripple issues to install schottky diodes on  
the Bucks(s) that are expected to perform under these ex-  
treme corner conditions.  
(Schottky diodes are recommended to reduce the output  
ripple, if system requirements include this shaded area of  
>
>
operation. VIN 1.5V and ILOAD 1.24)  
20207647  
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Board Layout Considerations  
PC board layout is an important part of DC-DC converter  
design. Poor board layout can disrupt the performance of a  
DC-DC converter and surrounding circuitry by contributing to  
EMI, ground bounce, and resistive voltage loss in the traces.  
These can send erroneous signals to the DC-DC converter  
IC, resulting in poor regulation or instability.  
per fill as a pseudo-ground plane. Then, connect this to  
the ground-plane (if one is used) with several vias. This  
reduces ground-plane noise by preventing the switching  
currents from circulating through the ground plane. It  
also reduces ground bounce at the converter by giving it  
a low-impedance ground connection.  
Good layout for the converters can be implemented by fol-  
lowing a few simple design rules.  
4. Use wide traces between the power components and for  
power connections to the DC-DC converter circuit. This  
reduces voltage errors caused by resistive losses across  
the traces.  
1. Place the converters, inductor and filter capacitors close  
together and make the traces short. The traces between  
these components carry relatively high switching cur-  
rents and act as antennas. Following this rule reduces  
radiated noise. Special care must be given to place the  
input filter capacitor very close to the VIN and GND pin.  
5. Route noise sensitive traces, such as the voltage feed-  
back path, away from noisy traces between the power  
components. The voltage feedback trace must remain  
close to the converter circuit and should be direct but  
should be routed opposite to noisy components. This  
reduces EMI radiated onto the DC-DC converter’s own  
voltage feedback trace. A good approach is to route the  
feedback trace on another layer and to have a ground  
plane between the top layer and layer on which the  
feedback trace is routed. In the same manner for the  
adjustable part it is desired to have the feedback divid-  
ers on the bottom layer.  
2. Arrange the components so that the switching current  
loops curl in the same direction. During the first half of  
each cycle, current flows from the input filter capacitor  
through the converter and inductor to the output filter  
capacitor and back through ground, forming a current  
loop. In the second half of each cycle, current is pulled  
up from ground through the converter by the inductor to  
the output filter capacitor and then back through ground  
forming a second current loop. Routing these loops so  
the current curls in the same direction prevents mag-  
netic field reversal between the two half-cycles and re-  
duces radiated noise.  
6. Place noise sensitive circuitry, such as radio RF blocks,  
away from the DC-DC converter, CMOS digital blocks  
and other noisy circuitry. Interference with noise-  
sensitive circuitry in the system can be reduced through  
distance.  
3. Connect the ground pins of the converter and filter ca-  
pacitors together using generous component-side cop-  
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58  
Physical Dimensions inches (millimeters) unless otherwise noted  
40-Pin Leadless Leadframe Package  
NS Package Number SQF40A  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves  
the right at any time without notice to change said circuitry and specifications.  
For the most current product information visit us at www.national.com.  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS  
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR  
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1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body, or  
(b) support or sustain life, and whose failure to perform when  
properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to result  
in a significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably  
expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
BANNED SUBSTANCE COMPLIANCE  
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and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:  
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Lead free products are RoHS compliant.  
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