LT1720CDD#TRPB全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

LT1720/LT1721

Dual/Quad,

4.5ns, Single Supply

3V/5V Comparators

with Rail-to-Rail Outputs

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FEATURES

DESCRIPTIO

The LT^®1720/LT1721 are UltraFast^TMdual/quad compara-

tors optimized for single supply operation, with a supply

voltage range of 2.7V to 6V. The input voltage range extends

from100mVbelowgroundto1.2Vbelowthesupplyvoltage.

Internal hysteresis makes the LT1720/LT1721 easy to use

even with slow moving input signals. The rail-to-rail outputs

directly interface to TTL and CMOS. Alternatively, the sym-

metric output drive can be harnessed for analog applications

or for easy translation to other single supply logic levels.

■

UltraFast: 4.5ns at 20mV Overdrive

7ns at 5mV Overdrive

■

Low Power: 4mA per Comparator

■

Optimized for 3V and 5V Operation

■

Pinout Optimized for High Speed Ease of Use

■

Input Voltage Range Extends 100mV

Below Negative Rail

■

TTL/CMOS Compatible Rail-to-Rail Outputs

■

Internal Hysteresis with Specified Limits

■

Low Dynamic Current Drain; 15µA/(V-MHz),

The LT1720 is available in the 8-pin MSOP and SO packages;

three pins per comparator plus power and ground. The

LT1721 is available in the 16-pin SSOP and S packages.

Dominated by Load In Most Circuits

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APPLICATIO S

ThepinoutsoftheLT1720/LT1721minimizeparasiticeffects

byplacingthemostsensitiveinputs(inverting)awayfromthe

outputs, shieldedbythepowerrails. TheLT1720/LT1721are

ideal for systems where small size and low power are

paramount.

■

High Speed Differential Line Receiver

■

Crystal Oscillator Circuits

■

Window Comparators

Threshold Detectors/Discriminators

Pulse Stretchers

Zero-Crossing Detectors

High Speed Sampling Circuits

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

UltraFast is a trademark of Linear Technology Corporation.

■

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TYPICAL APPLICATIO

2.7V to 6V Crystal Oscillator with TTL/CMOS Output

Propagation Delay vs Overdrive

8

2.7V TO 6V

25°C

1MHz TO 10MHz

7

6

5

4

3

2

1

0

V

C

= 100mV

= 10pF

STEP

CC

LOAD

2k

CRYSTAL (AT-CUT)

= 5V

RISING EDGE

(t

220Ω

)

PDLH

620Ω

GROUND

CASE

+

FALLING EDGE

(t

C1

)

PDHL

OUTPUT

1/2 LT1720

–

2k

1.8k

1720/21 TA01

0.01µF

10

20

OVERDRIVE (mV)

40

0

50

30

1720/21 TA02

1

LT1720/LT1721

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ABSOLUTE MAXIMUM RATINGS _{(Note 1)}

Storage Temperature Range ................. –65°C to 150°C

Operating Temperature Range

Supply Voltage, V_CCto GND ...................................... 7V

Input Current ...................................................... ±10mA

Output Current (Continuous) ............................. ±20mA

Junction Temperature........................................... 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

C Grade .................................................. 0°C to 70°C

I Grade .............................................. –40°C to 85°C

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PACKAGE/ORDER INFORMATION

TOP VIEW

–IN A

+IN A

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

–IN D

+IN D

TOP VIEW

V

CC

+IN A

–IN A

–IN B

+IN B

1

2

3

4

8

7

6

5

V

CC

+IN A

–IN A

–IN B

+IN B

1

2

3

4

8 V

CC

OUT A

OUT B

GND

OUT D

OUT C

7 OUT A

6 OUT B

5 GND

OUT A

OUT B

GND

V

CC

MS8 PACKAGE

8-LEAD PLASTIC MSOP

+IN B

–IN B

+IN C

–IN C

S8 PACKAGE

8-LEAD PLASTIC SO

T_JMAX= 150°C, θ_JA= 230°C/ W

GN PACKAGE

16-LEAD NARROW

PLASTIC SSOP

S PACKAGE

16-LEAD PLASTIC SO

T_JMAX= 150°C, θ_JA= 200°C/ W

T_JMAX= 150°C, θ_JA= 135°C/ W (GN)

T_JMAX= 150°C, θ_JA= 115°C/ W (S)

ORDER PART

NUMBER

MS8

PART MARKING

ORDER PART

NUMBER

S8

ORDER PART

NUMBER

GN

PART MARKING

LT1720CMS8

LTDS

LT1720CS8

LT1720IS8

1720

1720I

LT1721CGN

LT1721CS

LT1721IGN

LT1721IS

1721

1721I

Consult factory for Military grade parts.

The ● denotes specifications that apply over the full operating temperature

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at T_A= 25°C. V_CC= 5V, V_CM= 1V, C_OUT= 10pF, V_OVERDRIVE= 20mV, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

2.7

TYP

MAX

UNITS

V

Supply Voltage

●

6

V

CC

Common Mode Voltage Range

Input Trip Points

(Note 2)

(Note 3)

–0.1

V

– 1.2

CC

CMR

TRIP

+

–

–2.0

–3.0

5.5

6.5

mV

●

V

Input Trip Points

(Note 3)

–5.5

–6.5

2.0

3.0

mV

TRIP

OS

Input Offset Voltage

1.0

3.0

4.5

mV

●

Input Hysteresis Voltage

Input Offset Voltage Drift

2.0

3.5

10

5.0

mV

HYST

∆V /∆T

µV/°C

OS

2

LT1720/LT1721

The ● denotes specifications that apply over the full operating temperature

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at T_A= 25°C. V_CC= 5V, V_CM= 1V, C_OUT= 10pF, V_OVERDRIVE= 20mV, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

0

UNITS

µA

I

Input Bias Current

●

–6

B

Input Offset Current

0.6

µA

OS

CMRR

PSRR

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Voltage Gain

(Note 4)

(Note 5)

(Note 6)

55

65

70

80

∞

dB

A

V

+

Output High Voltage

Output Low Voltage

I

= 4mA, V = V

+ 10mV

●

V – 0.4

CC

V

OH

OL

SOURCE

IN

TRIP

–

= 10mA, V = V

– 10mV

0.4

SINK

IN

TRIP

I

t

Supply Current (Per Comparator)

V

= 5V

= 3V

●

4

3.5

7

6

mA

CC

Propagation Delay

V

= 20mV (Note 7)

4.5

7

6.5

8.0

ns

PD20

PD5

OVERDRIVE

●

V

= 5mV (Notes 7, 8)

10

13

ns

OVERDRIVE

∆t

Differential Propagation Delay

Propagation Delay Skew

Output Rise Time

(Note 9) Between Channels

0.3

0.5

2.5

2.2

1.0

1.5

ns

PD

+

–

t

(Note 10) Between t /t

SKEW

PD PD

10% to 90%

90% to 10%

r

Output Fall Time

f

+

–

Output Timing Jitter

V

= 1.2V (6dBm), Z = 50Ω

t

15

11

ps

JITTER

IN

P-P

IN

PD

RMS

= 2V, f = 20MHz

CM

PD

f

Maximum Toggle Frequency

V

= 50mV, V = 3V

70.0

62.5

MHz

MAX

OVERDRIVE

CC

= 50mV, V = 5V

CC

Note 1: Absolute Maximum Ratings are those values beyond which the

life of a device may be impaired.

Note 7: Propagation delay measurements made with 100mV steps.

Overdrive is measured relative to V_TRIP.

±

Note 2: If one input is within these common mode limits, the other

input can go outside the common mode limits and the output will be

valid.

Note 3: The LT1720/LT1721 comparators include internal hysteresis.

The trip points are the input voltage needed to change the output state

Note 8: t_PDcannot be measured in automatic handling equipment with

low values of overdrive. The LT1720/LT1721 are 100% tested with a

100mV step and 20mV overdrive. Correlation tests have shown that

t_PDlimits can be guaranteed with this test, if additional DC tests are

performed to guarantee that all internal bias conditions are correct.

Note 9: Differential propagation delay is defined as the larger of the

two:

+

in each direction. The offset voltage is defined as the average of V_TRIP

and V_TRIP^–, while the hysteresis voltage is the difference of these two.

Note 4: The common mode rejection ratio is measured with V_CC= 5V

∆t_PDLH= t_PDLH(MAX)– t_PDLH(MIN)

∆t_PDHL= t_PDHL(MAX)– t_PDHL(MIN)

where (MAX) and (MIN) denote the maximum and minimum values of

a given measurement across the different comparator channels.

and is defined as the change in offset voltage measured from V_CM

–0.1V to V_CM= 3.8V, divided by 3.9V.

=

Note 5: The power supply rejection ratio is measured with V_CM= 1V

and is defined as the change in offset voltage measured from V_CC

2.7V to V_CC= 6V, divided by 3.3V.

Note 6: Because of internal hysteresis, there is no small-signal region

in which to measure gain. Proper operation of internal circuity is

ensured by measuring V_OHand V_OLwith only 10mV of overdrive.

=

Note 10: Propagation Delay Skew is defined as:

t_SKEW= |t_PDLH– t_PDHL

|

3

LT1720/LT1721

TYPICAL PERFORMANCE CHARACTERISTICS

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Input Offset and Trip Voltages

vs Supply Voltage

Input Offset and Trip Voltages

vs Temperature

Input Common Mode Limits

vs Temperature

3

2

3

2

4.2

4.0

V

CC

= 5V

+

V

TRIP

V

TRIP

3.8

3.6

0.2

0

1

0

1

V

OS

0

–1

–2

–3

–1

–2

–3

–

V

TRIP

–0.2

25°C

CM

V

= 1V

–0.4

–50 –25

0

25

50

75 100 125

4.5

SUPPLY VOLTAGE (V)

5.5 6.0

50

TEMPERATURE (°C)

100 125

2.5 3.0

3.5 4.0

5.0

–50

25

75

–25

0

TEMPERATURE (°C)

1720/21 G02

1720/21 G01

1720/21 G03

Input Current

vs Differential Input Voltage

Quiescent Supply Current

vs Temperature

Quiescent Supply Current

vs Supply Voltage

7

6

5

4

3

2

1

0

2

1

6.0

25°C

CC

V

= 5V

125°C

5.5

5.0

0

–1

–2

–3

–4

–5

–6

–7

4.5

4.0

3.5

3.0

2.5

25°C

V

CC

= 5V

–55°C

V

CC

= 3V

2.0

0

2

3

4

5

6

7

–25

0

50

75 100 125

1

–50

25

–5 –4 –3 –2 –1

0

5

1

2

3

4

SUPPLY VOLTAGE (V)

DIFFERENTIAL INPUT VOLTAGE (V)

TEMPERATURE (˚C)

1720/21 G06

1720/21 G05

1720/21 G04

Propagation Delay

vs Load Capacitance

Propagation Delay

vs Temperature

Propagation Delay

vs Supply Voltage

9

8.0

5.0

4.5

4.0

t

25°C

STEP

PDLH

CM

STEP

LOAD

25°C

STEP

RISING EDGE

(t

V

C

= 1V

= 100mV

= 10pF

8

7

6

5

4

3

2

1

0

V

= 100mV

V

= 100mV

7.5

7.0

)

PDLH

OVERDRIVE = 20mV

= 5V

OVERDRIVE = 20mV

= 10pF

V

= 3V

CC

V

CC

C

LOAD

V

= 5V

6.5

6.0

5.5

5.0

4.5

CC

FALLING EDGE

(t

RISING EDGE

(t

)

PDHL

)

OVERDRIVE = 5mV

OVERDRIVE = 20mV

PDLH

V

CC

= 5V

FALLING EDGE

(t

PDHL

)

V

CC

= 3V

4.0

10

20

40

0

50

30

4.5

5.5

6.0

–25

0

50

75 100 125

2.5 3.0

3.5 4.0

5.0

–50

25

OUTPUT LOAD CAPACITANCE (pF)

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

1720/21 G07

1720/21 G08

1720/21 G09

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LT1720/LT1721

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TYPICAL PERFORMANCE CHARACTERISTICS

Output High Voltage

vs Load Current

Output Low Voltage

vs Load Current

Supply Current vs Frequency

0.5

0.4

0.3

0.2

0.1

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

10

9

25°C

CC

V

= 5V

= 1V

V

= 5V

= 1V

CC

CM

IN

CC

CM

IN

V

= 5V

125°C

= 15mV

= –15mV

125°C

= 2.7V

8

V

CC

–55°C

C

= 20pF

LOAD

25°C

7

6

5

4

3

25°C

–55°C

NO LOAD

25°C

= 2.7V

V

CC

4

8

12

16

20

10

20

FREQUENCY (MHz)

40

0

4

8

12

16

20

0

30

OUTPUT SINK CURRENT (mA)

OUTPUT SOURCE CURRENT (mA)

1720/21 G10

1720/21 G11

1720/21 G12

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PIN FUNCTIONS

LT1720

LT1721

–IN A (Pin 1): Inverting Input of Comparator A.

+IN A (Pin 1): Noninverting Input of Comparator A.

–IN A (Pin 2): Inverting Input of Comparator A.

–IN B (Pin 3): Inverting Input of Comparator B.

+IN B (Pin 4): Noninverting Input of Comparator B.

GND (Pin 5): Ground.

+IN A (Pin 2): Noninverting Input of Comparator A.

GND (Pins 3, 6): Ground.

OUT A (Pin 4): Output of Comparator A.

OUT B (Pin 5): Output of Comparator B.

OUT B (Pin 6): Output of Comparator B.

OUT A (Pin 7): Output of Comparator A.

V_CC(Pin 8): Positive Supply Voltage.

+IN B (Pin 7): Noninverting Input of Comparator B.

–IN B (Pin 8): Inverting Input of Comparator B.

–IN C (Pin 9): Inverting Input of Comparator C.

+IN C (Pin 10): Noninverting Input of Comparator C.

V_CC(Pins 11, 14): Positive Supply Voltage.

OUT C (Pin 12): Output of Comparator C.

OUT D (Pin 13): Output of Comparator D.

+IN D (Pin 15): Noninverting Input of Comparator D.

–IN D (Pin 16): Inverting Input of Comparator D.

5

LT1720/LT1721

TEST CIRCUITS

±V_TRIPTest Circuit

15V

P-P

LTC203

BANDWIDTH-LIMITED

TRIANGLE WAVE

~

1kHz

14

15

3

2

V

CC

0.1µF

+

1000 × V

TRIP

50k

10nF

1µF

10k

+

–

16

9

1

8

50Ω

1/2 LT1112

200k

+

–

1000 × V

HYST

DUT

1/2 LT1720 OR

1/4 LT1721

V

CM

11

10

6

7

1000 × V

OS

10k

LTC203

3

2

14

15

1/2 LT1638

+

–

1000 × V

TRIP

100k

1µF

10nF

–

1

8

16

9

+

–

2.4k

100k

1/2 LT1638

1/2 LT1112

+

–

0.15µF

6

7

11

10

1720/21 TC01

NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V.

200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS

WHEN DUT IS NOT POWERED

Response Time Test Circuit

+V – V

CC

CM

0V

DUT

1/2 LT1720 OR

1/4 LT1721

–100mV

0.01µF

+

–

25Ω

10 × SCOPE PROBE

(C ≈ 10pF)

25Ω

50k

IN

0.01µF

50Ω

V1*

0.1µF

130Ω

400Ω

PULSE

IN

2N3866

0V

1N5711

–V

+

CM

–3V

50Ω

750Ω

*V1 = –1000 • (OVERDRIVE + V

TRIP

)

NOTE: RISING EDGE TEST SHOWN.

FOR FALLING EDGE, REVERSE LT1720 INPUTS

1720/21 TC02

–5V

6

LT1720/LT1721

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APPLICATIONS INFORMATION

Input Voltage Considerations

Input Protection

The LT1720/LT1721 are specified for a common mode

range of –100mV to 3.8V when used with a single 5V

supply. In general the common mode range is 100mV

below ground to 1.2V below V_CC. The criterion for this

common mode limit is that the output still responds

correctly to a small differential input signal. Also, if one

input is within the common mode limit, the other input

signal can go outside the common mode limits, up to the

absolute maximum limits (a diode drop past either rail at

10mA input current) and the output will retain the correct

polarity.

The input stage is protected against damage from large

differential signals, up to and beyond a differential voltage

equal to the supply voltage, limited only by the absolute

maximum currents noted. External input protection cir-

cuitry is only needed if currents would otherwise exceed

these absolute maximums. The internal catch diodes can

conduct current up to these rated maximums without

latchup, even when the supply voltage is at the absolute

maximum rating.

The LT1720/LT1721 input stage has general purpose

internalESDprotectionforthehumanbodymodel.Foruse

as a line receiver, additional external protection may be

required. As with most integrated circuits, the level of

immunity to ESD is much greater when residing on a

printed circuit board where the power supply decoupling

capacitance will limit the voltage rise caused by an ESD

pulse.

When either input signal falls below the negative common

mode limit, the internal PN diode formed with the sub-

strate can turn on, resulting in significant current flow

through the die. An external Schottky clamp diode

between the input and the negative rail can speed up

recovery from negative overdrive by preventing the sub-

strate diode from turning on.

Input Bias Current

When both input signals are below the negative common

mode limit, phase reversal protection circuitry prevents

false output inversion to at least –400mV common mode.

However, the offset and hysteresis in this mode will

increasedramatically,toasmuchas15mVeach.Theinput

bias currents will also increase.

Inputbiascurrentismeasuredwithbothinputsheldat1V.

As with any PNP differential input stage, the LT1720/

LT1721 bias current flows out of the device. With a

differential input voltage of even just 100mV or so, there

will be zero bias current into the higher of the two inputs,

while the current flowing out of the lower input will be

twice the measured bias current. With more than two

diode drops of differential input voltage, the LT1720/

LT1721’s input protection circuitry activates, and current

out of the lower input will increase an additional 30% and

there will be a small bias current into the higher of the two

input pins, of 4µA or less. See the Typical Performance

curve “Input Current vs Differential Input Voltage.”

When both input signals are above the positive common

mode limit, the input stage will become debiased and the

output polarity will be random. However, the internal

hysteresis will hold the output to a valid logic level, and

because the biasing of each comparator is completely

independent, there will be no impact on any other com-

parator. When at least one of the inputs returns to within

thecommonmodelimits,recoveryfromthisstatewilltake

as long as 1µs.

High Speed Design Considerations

The propagation delay does not increase significantly

whendrivenwithlargedifferentialvoltages.However,with

low levels of overdrive, an apparent increase may be seen

with large source resistances due to an RC delay caused

by the 2pF typical input capacitance.

Application of high speed comparators is often plagued

by oscillations. The LT1720/LT1721 have 4mV of internal

hysteresis, which will prevent oscillations as long as

parasitic output to input feedback is kept below 4mV.

7

LT1720/LT1721

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APPLICATIONS INFORMATION

However, with the 2V/ns slew rate of the LT1720/LT1721

outputs, a 4mV step can be created at a 100Ω input

source with only 0.02pF of output to input coupling. The

pinouts of the LT1720/LT1721 have been arranged to

minimize problems by placing the most sensitive inputs

(inverting) away from the outputs, shielded by the power

rails. The input and output traces of the circuit board

should also be separated, and the requisite level of

isolationisreadilyachievedifatopsidegroundplaneruns

betweentheoutputsandtheinputs. Formultilayerboards

where the ground plane is internal, a topside ground or

supply trace should be run between the inputs and

outputs, as illustrated in Figure 1.

The supply bypass should include an adjacent

10nF ceramic capacitor and a 2.2µF tantalum capacitor no

farther than 5cm away; use more capacitance if driving

more than 4mA loads. To prevent oscillations, it is helpful

tobalancetheimpedanceattheinvertingandnoninverting

inputs; source impedances should be kept low, preferably

1kΩ or less.

The outputs of the LT1720/LT1721 are capable of very

high slew rates. To prevent overshoot, ringing and other

problems with transmission line effects, keep the output

traces shorter than 10cm, or be sure to terminate the lines

to maintain signal integrity. The LT1720/LT1721 can drive

DCterminationsof250Ωormore,butlowercharacteristic

impedance traces can be driven with series termination or

AC termination topologies.

Hysteresis

The LT1720/LT1721 include internal hysteresis, which

makes them easier to use than many other comparable

speed comparators.

(a)

(b)

1720/21 F01

The input-output transfer characteristic is illustrated in

Figure 2 showing the definitions of V_OSand V_HYSTbased

upon the two measurable trip points. The hysteresis band

makestheLT1720/LT1721wellbehaved, evenwithslowly

moving inputs.

Figure 1. Typical Topside Metal for Multilayer PCB Layouts

Figure 1a shows a typical topside layout of the LT1720 on

such a multilayer board. Shown is the topside metal etch

including traces, pin escape vias, and the land pads for an

SO-8 LT1720 and its adjacent X7R 10nF bypass capacitor

in a 1206 case.

The ground trace from Pin 5 runs under the device up to

the bypass capacitor, shielding the inputs from the

outputs. Note the use of a common via for the LT1720 and

the bypass capacitor, which minimizes interference from

highfrequencyenergyrunningaroundthegroundplaneor

power distribution traces.

V

OH

V

HYST

+

–

(= V

– V

)

TRIP

V

/2

HYST

Figure 1b shows a typical topside layout of the LT1721 on

a multilayer board. In this case, the power and ground

traces have been extended to the bottom of the device

solely to act as high frequency shields between input and

output traces.

V

OL

+

–

∆V = V – V

IN

0

–

+

V

TRIP

+

–

V

+ V

2

TRIP

V

=

OS

1720/21 F02

Although both V_CCpins are electrically shorted internal to

the LT1721, they must be shorted together externally as

well in order for both to function as shields. The same is

true for the two GND pins.

Figure 2. Hysteresis I/O Characteristics

8

LT1720/LT1721

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APPLICATIONS INFORMATION

The exact amount of hysteresis will vary from part to part

asindicatedinthespecificationstable.Thehysteresislevel

will also vary slightly with changes in supply voltage and

common mode voltage. A key advantage of the LT1720/

LT1721 is the significant reduction in these effects, which

is important whenever an LT1720/LT1721 is used to de-

tect a threshold crossing in one direction only. In such a

case, the relevant trip point will be all that matters, and a

stable offset voltage with an unpredictable level of hyster-

esis, as seen in competing comparators, is of little value.

TheLT1720/LT1721aremanytimesbetterthanpriorcom-

parators in these regards. In fact, the CMRR and PSRR

tests are performed by checking for changes in either trip

point to the limits indicated in the specifications table.

Because the offset voltage is the average of the trip points,

the CMRR and PSRR of the offset voltage is therefore

guaranteed to be at least as good as those limits. This

more stringent test also puts a limit on the common mode

and power supply dependence of the hysteresis voltage.

voltage on the right side of R3 is 300mV or V_CC– 300mV,

for a total voltage swing of (V_CC– 300mV) – 300mV =

V_CC– 600mV.

Withthisinmind, calculationoftheresistorvaluesneeded

isatwo-stepprocess.First,calculatethevalueofR3based

on the additional hysteresis desired, the output voltage

swing, and the impedance of the primary bias string:

R3 = (R1 R2)(V_CC– 0.6V)/(additional hysteresis)

Additional hysteresis is the desired overall hysteresis less

the internal 3.5mV hysteresis.

The second step is to recalculate R2 to set the same

averagethresholdasbefore. Theaveragethresholdbefore

was set at V_TH= (V_REF)(R1)/(R1 + R2). The new R2 is

calculated based on the average output voltage (V_CC/2)

and the simplified circuit model in Figure 4. To assure that

the comparator’s noninverting input is, on average, the

same V_THas before:

R2′ = (V_REF– V_TH)/(V_TH/R1 + (V_TH– V_CC/2)/R3)

Additionalhysteresismaybeaddedexternally. Therail-to-

rail outputs of the LT1720/LT1721 make this more pre-

dictable than with TTL output comparators due to the

LT1720/LT1721’s small variability of V_OH(output high

voltage).

For additional hysteresis of 10mV or less, it is not uncom-

mon for R2′ to be the same as R2 within 1% resistor

tolerances.

This method will work for additional hysteresis of up to a

few hundred millivolts. Beyond that, the impedance of R3

is low enough to effect the bias string, and adjustment of

R1 may also be required. Note that the currents through

the R1/R2 bias string should be many times the input

currents of the LT1720/LT1721. For 5% accuracy, the

current must be at least 120µA(6µA I_B÷ 0.05); more for

higher accuracy.

To add additional hysteresis, set up positive feedback by

adding additional external resistor R3 as shown in Figure

3. ResistorR3addsaportionoftheoutputtothethreshold

set by the resistor string. The LT1720/LT1721 pulls the

outputs to the supply rail and ground to within 200mV of

the rails with light loads, and to within 400mV with heavy

loads. For the load of most circuits, a good model for the

V

REF

R2′

V

REF

V

TH

R3

V

2

CC

V

=

AVERAGE

R2

R1

+

1/2 LT1720

R1

–

1720/21 F04

INPUT

1720/21 F03

Figure 3. Additional External Hysteresis

Figure 4. Model for Additional Hysteresis Calculations

9

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Interfacing the LT1720/LT1721 to ECL

100µA of forward current. R4 prevents this with the

minimum additional power dissipation.

The LT1720/LT1721 comparators can be used in high

speed applications where Emitter-Coupled Logic (ECL) is

deployed. To interface the outputs of the LT1720/LT1721

to ECL logic inputs, standard TTL/CMOS to ECL level

translators such as the 10H124, 10H424 and 100124 can

be used. These components come at a cost of a few

nanosecondsadditionaldelayaswellassupplycurrentsof

50mA or more, and are only available in quads. A faster,

simpler and lower power translator can be constructed

with resistors as shown in Figure 5.

Finally, Figure 5d shows the case of driving standard,

negative-rail, ECL with the LT1720/LT1721. Resistor val-

ues are given for both ECL interface types and for both a

5V and 3V LT1720/LT1721 supply rail. Again, a fourth

resistor,R4isneededtopreventthelowstatecurrentfrom

flowing out of the LT1720/LT1721, turning on the internal

ESD/substrate diodes. Not only can the output stage func-

tionality and speed suffer, but in this case the substrate is

common to all the comparators in the LT1720/LT1721, so

operation of the other comparator(s) in the same package

could also be affected. Resistor R4 again prevents this

with the minimum additional power dissipation.

Figure 5a shows the standard TTL to Positive ECL (PECL)

resistive level translator. This translator cannot be used

for the LT1720/LT1721, or with CMOS logic, because it

depends on the 820Ω resistor to limit the output swing

(V_OH)oftheall-NPNTTLgatewithitsso-calledtotem-pole

output. The LT1720/LT1721 are fabricated in a comple-

mentary bipolar process and their output stage has a PNP

driver that pulls the output nearly all the way to the supply

rail, even when sourcing 10mA.

For all the dividers shown, the output impedance is about

110Ω. This makes these fast, less than a nanosecond,

with most layouts. Avoid the temptation to use speedup

capacitors. Not only can they foul up the operation of the

ECL gate because of overshoots, they can damage the

ECL inputs, particularly during power-up of separate

supply configurations.

Figure 5b shows a three resistor level translator for inter-

facing the LT1720/LT1721 to ECL running off the same

supply rail. No pull-down on the output of the LT1720/

LT1721 is needed, but pull-down R3 limits the V_IHseen by

the PECL gate. This is needed because ECL inputs have

both a minimum and maximum V_IHspecification for

proper operation. Resistor values are given for both ECL

interface types; in both cases it is assumed that the

LT1720/LT1721 operates from the same supply rail.

The level translator designs assume one gate load. Mul-

tiple gates can have significant I_IHloading, and the trans-

missionlineroutingandterminationissuesalsomakethis

case difficult.

ECL,andparticularlyPECL,isvaluabletechnologyforhigh

speed system design, but it must be used with care. With

less than a volt of swing, the noise margins need to be

evaluated carefully. Note that there is some degradation of

noise margin due to the ±5% resistor selections shown.

With10KH/E,thereisnotemperaturecompensationofthe

logic levels, whereas the LT1720/LT1721 and the circuits

shown give levels that are stable with temperature. This

will degrade the noise margin over temperature. In some

configurations it is possible to add compensation with

diode or transistor junctions in series with the resistors of

these networks.

Figure 5c shows the case of translating to PECL from an

LT1720/LT1721 powered by a 3V supply rail. Again,

resistorvaluesaregivenforbothECLinterfacetypes.This

time four resistors are needed, although with 10KH/E, R3

is not needed. In that case, the circuit resembles the

standard TTL translator of Figure 5a, but the function of

the new resistor, R4, is much different. R4 loads the

LT1720/LT1721 output when high so that the current

flowing through R1 doesn’t forward bias the LT1720/

LT1721’s internal ESD clamp diode. Although this diode

can handle 20mA without damage, normal operation and

performance of the output stage can be impaired above

For more information on ECL design, refer to the ECLiPS

data book (DL140), the 10KH system design handbook

(HB205) and PECL design (AN1406), all from Motorola.

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5V

180Ω

270Ω

820Ω

DO NOT USE FOR LT1720/LT1721

LEVEL TRANSLATION. SEE TEXT

LSTTL

10KH/E

(a) STANDARD TTL TO PECL TRANSLATOR

V

CC

R2

R1

V

R1

10KH/E 5V OR 5.2V 510Ω 180Ω 750Ω

100K/E 4.5V 620Ω 180Ω 510Ω

R2

R3

CC

1/2 LT1720

R3

(b) LT1720/LT1721 OUTPUT TO PECL TRANSLATOR

V

CC

3V

R2

R1

R4

V

R1

R2

R3

R4

CC

1/2 LT1720

10KH/E 5V OR 5.2V 300Ω 180Ω OMIT 560Ω

100K/E

4.5V

330Ω 180Ω 1500Ω 1000Ω

R3

(c) 3V LT1720/LT1721 OUTPUT TO PECL TRANSLATOR

V

CC

R4

ECL FAMILY

V

R1

R2

R3

R4

EE

CC

R1

5V

3V

5V

3V

560Ω 270Ω 330Ω 1200Ω

270Ω 510Ω 300Ω 330Ω

680Ω 270Ω 300Ω 1500Ω

330Ω 390Ω 270Ω 430Ω

1720/21 F05

1/2 LT1720

10KH/E

–5.2V

–4.5V

R2

R3

100K/E

V

EE

(d) LT1720/LT1721 OUTPUT TO STANDARD ECL TRANSLATOR

Figure 5

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Circuit Description

Technology’s rail-to-rail ampliﬁers and other products.

But the output of a comparator is digital, and this output

stagecandriveTTLorCMOSdirectly.ItcanalsodriveECL,

as described earlier, or analog loads as demonstrated in

the applications to follow.

TheblockdiagramofonecomparatorintheLT1720/LT1721

is shown in Figure 6. There are differential inputs

(+IN/–IN), an output (OUT), a single positive supply (V_CC)

and ground (GND). All comparators are completely inde-

pendent, sharing only the power and ground pins. The

circuit topology consists of a differential input stage, a

gain stage with hysteresis and a complementary

common-emitter output stage. All of the internal signal

pathsutilizelowvoltageswingsforhighspeedatlowpower.

Thebiasconditionsandsignalswingsintheoutputstages

are designed to turn their respective output transistors off

faster than on. This nearly eliminates the surge of current

from V_CCto ground that occurs at transitions, keeping the

power consumption low even with high output-toggle

frequencies.

The input stage topology maximizes the input dynamic

range available without requiring the power, complexity

and die area of two complete input stages such as are

foundinrail-to-railinputcomparators.Witha2.7Vsupply,

the LT1720/LT1721 still have a respectable 1.6V of input

common mode range. The differential input voltage range

is rail-to-rail, without the large input currents found in

competing devices. The input stage also features phase

reversal protection to prevent false outputs when the

inputs are driven below the –100mV common mode

voltage limit.

The low surge current is what keeps the power consump-

tion low at high output-toggle frequencies. The frequency

dependence of the supply current is shown in the Typical

Performance Characteristics. Just 20pF of capacitive load

on the output more than triples the frequency dependent

rise. Theslopeoftheno-loadcurveisjust32µA/MHz. With

a 5V supply, this current is the equivalent of charging and

discharging just 6.5pF. The slope of the 20pF load curve is

133µA/MHz, an addition of 101µA/MHz, or 20µA/MHz-V,

units that are equivalent to picoFarads.

Theinternalhysteresisisimplementedbypositive,nonlin-

ear feedback around a second gain stage. Until this point,

the signal path has been entirely differential. The signal

path is then split into two drive signals for the upper and

lower output transistors. The output transistors are con-

nected common emitter for rail-to-rail output operation.

The Schottky clamps limit the output voltages at about

300mVfromtherail, notquitethe50mVor15mVofLinear

The LT1720/LT1721 dynamic current can be estimated by

addingtheexternalcapacitiveloadingtoaninternalequiva-

lent capacitance of 5pF to 15pF, multiplied by the toggle

frequency and the supply voltage. Because the capaci-

tance of routing traces can easily approach these values,

the dynamic current is dominated by the load in most

circuits.

V

NONLINEAR STAGE

CC

+

–

+

Σ

+IN

+

–

+

–

A

OUT

V1

V2

+

Σ

–IN

+

–

GND

1720/21 F06

Figure 6. LT1720/LT1721 Block Diagram

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Speed Limits

The second output speed limit is the clamp turnaround.

The LT1720/LT1721 output is optimized for fast initial

response, with some loss of turnaround speed, limiting

the toggle frequency. The output transistors are idled in a

low power state once V_OHor V_OLis reached by detecting

the Schottky clamp action. It is only when the output has

slewed from the old voltage to the new voltage, and the

clamp circuitry has settled, that the idle state is reached

andtheoutputisfullyreadytotransitionagain. Thisclamp

turnaround time is typically 8ns for each direction, result-

ing in a maximum toggle frequency of 62.5MHz, or a

125MB data rate. With higher frequencies, dropout and

runt pulses can occur. Increases in capacitive load will

increase the time needed for slewing due to the limited

slew currents and the maximum toggle frequency will

decrease further. For higher toggle frequency applica-

tions, consider the LT1394, whose linear output stage can

toggle at 100MHz typical.

The LT1720/LT1721 comparators are intended for high

speed applications, where it is important to understand a

few limitations. These limitations can roughly be divided

into three categories: input speed limits, output speed

limits, and internal speed limits.

There are no signiﬁcant input speed limits except the

shunt capacitance of the input nodes. If the 2pF typical

input nodes are driven, the LT1720/LT1721 will respond.

The output speed is constrained by two mechanisms, the

firstofwhichistheslewcurrentsavailablefromtheoutput

transistors. To maintain low power quiescent operation,

the LT1720/LT1721 output transistors are sized to deliver

25mA to 45mA typical slew currents. This is sufﬁcient to

drive small capacitive loads and logic gate inputs at

extremelyhighspeeds.Buttheslewratewillslowdramati-

callywithheavycapacitiveloads.Becausethepropagation

delay (t_PD) deﬁnition ends at the time the output voltage is

halfway between the supplies, the ﬁxed slew current

actually makes the LT1720/LT1721 faster at 3V than 5V

with 20mV of input overdrive.

The internal speed limits manifest themselves as disper-

sion. All comparators have some degree of dispersion,

deﬁned as a change in propagation delay versus input

overdrive. The propagation delay of the LT1720/LT1721

will vary with overdrive, from a typical of 4.5ns at 20mV

overdrive to 7ns at 5mV overdrive (typical). The LT1720/

LT1721’s primary source of dispersion is the hysteresis

stage. As a change of polarity arrives at the gain stage, the

positive feedback of the hysteresis stage subtracts from

the overdrive available. Only when enough time has

elapsedforasignaltopropagateforwardthroughthegain

stage, backwards through the hysteresis stage and for-

ward through the gain stage again, will the output stage

receive the same level of overdrive that it would have

received in the absence of hysteresis.

Another manifestation of this output speed limit is skew,

the difference between t_PD⁺and t_PD^–. The slew currents of

theLT1720/LT1721varywiththeprocessvariationsofthe

PNP and NPN transistors, for rising edges and falling

edges respectively. The typical 0.5ns skew can have either

polarity, rising edge or falling edge faster. Again, the skew

will increase dramatically with heavy capacitive loads.

The skews of comparators in a single package are corre-

lated, but not identical. Besides some random variability,

there is a small (100ps to 200ps) systematic skew due to

physical parasitics of the packages. For the LT1720 SO-8,

comparatorA, whoseoutputisadjacenttotheV_CCpin, will

have a relatively faster rising edge than comparator B.

Likewise, comparator B, by virtue of an output adjacent to

the ground pin will have a relatively faster falling edge.

Similar dependencies occur in the LT1721 S16, while the

systemic skews in the smaller MSOP and SSOP packages

arehalfagainassmall. Ofcourse, ifthecapacitiveloadson

the two comparators of a single package are not identical,

the differential timing will degrade further.

With5mVofoverdrive, theLT1720/LT1721arefasterwith

a 5V supply than with a 3V supply, the opposite of what is

true with 20mV overdrive. This is due to the internal speed

limit, because the gain stage is faster at 5V than 3V due

primarily to the reduced junction capacitances with higher

reverse voltage bias.

Inmanyapplications, asshowninthefollowingexamples,

there is plenty of input overdrive. Even in applications

providing low levels of overdrive, the LT1720/LT1721 are

13

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APPLICATIONS INFORMATION

fast enough that the absolute dispersion of 2.5ns

noninvertinginput.ThecircuitwilloperatewithanyAT-cut

crystal from 1MHz to 10MHz over a 2.7V to 6V supply

range. As the power is applied, the circuit remains off until

the LT1720/LT1721 bias circuits activate, at a typical V_CC

of 2V to 2.2V (25°C), at which point the desired frequency

output is generated.

(= 7 – 4.5) is often small enough to ignore.

The gain and hysteresis stage of the LT1720/LT1721 is

simple, short and high speed to help prevent parasitic

oscillations while adding minimum dispersion. This in-

ternal “self-latch” can be usefully exploited in many

applicationsbecauseitoccursearlyinthesignalchain, in

a low power, fully differential stage. It is therefore highly

immune to disturbances from other parts of the circuit,

either in the same comparator, on the supply lines, or

from the other comparator(s) in the same package. Once

a high speed signal trips the hysteresis, the output will

respond, after a ﬁxed propagation delay, without regard

to these external inﬂuences that can cause trouble in

nonhysteretic comparators.

The output duty cycle for this circuit is roughly 50%, but

it is affected by resistor tolerances and, to a lesser extent,

by comparator offsets and timings. If a 50% duty cycle is

required, the circuit of Figure 7 creates a pair of comple-

mentary outputs with a forced 50% duty cycle. Crystals

are narrow-band elements, so the feedback to the nonin-

vertinginputisaﬁlteredanalogversionofthesquarewave

output.Changingthenoninvertingreferencelevelcanthere-

fore vary the duty cycle. C1 operates as in the previous

example, whereas C2 creates a complementary output by

comparing the same two nodes with the opposite input

polarity. A1 compares band-limited versions of the out-

puts and biases C1’s negative input. C1’s only degree of

freedom to respond is variation of pulse width; hence the

outputs are forced to 50% duty cycle. Again, the circuit

operatesfrom2.7Vto6V, andtheskewbetweentheedges

of the two outputs are shown in Figure 8. There is a slight

duty cycle dependence on comparator loading, so equal

capacitive and resistive loading should be used in critical

±V_TRIPTest Circuit

The input trip points are tested using the circuit shown in

the Test Circuits section that precedes this Applications

Information section. The test circuit uses a 1kHz triangle

wave to repeatedly trip the comparator being tested. The

LT1720/LT1721outputisusedtotriggerswitchedcapaci-

tor sampling of the triangle wave, with a sampler for each

direction. Because the triangle wave is attenuated 1000:1

and fed to the LT1720/LT1721’s differential input, the

sampled voltages are therefore 1000 times the input trip

voltages. The hysteresis and offset are computed from the

trip points as shown.

V

CC

2.7V TO 6V

1MHz TO 10MHz

CRYSTAL (AT-CUT)

2k

220Ω

Crystal Oscillators

620Ω

GROUND

CASE

A simple crystal oscillator using one comparator of an

LT1720/LT1721 is shown on the first page of this data

sheet. The 2k-620Ω resistor pair set a bias point at the

comparator’s noninverting input. The 2k-1.8k-0.1µF path

sets the inverting input node at an appropriate DC average

level based on the output. The crystal’s path provides

resonant positive feedback and stable oscillation occurs.

Although the LT1720/LT1721 will give the correct logic

output when one input is outside the common mode

range, additional delays may occur when it is so operated,

opening the possibility of spurious operating modes.

Therefore, the DC bias voltages at the inputs are set near

the center of the LT1720/LT1721’s common mode range

and the 220Ω resistor attenuates the feedback to the

+

C1

OUTPUT

100k

1/2 LT1720

–

2k

+

–

A1

LT1636

0.1µF

1.8k

0.1µF

1k

100k

+

C2

OUTPUT

1/2 LT1720

–

1720 F07

Figure 7. Crystal Oscillator with Complementary

Outputs and 50% Duty Cycle

14

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1000

56% low duty cycle, sufﬁcient to allow 2ns between the

high pulses. Figure 10 shows the two outputs.

800

600

400

200

The optional A1 feedback network shown can be used to

force identical output duty cycles. The steady state duty

cycles of both outputs will be 44%. Note, though, that the

addition of this network only adjusts the percentage of

time each output is high to be the same, which can be

important in switching circuits requiring identical settling

times. Itcannotadjusttherelativephasesbetweenthetwo

outputs to be exactly 180^°apart, because the signal at the

input node driven by the crystal is not a pure sinusoid.

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

SUPPLY VOLTAGE (V)

1720/21 F08

Q0

2V/DIV

Figure 8. Timing Skew of Figure 7’s Circuit

applications. This circuit works well because of the two

matcheddelaysandrail-to-railstyleoutputsoftheLT1720.

Q1

2V/DIV

ThecircuitinFigure9showsacrystaloscillatorcircuitthat

generatestwononoverlappingclocksbymakingfulluseof

the two independent comparators of the LT1720.

C1 oscillates as before, but with a lower reference level,

C2’s output will toggle at different times. The resistors set

thedegreeofseparationbetweentheoutput’shighpulses.

With the values shown, each output has a 44% high and

20ns/DIV

Figure 10. Nonoverlapping Outputs of Figure 9's Circuit

V

CC

2.7V TO 6V

10MHz

CRYSTAL (AT-CUT)

2k

220Ω

620Ω

GROUND

CASE

+

C1

OUTPUT 0

1/2 LT1720

–

OPTIONAL—

SEE TEXT

100k

2k

+

A1

LT1636

0.1µF

1.3k

0.1µF

–

0.1µF

1k

2.2k

100k

+

C2

OUTPUT 1

1/2 LT1720

1720/21 F09

–

Figure 9. Crystal-Based Nonoverlapping 10MHz Clock Generator

15

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APPLICATIONS INFORMATION

Timing Skews

high speed instrumentation. The circuit in Figure 12 is a

delay detector which will output a pulse when signals X

and Y are out of sync (specifically, when X is high and Y is

low). Note that the addition of an identical circuit to detect

the opposite situation (X low and Y high) allows for full

skew detection.

For a number of reasons, the LT1720/LT1721’s superior

timing specifications make them an excellent choice for

applications requiring accurate differential timing skew.

The comparators in a single package are inherently well

matched, with just 300ps ∆t_PDtypical. Monolithic con-

struction keeps the delays well matched vs supply voltage

and temperature. Crosstalk between the comparators,

usually a disadvantage in monolithic duals and quads, has

minimal effect on the LT1720/LT1721 timing due to the

internal hysteresis, as described in the Speed Limits

section.

Comparators U1A and U1B clean up the incoming signals

and render the circuit less sensitive to input levels and

slew rates. The resistive divider network provides level

shifting for the downstream comparator’s common mode

input range, as well as offset to keep the output low except

during a decisive event. When the upstream comparator’s

outputs can overcome the resistively generated offset

(and hysteresis), comparator U1C performs a Boolean

“X*_Y” function and produces an output pulse (see Fig-

ure 13). The circuit will give full output response with

input delays down to 3ns and partial output response with

inputdelaysdownto1.8ns.CapacitorC1helpsensurethat

an imbalance of parasitic capacitances in the layout will

not cause common mode excursions to result in differen-

tial mode signal and false outputs.¹

The circuits of Figure 11 show basic building blocks for

differential timing skews. The 2.5k resistance interacts

with the 2pF typical input capacitance to create at least

±4ns delay, controlled by the potentiometer setting.

A differential and a single-ended version are shown. In the

differentialconﬁguration,theoutputedgescanbesmoothly

scrolled through ∆t = 0 with negligible interaction.

3ns Delay Detector

¹Make sure the input levels at X and Y are not too close to the 0.5V threshold set by the R8–R9

divider. If you are still getting false outputs, try increasing C1 to 10pF or more. You can also look

fortheproblemintheimpedancebalance(R5||R6=R7)attheinputsofU1C. Increasingtheoffset

by lowering R5 will help reject false outputs, but R7 should also be lowered to maintain impedance

balance. For ease of design and parasitic matching, R7 can be replaced by two parallel resistors

equal to R5 and R6.

It is often necessary to measure comparative timing of

pulseedgesinordertodeterminethetruesynchronicityof

clock and control signals, whether in digital circuitry or in

LT1720

C

IN

C

IN

+

–

+

INPUT

–

2.5k

C

IN

C

IN

0ns TO 4ns

SINGLE-ENDED

DELAY

DIFFERENTIAL ±4ns

RELATIVE SKEW

INPUT

2.5k

C

IN

C

IN

–

+

–

+

C

IN

C

IN

V

REF

1720/21 F11

Figure 11. Building Blocks for Timing Skew Generation with the LT1720

16

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DELAY DETECTOR

5V

R5

1.82k*

OPTIONAL LOGARITHMIC PULSE STRETCHER (SEE TEXT)

+

X

301Ω*

R6

301Ω*

U1A

5V

1/4 LT1721

51Ω*

CAPTURE

–

0.33µF

R1

–

1N5711

499Ω*

Z

U1C

R8*

4.53k

C1

5.6pF

301Ω*

+

1/4 LT1721

V

U1D

IN

C

R9

487Ω*

5V

0.1µF

L

+

1/4 LT1721

C2

540pF

**

–

5V

–

301Ω*

U1B

1/4 LT1721

475Ω*

Y

+

R7

261Ω*

51Ω*

R2

1k*

R3

1Ω*

–

V

OFF

1V

R4

DELAY

X

Y

Z

30Ω*

0V

1V

0V

1720/21 F12

* 1% METAL FILM RESISTOR

** 270pF ×2 FOR REDUCED LEAD INDUCTANCE

5V

0V

RESULT OF X AND NOT Y

Figure 12. 3ns Delay Detector with Logarithmic Pulse Stretcher

X

Y

Z

Figure 13. Output Pulse Due to Delay of Y Input Pulse

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Optional Logarithmic Pulse Stretcher

For simplicity, with t_P< τ₁, and neglecting the very slight

delay in turn-on due to offset and hysteresis, the equation

can be approximated by:

The fourth comparator of the quad LT1721 can be put to

work as a logarithmic pulse stretcher. This simple circuit

can help tremendously if you don’t have a fast enough

oscilloscope(orcontrolcircuit)toeasilycapture3nspulse

widths (or faster). When an input pulse occurs, C2 is

charged up with a 180ns capture²time constant. The

hysteresis and 10mV offset across R3 are overcome

within the first nanosecond³, switching the comparator

output high. When the input pulse subsides, C2 dis-

chargeswitha540nstimeconstant,keepingthecompara-

tor on until the decay overrides the 10mV offset across R3

minus hysteresis. Because of this exponential decay, the

output pulse width will be proportional to the logarithm of

theinputpulsewidth. Itisimportanttobypassthecircuit’s

V_CCwell to avoid coupling into the resistive divider. R4

keepsthequiescentinputvoltageinarangewhereforward

leakage of the diode due to the 0.4V V_OLof the driving

comparator is not a problem.

t_OUT= τ₂• ln [(V_CH• t_P/τ₁)/(V_OFF– V_H/2)]

(2)

For example, an 8ns input pulse gives a 1.67µs output

pulse. Doubling the input pulse to 16ns lengthens the

output pulse by 0.37µs. Doubling the input pulse again to

32ns adds another 0.37µs to the output pulse, and so on.

The rate of 0.37µs per octave falls out of the above

equation as:

∆t_OUT/octave = τ₂• ln(2)

(3)

There is ±0.01µs jitter⁵in the output pulse which gives an

uncertainty referred to the input pulse of less than 2%

(60ps resolution on a 3ns pulse with a 60MHz oscillo-

scope—not bad!). The beauty of this circuit is that it gives

resolution precisely where it’s hardest to get. The jitter is

due to a combination of the slow decay of the last few

millivolts on C2 and the 4nV/√Hz noise and 400MHz

bandwidthoftheLT1721inputstage.Increasingtheoffset

across R3 or decreasing τ₂will decrease this jitter at the

expense of dynamic range.

Neglectingsomeeffects⁴, theoutputpulseisrelatedtothe

input pulse as:

t_OUT= τ₂• ln {V_CH• [1 – exp (–t_P/τ₁)]/(V_OFF– V_H/2)}

– τ₁• ln [V_CH/(V_CH– V_OFF– V_H/2)]

The circuit topology itself is extremely fast, limited theo-

retically only by the speed of the diode, the capture time

constant τ₁and the pulse source impedance. Figure 14

shows results achieved with the implementation shown,

compared to a plot of equation (1). The low end is limited

by the delivery time of the upstream comparators. As the

input pulse width is increased, the log function is con-

strained by the asymptotic RC response but, rather than

becoming clamped, becomes time linear. Thus, for very

long input pulses the third term of equation (1) dominates

and the circuit becomes a 3µs pulse stretcher.

+ t_P

(1)

where

t_P= input pulse width

t_OUT= output pulse width

τ₁= R1 || R2 • C2

τ₂= R2 • C2

the capture time constant

the decay time constant

the voltage drop across R1

LT1721 hysteresis

V_OFF= 10mV

²So called because the very fast input pulse is “captured,” for later examination, as a charge on the

capacitor.

V_H= 3.5mV

³Assumingtheinputpulseslewrateatthediodeisinfinite.Thiseffectivedelayconstant,about0.4%

of τ₁or 0.8ns, is the second term of equation 1, below. Driven by the 2.5ns slew-limited LT1721,

this effective delay will be 2ns.

⁴V_Cis dependent on the LT1721 output voltage and nonlinear diode characteristics. Also, the

Thevenin equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above

ground.

⁵Output jitter increases with inputs pulse widths below ~3ns.

V_C= V_IN– V_FDIODE

the input pulse voltage after

the diode drop

V_CH= V_C• R2/(R1 + R2) the effective source voltage

for the charge

18

LT1720/LT1721

U

W U U

APPLICATIONS INFORMATION

14

easily measured 1.70µs output pulses. A 12 foot cable

length difference will result in ~18.4ns delay and 2.07µs

output pulses. The difference in the two output pulse

widths is the per-octave response of your circuit (see

equation (3)). Shorter cable length differences can be

used to get a plot of circuit performance down to 1.5ns (if

any), which can then later be used as a lookup reference

whenyouhavemovedfromquantifyingthecircuittousing

the circuit. (Note there is a slight aberration in perfor-

mance below 10ns. See Figure 14.) As a final check, feed

the circuit with identical cable lengths and check that it is

not producing any output pulses.

12

10

8

6

MEASURED

4

EQUATION 1

2

0

1

10

100

(ns)

1000

10000

t

PULSE

1720/21 F14

Figure 14. Log Pulse Stretcher Output Pulse vs Input Pulse

10ns Triple Overlap Generator

The circuit of Figure 16 utilizes an LT1721 to generate

three overlapping outputs whose pulse edges are sepa-

ratedby10nsasshown. ThetimeconstantissetbytheRC

network on the output of comparator A. Comparator B and

Dtripatfixedpercentagesoftheexponentialvoltagedecay

across the capacitor. The 4.22kΩ feed-forward to the C

comparator’s inverting input keeps the delay differences

the same in each direction despite the exponential nature

of the RC network’s voltage.

NANOSECOND

INPUT RANGE

MICROSECOND

OUTPUT RANGE

X

Y

1 FOOT CABLE

L

t

OUT

(SEE TEXT)

CIRCUIT OF

FIGURE 12

2V

0V

There is a 15ns delay to the first edge in both directions,

due to the 4.5ns delay of two LT1721 comparators, plus

6ns delay in the RC network. This starting delay is short-

ened somewhat if the pulse was shorter than 40ns be-

cause the RC network will not have fully settled; however,

the 10ns edge separations stay constant.

SPLITTER

n FOOT CABLE

1720/21 F15

Thevaluesshownutilizeonlythelowest75%ofthesupply

voltagespan, whichallowsittoworkdownto2.7Vsupply.

Thedelaydifferencesgrowacouplenanosecondsfrom5V

to 2.7V supply due to the fixed V_OL/V_OHdrops which grow

as a percentage at low supply voltage. To keep this effect

to a minimum, the 1kΩ pull-up on comparator A provides

equal loading in either state.

Figure 15. RG-58 Cable with Velocity of Propogation = 66%;

Delay at Y = (n – 1) • 1.54ns

You don’t need expensive equipment to confirm the actual

overall performance of this circuit. All you need is a

respectablewaveformgenerator(capableof>~100kHz), a

splitter, a variety of cable lengths and a 20MHz or 60MHz

oscilloscope. Split a single pulse source into different

cable lengths and then into the delay detector, feeding the

longer cable into the Y input (see Figure 15). A 6 foot cable

length difference will create a ~9.2ns delay (using 66%

propagation speed RG-58 cable), and should result in

Fast Waveform Sampler

Figure 17 uses a diode-bridge-type switch for clean, fast

waveform sampling. The diode bridge, because of its

inherent symmetry, provides lower AC errors than other

semiconductor-based switching technologies. This cir-

cuit features 20dB of gain, 10MHz full power bandwidth

19

LT1720/LT1721

U

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APPLICATIONS INFORMATION

V

CC

V

CC

OUTPUTS

+

U1B

1k

1/4 LT1721

V

CC

10ns

–

V

CC

INPUT

750Ω

909Ω

+

1.37k

215Ω

681Ω

U1A

+

1/4 LT1721

U1C

100pF

V

–

REF

1/4 LT1721

10ns

–

681Ω

4.22k

+

U1D

1/4 LT1721

–

453Ω

1720/21 F16

Figure 16. 10ns Triple Overlap Generator

5V

2.2k

INPUT

±100mV FULL SCALE

+

–

OUTPUT

±1V FULL SCALE

LT1227

1k

909Ω

= 1N5711

AC BALANCE

3pF

= CA3039 DIODE ARRAY

(SUBSTRATE TO –5V)

100Ω

5V

1.5k

3.6k

1.1k

0.1µF

1.1k

+

C

IN

1/2 LT1720

1.1k

–

MRF501

SKEW

COMP

2k

10pF

SAMPLE

COMMAND

DC BALANCE

2.5k

+

500Ω

680Ω

11

8

1/2 LT1720

2k

–

820Ω

6

9

C

IN

LM3045

13

10

51Ω

7

51Ω

1720/21 F17

–5V

Figure 17. Fast Waveform Sampler Using the LT1720 for Timing-Skew Compensation

20

LT1720/LT1721

U

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APPLICATIONS INFORMATION

and 100µV/°C baseline uncertainty. Switching delay is

less than 15ns and the minimum sampling window width

for full power response is 30ns.

is adjusted for minimal bridge ON vs OFF variation at the

output. The skew compensation and AC balance adjust-

ments are then optimized for minimum AC disturbance in

the output. Finally, unground the input and the circuit is

ready for use.

The input waveform is presented to the diode bridge

switch, the output of which feeds the LT1227 wideband

ampliﬁer.TheLT1720comparators,triggeredbythesample

command, generate phase-opposed outputs. These sig-

nals are level shifted by the transistors, providing comple-

mentary bipolar drive to switch the bridge. A skew

compensation trim ensures bridge-drive signal simulta-

neity within 1ns. The AC balance corrects for parasitic

capacitive bridge imbalances. A DC balance adjustment

trims bridge offset.

Voltage-Controlled Clock Skew Generator

It is sometimes necessary to generate pairs of identical

clock signals that are phase skewed in time. Further, it is

desirable to be able to set the amount of time skew via a

tuning voltage. Figure 18’s circuit does this by utilizing

theLT1720todigitizephaseinformationfromavaractor-

tuned time domain bridge. A 0V to 2V control signal

provides ≈±10ns of output skew. This circuit operates

from a 2.7V to 6V supply.

The trim sequence involves grounding the input via 50Ω

and applying a 100kHz sample command. The DC balance

CLOCK

INPUT

V

CC

2.7V TO 6V

+

C1

FIXED

OUTPUT

Q

1/2 LT1720

–

V

CC

2k

2.5k

2.5k*

10ns

TRIM

14k

2k*

“FIXED”

“SKEWED”

†

+

†

C2

SKEWED

OUTPUT

36pF

Q′

1/2 LT1720

12pF

–

MV-209

VARACTOR

DIODE

1M

0.1µF

0.005µF

47µF

INPUT

L1**

0V TO 2V ≈

±10ns

+

–

V

CC

A1

LT1077

+

SKEW

1.1M

100k

2.2µF

V

SW

IN

= 1N4148

= 74HC04

6.2M*

LT1317 FB

GND

V

C

200pF

* 1% FILM RESISTOR

** SUMIDA CD43-100

1.82M*

†

POLYSTYRENE, 5%

1720/21 F18

Figure 18. Voltage-Controlled Clock Skew

21

LT1720/LT1721

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APPLICATIONS INFORMATION

Coincidence Detector

AND gate could instead be used, but would add consider-

ably more delay than the 300ps contributed by this dis-

crete stage.

High speed comparators are especially suited for interfac-

ing pulse-output transducers, such as particle detectors,

to logic circuitry. The matched delays of a monolithic dual

are well suited for those cases where the coincidence of

two pulses needs to be detected. The circuit of Figure 19

isacoincidencedetectorthatusesanLT1720anddiscrete

components as a fast AND gate.

This circuit can detect coincident pulses as narrow as 3ns.

For narrower pulses, the output will degrade gracefully,

responding, but with narrow pulses that don’t rise all the

way to “high” before starting to fall. The decision delay is

4.5ns with input signals 50mV or more above the refer-

encelevel.ThiscircuitcreatesaTTLcompatibleoutputbut

it can typically drive CMOS as well.

Thereferencelevelissetto1V,anarbitrarythreshold.Only

when both input signals exceed this will a coincidence be

detected. The Schottky diodes from the comparator out-

puts to the base of the MRF-501 form the AND gate, while

the other two Schottkys provide for fast turn-off. A logic

For a more detailed description of the operation of this

circuit, see Application Note 75, pages 10 and 11.

5V

GROUND

CASE LEAD

300Ω

+

MRF501

OUTPUT

1/2 LT1720

51Ω

5V

3.9k

–

1k

0.1µF

–

1/2 LT1720

+

300Ω

4× 1N5711

51Ω

1720/21 F19

300ps AND GATE

COINCIDENCE COMPARATORS

Figure 19. A 3ns Coincidence Detector

22

LT1720/LT1721

W

SI PLIFIED SCHE ATIC

23

LT1720/LT1721

U

PACKAGE DESCRIPTION ^{Dimensions in inches (millimeters) unless otherwise noted.}

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

7

5

8

6

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

1

3

4

2

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

SO8 1298

24

LT1720/LT1721

U

PACKAGE DESCRIPTION ^{Dimensions in inches (millimeters) unless otherwise noted.}

MS8 Package

8-Lead Plastic MSOP

(LTC DWG # 05-08-1660)

0.118 ± 0.004*

(3.00 ± 0.102)

8

7

6

5

0.118 ± 0.004**

(3.00 ± 0.102)

0.193 ± 0.006

(4.90 ± 0.15)

1

2

3

4

0.040 ± 0.006

(1.02 ± 0.15)

0.034 ± 0.004

(0.86 ± 0.102)

0.007

(0.18)

0° – 6° TYP

SEATING

PLANE

0.012

(0.30)

REF

0.021 ± 0.006

(0.53 ± 0.015)

0.006 ± 0.004

(0.15 ± 0.102)

0.0256

(0.65)

BSC

MSOP (MS8) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

25

LT1720/LT1721

U

PACKAGE DESCRIPTION ^{Dimensions in inches (millimeters) unless otherwise noted.}

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.386 – 0.394*

(9.804 – 10.008)

16

15

14

13

12

11

10

9

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

5

7

8

1

2

3

4

6

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0° – 8° TYP

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

0.016 – 0.050

(0.406 – 1.270)

S16 1098

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

26

LT1720/LT1721

U

PACKAGE DESCRIPTION ^{Dimensions in inches (millimeters) unless otherwise noted.}

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.189 – 0.196*

(4.801 – 4.978)

0.009

(0.229)

REF

16 15 14 13 12 11 10 9

0.229 – 0.244

(5.817 – 6.198)

0.150 – 0.157**

(3.810 – 3.988)

1

2

3

4

5

6

7

8

0.015 ± 0.004

(0.38 ± 0.10)

× 45°

0.053 – 0.068

(1.351 – 1.727)

0.004 – 0.0098

(0.102 – 0.249)

0.007 – 0.0098

(0.178 – 0.249)

0° – 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.0250

(0.635)

BSC

0.008 – 0.012

(0.203 – 0.305)

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

GN16 (SSOP) 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LT1720/LT1721

U

TYPICAL APPLICATION

Pulse Stretcher

capacitor C now begins charging through R and, at the

end of 100ns, C2 resets low. The output of C1 also goes

low, latching both outputs low. A new pulse at the input

of C1 can now restart the process. Timing capacitor C can

be increased without limit for longer output pulses.

For detecting short pulses from a single sensor, a pulse

stretcher is often required. The circuit of Figure 20 acts as

a one-shot, stretching the width of an incoming pulse to a

consistent 100ns. Unlike a logic one-shot, this LT1720-

based circuit requires only 100pV-s of stimulus to trigger.

This circuit has an ultimate sensitivity of better than 14mV

with 5ns to 10ns input pulses. It can even detect an

avalanche generated test pulse of just 1ns duration with

sensitivity better than 100mV.⁶It can detect short events

better than the coincidence detector of Figure 14 because

the one-shot is conﬁgured to catch just 100mV of upward

movement from C1’s V_OL, whereas the coincidence

detector’s 3ns speciﬁcation is based on a full, legitimate

logic high, without the help of a regenerative one-shot.

The circuit works as follows: Comparator C1 functions as

a threshold detector, whereas comparator C2 is conﬁg-

uredasaone-shot. Theﬁrstcomparatorisprebiasedwith

a threshold of 8mV to overcome comparator and system

offsets and establish a low output in the absence of an

input signal. An input pulse sends the output of C1 high,

which in turn latches C2’s output high. The output of C2

is fed back to the input of the ﬁrst comparator, causing

regeneration and latching both outputs high. Timing

⁶See Linear Technology Application Note 47, Appendix B. This circuit can detect the output of the

pulse generator described after 40dB attenuation.

5V

0.01µF

15k

OUTPUT

–

C1

PULSE SOURCE

1/2 LT1720

50Ω

100ns

+

51Ω

24Ω

R

1k

6.8k

1N5711

C

100pF

–

C2

1/2 LT1720

+

2k

1720/21 F20

2k

Figure 20. A 1ns Pulse Stretcher

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1016

UltraFast Precision Comparator

Industry Standard 10ns Comparator

Single Supply Version of LT1016

6mA Single Supply Comparator

450µA Single Supply Comparator

Single Comparator Similar to the LT1720/LT1721

LT1116

12ns Single Supply Ground-Sensing Comparator

7ns, UltraFast, Single Supply Comparator

60ns, Low Power, Single Supply Comparator

4.5ns Single Supply 3V/5V Comparator

LT1394

LT1671

LT1719

17201f LT/TP 1099 4K • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

LINEAR TECHNOLOGY CORPORATION 1998

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com

型号:	LT1720CMS8
是否Rohs认证：	不符合
生命周期：	Active
包装说明：	PLASTIC, MSOP-8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.16
放大器类型：	COMPARATOR
最大平均偏置电流 (IIB)：	6 µA
最大输入失调电压：	4500 µV
JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e0
长度：	3 mm
湿度敏感等级：	1
功能数量：	2
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
输出类型：	PUSH-PULL
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	235
认证状态：	Not Qualified
标称响应时间：	7 ns
座面最大高度：	1.1 mm
子类别：	Comparator
供电电压上限：	7 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	20
宽度：	3 mm
Base Number Matches：	1

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