LTC2365HS6#TRMPBF中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

LTC2365/LTC2366

1Msps/3Msps, 12-Bit Serial

Sampling ADCs in TSOT

FEATURES

DESCRIPTION

The LTC^®2365/LTC2366 are 1Msps/3Msps, 12-bit, sam-

pling A/D converters that draw only 2mA and 2.6mA, re-

spectively,fromasingle3Vsupply.Thesehighperformance

devices include a high dynamic range sample-and-hold

and a high speed serial interface. The full scale input is

n

12-Bit Resolution

n

1Msps/3Msps Sampling Rates

n

Low Noise: 73dB SNR

Low Power Dissipation: 6mW

Single Supply 2.35V to 3.6V Operation

No Data Latency

n

0V to V or V . Outstanding AC performance includes

DD

REF

n

Sleep Mode with 0.1μA Typical Supply Current

72dB SINAD and –80dB THD at sample rates of 3Msps.

The serial interface provides ﬂexible power management

and allows maximum power efﬁciency at low throughput

rates. These devices are available in tiny 6- and 8-lead

TSOT-23 packages.

n

Dedicated External Reference (TSOT23-8)

n

1V to 3.6V Digital Output Supply (TSOT23-8)

SPI/MICROWIRE^™Compatible Serial I/O

n

Guaranteed Operation from –40°C to 125°C

6- and 8-Lead TSOT-23 Packages

n

The serial interface, tiny TSOT-23 package and extremely

highsamplerate-to-powerratiomaketheLTC2365/LTC2366

ideal for compact, low power, high speed systems.

APPLICATIONS

n

Communication Systems

The high impedance single-ended analog input and the

ability to operate with reduced spans (down to 1.4V full

scale)allowdirectconnectiontosensorsandtransducersin

many applications, eliminating the need for gain stages.

n

Data Acquisition Systems

n

Handheld Terminal Interface

n

Medical Imaging

n

Uninterrupted Power Supplies

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S.

n

Battery Operated Systems

n

Automotive

TYPICAL APPLICATION

12-Bit TSOT23-6/-8 ADC Family

DATA OUTPUT RATE

3Msps

1Msps

500ksps

250ksps

100ksps

Part Number

LTC2366 LTC2365 LTC2362 LTC2361 LTC2360

1MHz Sine Wave 8192 FFT Plot

0

–20

Single 3V Supply, 3Msps, 12-Bit Sampling ADC

V

= 3V

DD

f

= 3Msps

SMPL

IN

= 994kHz

3V

SINAD = 72dB

THD = –80.3dB

–40

10μF

LTC2366

V

CS

SDO

SCK

DD

–60

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP

OR SHIFT REGISTERS

REF

–80

GND

ANALOG INPUT

0V TO 3V

DIGITAL OUTPUT SUPPLY

1V TO 3.6V

–100

–120

–140

A

OV

DD

IN

4.7μF

23656 TA01

1000

INPUT FREQUENCY (kHz)

1500

0

250

500

750

1250

23656 TA01b

23656f

1

LTC2365/LTC2366

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Operating Temperature Range

Supply Voltage (V , OV ).....................................4.0V

LTC2365C/LTC2366C ............................... 0°C to 70°C

LTC2365I/LTC2366I.............................. –40°C to 85°C

LTC2365H/LTC2366H (Note 13)......... –40°C to 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

DD

V

REF

and Analog Input Voltage

(Note 3).........................................–0.3V to (V + 0.3V)

DD

Digital Input Voltage......................–0.3V to (V + 0.3V)

DD

Digital Output Voltage ...................–0.3V to (V + 0.3V)

DD

Power Dissipation...............................................100mW

PIN CONFIGURATION

TOP VIEW

V

1

2

8 CS

7 SCK

6 SDO

DD

V

1

6 CS

DD

V

REF

GND 2

5 SDO

4 SCK

GND 3

A

3

IN

4

5 OV

DD

IN

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

= 150°C, θ = 250°C/W

S6 PACKAGE

6-LEAD PLASTIC TSOT-23

T = 150°C, θ = 250°C/W

JMAX

T

JMAX

JA

ORDER INFORMATION

Lead Free Finish

TAPE AND REEL (MINI)

LTC2366CTS8#TRMPBF

LTC2366ITS8#TRMPBF

LTC2366HTS8#TRMPBF

LTC2366CS6#TRMPBF

LTC2366IS6#TRMPBF

LTC2366HS6#TRMPBF

LTC2365CTS8#TRMPBF

LTC2365ITS8#TRMPBF

LTC2365HTS8#TRMPBF

LTC2365CS6#TRMPBF

LTC2365IS6#TRMPBF

LTC2365HS6#TRMPBF

TAPE AND REEL

PART MARKING*

LTCYZ

PACKAGE DESCRIPTION

8-lead Plastic TSOT-23

6-lead Plastic TSOT-23

8-lead Plastic TSOT-23

6-lead Plastic TSOT-23

TEMPERATURE RANGE

0°C to 70°C

LTC2366CTS8#TRPBF

LTC2366ITS8#TRPBF

LTC2366HTS8#TRPBF

LTC2366CS6#TRPBF

LTC2366IS6#TRPBF

LTC2366HS6#TRPBF

LTC2365CTS8#TRPBF

LTC2365ITS8#TRPBF

LTC2365HTS8#TRPBF

LTC2365CS6#TRPBF

LTC2365IS6#TRPBF

LTC2365HS6#TRPBF

LTCYZ

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LTCYZ

LTCXK

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LTCXK

LTDCB

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LTDCB

LTDCC

–40°C to 85°C

–40°C to 125°C

LTDCC

TRM = 500 pieces. *Temperature grades are identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

23656f

2

LTC2365/LTC2366

CONVERTER CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

LTC2365

TYP

LTC2366

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Transition Noise

12

(Note 5, 6)

(Note 6)

(Note 7)

(Note 6)

0.25

0.34

2

1

0.25

0.34

2

1

LSB

RMS

l

Offset Error

3.5

2

3.5

2

LSB

Gain Error

1

LSB

l

Total Unadjusted Error

S6 Package (Note 6)

TS8 Package (Note 6)

2

3

3.5

4.5

2

3

3.5

4.5

LSB

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

ANALOG INPUTS

speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

+ 0.05

DD

UNITS

l

V

Analog Input Voltage

S6 Package

TS8 Package

–0.05

V

IN

+ 0.05

REF

l

I

Analog Input Leakage Current

Analog Input Capacitance

CS = High

1

μA

IN

C

Between Conversions

During Conversions

20

4

pF

IN

l

V

Reference Input Voltage

TS8 Package

1.4

V

+ 0.05

1

V

μA

pF

ns

REF

DD

I

Reference Input Leakage Current

Reference Input Capacitance

C

REF

4

1

t

Sample-and-Hold Aperture Delay Time

Sample-and-Hold Aperture Delay Time Jitter

AP

JITTER

0.3

The l denotes the speciﬁcations which apply over the full operating temperature range,

DYNAMIC ACCURACY

otherwise speciﬁcations are at T_A= 25°C. (Note 4)

LTC2365

LTC2366

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX MIN TYP MAX UNITS

l

SINAD

SNR

Signal-to-(Noise + Distortion) Ratio

f

= 1MHz

68

70

72

68

69

71

dB

IN

Signal-to-Noise Ratio

73

72

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

Intermodulation Distortion

–86 –72

87

–80 –72

82

SFDR

IMD

f

IN1

f

IN1

= 0.97MHz, f = 1MHz for LTC2366

= 97kHz, f = 100kHz for LTC2365

–71.5

dB

IN2

–76

Full Power Bandwidth

Full Linear Bandwidth

At 3dB

30

5

50

8

MHz

At 0.1dB

SINAD ≥ 68dB

2

2.5

MHz

23656f

3

LTC2365/LTC2366

The l denotes the speciﬁcations which apply over the full

DIGITAL INPUTS AND DIGITAL OUTPUTS

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

2.7V < V ≤ 3.6V

MIN

TYP

MAX

UNITS

l

V

High Level Input Voltage

2

1.7

V

IH

IL

DD

2.35V ≤ V ≤ 2.7V

DD

l

V

Low Level Input Voltage

2.7V < V ≤ 3.6V

0.8

0.7

V

DD

2.35V ≤ V ≤ 2.7V

DD

l

I

High Level Input Current

Low Level Input Current

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage

V

= V

DD

2.5

μA

pF

V

IH

IL

IN

= 0V

–2.5

C

V

2

IN

l

V

= 2.35V to 3.6V, I

= 200μA

V

DD

–0.2

OH

OL

DD

SOURCE

= 200μA

0.2

3

V

DD

SINK

I

CS = V

μA

pF

mA

OZ

DD

C

Hi-Z Output Capacitance

Output Source Current

Output Sink Current

4

OZ

I

V

= 0V

–10

10

SOURCE

SINK

OUT

I

= V

DD

POWER REQUIREMENT

SYMBOL PARAMETER

CONDITIONS

MIN

2.35

1

TYP

MAX

3.6

UNITS

l

V

Supply Voltage

3.0

V

DD

O

Digital Output Supply Voltage

3.6

VDD

I

Supply Current, Static Mode

Operational Mode, LTC2366

Operational Mode, LTC2365

Sleep Mode

CS = 0V, SCK = 0V or V

SMPL

–40°C to +85°C

+85°C to +125°C

1

mA

μA

DD

l

f

= 3Msps

= 1Msps

2.6

2

4

3.5

2

0.1

Sleep Mode

5

μA

P

Power Dissipation, Static Mode

Operational Mode, LTC2366

Operational Mode, LTC2365

Sleep Mode

CS = 0V, SCK = 0V or V

3.6

14.4

12.6

7.2

mW

μW

D

l

f

= 3Msps

= 1Msps

7.8

6

0.3

SMPL

–40°C to +85°C

+85°C to +125°C

Sleep Mode

18

23656f

4

LTC2365/LTC2366

The l denotes the speciﬁcations which apply over the full operating temperature

TIMING CHARACTERISTICS

range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

LTC2365

TYP

LTC2366

TYP

SYMBOL

PARAMETER

CONDITIONS

(Notes 8, 9)

MIN

1

MAX MIN

MAX UNITS

l

f

t

Maximum Sampling Frequency

Shift Clock Frequency

Shift Clock Period

3

MHz

SMPL(MAX)

(Notes 8, 9, 10)

0.5

62.5

16

0.5

48

MHz

ns

SCK

2000 20.8

2000

333

SCK

Minimum Throughput Time, t

Acquisition Time

+ t

CONV

1000

56

THROUGHPUT

ACQ

181.5

ACQ

Conversion Time

818.5

277

4

CONV

SDO Hi-Z State to CS ↓

(Notes 8, 9)

4

6

QUIET

Minimum Positive or Negative CS Pulse Width (Notes 8)

4

1

SCK↓ Setup Time After CS ↓

SDO Enabled Time After CS ↓

SDO Data Valid Access Time After SCK↓

SCK Low Time

(Notes 8)

2000

4

6

2000

4

2

(Notes 9, 11, 12)

(Notes 8, 9, 11)

3

15

4

40%

5

40%

5

t

5

SCK

SCK High Time

6

SCK

SDO Data Valid Hold Time After SCK↓

SDO Into Hi-Z State Time After SCK↓

SDO Into Hi-Z State Time After CS ↑

Power-up Time from Sleep Mode

(Notes 8, 9, 11)

(Notes 9, 12)

ns

7

5

30

4.2

5

14

4.2

333

ns

8

(Notes 9, 12)

9

See Sleep Mode section

1000

POWER-UP

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: Linearity, offset and gain speciﬁcations apply for a single-ended

input with respect to GND.

Note 7: Typical RMS noise at code transitions.

A

IN

Note 8: Guaranteed by characterization. All input signals are speciﬁed with

Note 2: All voltage values are with respect to GND.

t = t = 2ns (10% to 90% of V ) and timed from a voltage level of 1.6V.

r

f

DD

Note 3: When this pin, A , is taken below GND or above V , it will be

IN

DD

Note 9: All timing speciﬁcations given are with a 10pF capacitance load.

With a capacitance load greater than this value, a digital buffer or latch

must be used.

clamped by internal diodes. These products can handle input currents

greater than 100mA below GND or above V without latchup.

DD

Note 4: V = OV = V = 2.35V to 3.6V, f

SCK(MAX)

= f

and f

=

DD

REF

SMPL

SMPL(MAX)

SCK

Note 10: Minimum f

at which speciﬁcations are guaranteed.

SCK

f

unless otherwise speciﬁed.

Note 11: The time required for the output to cross the V or V voltage.

IH

IL

Note 5: Integral linearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve. The

deviation is measured from the center of the quantization band.

Note 12: Guaranteed by design, not subject to test.

Note 13: High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C.

23656f

5

LTC2365/LTC2366

T_A= 25°C, V_DD= OV_DD= V_REF(LTC2365, Note 4)

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

Integral and Differential

Nonlinearity vs Supply Voltage

1.0

0.8

1.0

0.8

V

= 3V

V

= 3V

DD

0.8

0.6

MAX INL

0.4

0.2

MAX DNL

0

MIN DNL

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

MIN INL

0

1024

2048

3072

4096

0

1024

2048

3072

4096

2.1

2.4

2.7

3.0

3.3

3.6

OUTPUT CODE

SUPPLY VOLTAGE (V)

23656 G01

23656 G02

23656 G03

Histogram for 16384 Conversions

SNR vs Input Frequency

SINAD vs Input Frequency

10000

8000

6000

4000

73.5

73.3

73.1

72.9

72.7

72.5

73.2

73.0

V

DD

= 3V

V

= 3.6V

DD

V

= 3.6V

DD

72.8

72.6

V

= 3V

DD

V

= 3V

DD

V

= 2.35V

DD

72.4

72.2

72.0

V

= 2.35V

DD

2000

0

2045

2047 2048 2049 2050

CODE

2046

100

1000

100

1000

INPUT FREQUENCY (kHz)

23656 G04

23656 G05

23656 G06

THD vs Input Resistance

461kHz Sine Wave 8192 FFT Plot

THD vs Input Frequency

–81

–82

–83

–78

–79

–80

–81

–82

–83

0

R

SMPL

= 10Ω

IN

V

= 3V

V

= 3V

DD

f

= 1Msps

f

= 1Msps

f

= 1Msps

SMPL

IN

–20

= 1MHz

f

= 461kHz

IN

SINAD = 72.8dB

THD = –86.1dB

–40

–60

–84

–85

–86

–87

–88

V

= 3V

DD

–80

V

= 2.35V

DD

–100

–120

–140

V

= 3.6V

DD

100

1000

0

25

50

75

100

200

300

500

0

400

INPUT FREQUENCY (kHz)

INPUT RESISTANCE (Ω)

INPUT FREQUENCY (kHz)

23656 G07

23656 G08

23656 G09

23656f

6

LTC2365/LTC2366

T_A= 25°C, V_DD= OV_DD= V_REF(LTC2366, Note 4)

TYPICAL PERFORMANCE CHARACTERISTICS

Differential Nonlinearity

vs Output Code

Integral and Differential

Nonlinearity vs Supply Voltage

1.0

Integral Nonlinearity

vs Output Code

1.0

0.8

1.0

0.8

V

= 3V

V

= 3V

DD

0.8

0.6

MAX INL

0.6

0.4

MAX DNL

0.2

0

MIN INL

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

MIN DNL

0

1024

2048

3072

4096

0

1024

2048

3072

4096

2.1

2.4

2.7

3.0

3.3

3.6

OUTPUT CODE

SUPPLY VOLTAGE (V)

23656 G10

23656 G11

23656 G12

Histogram for 16384 Conversions

SNR vs Input Frequency

SINAD vs Input Frequency

73.0

72.5

10000

8000

6000

4000

73.2

73.0

72.8

72.6

72.4

72.2

V

= 3V

DD

V

= 3.6V

DD

V

= 3.6V

DD

V

= 2.35V

DD

72.0

71.5

V

= 3V

DD

V

= 3V

DD

71.0

70.5

70.0

V

= 2.35V

DD

2000

0

100

1000 1500

2045

2047 2048 2049 2050

CODE

2046

100

1000 1500

INPUT FREQUENCY (kHz)

23656 G15

23656 G13

23656 G14

THD vs Input Resistance

1MHz Sine Wave 8192 FFT Plot

THD vs Input Frequency

0

–20

–72

–74

-76

–64

–66

–68

R

f

= 10Ω

= 3Msps

V

f

= 3V

SMPL

f = 994kHz

IN

V

f

= 3V

DD

= 3Msps

SMPL

= 3Msps

SMPL

IN

f

= 1.5MHz

SINAD = 72dB

THD = –80.3dB

–40

–78

–80

–82

–84

–86

–88

–60

–70

–72

–74

–76

–78

V

= 3.6V

–80

DD

–100

–120

–140

V

= 3V

DD

V

= 2.35V

DD

1000

INPUT FREQUENCY (kHz)

1500

0

250

500

750

1250

100

1000 1500

25

50

100

0

75

INPUT FREQUENCY (kHz)

INPUT RESISTANCE (Ω)

23656 G18

23656 G16

23656 G17

23656f

7

LTC2365/LTC2366

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= OV_DD= V_REF

(LTC2365/LTC2366, Note 4)

Integral and Differential

Nonlinearity vs Reference

Voltage (TS8 Package)

Reference Current vs SCK

Frequency (TS8 Package)

Supply Current vs SCK Frequency

3.0

2.5

1.0

0.8

250

200

150

16 SCKS PER CONVERSION

LTC2365, V = 3.6V

DD

V

= 3.6V

0.6

DD

MAX DNL

MAX INL

0.4

2.0

1.5

0.2

MIN DNL

V

= 3V

0

DD

V

= 3V

DD

–0.2

–0.4

–0.6

–0.8

–1.0

100

50

0

V

= 2.35V

DD

V

= 3.6V

DD

1.0

0.5

0

MIN INL

V

= 2.35V

DD

0

10

20

30

40

50

0.6

1.2

1.8

2.4

3.0

3.6

0

5

10 15 20 25 30 35 40 45 50

SCK FREQUENCY (MHz)

23656 G20

SCK FREQUENCY (MHz)

REFERENCE VOLTAGE (V)

23656 G19

23656 G21

Integral and Differential

Nonlinearity vs Reference

Voltage (TS8 Package)

Input Power Bandwidth

2

0

1.0

0.8

V

= 3V

LTC2366, V = 3.6V

DD

0.6

LTC2366

0.4

–2

–4

MAX DNL

MAX INL

0.2

0

LTC2365

MIN DNL

–0.2

–0.4

–0.6

–0.8

–1.0

–6

–8

MIN INL

–10

1

10

INPUT FREQUENCY (MHz)

100

0.6

1.2

1.8

2.4

3.0

3.6

REFERENCE VOLTAGE (V)

23656 G23

23656 G22

23656f

8

LTC2365/LTC2366

PIN FUNCTIONS

LTC2365/LTC2366 (S6 Package)

LTC2365/LTC2366 (TS8 Package)

V (Pin 1): Positive Supply. The V range is 2.35V to

DD

3.6V. Bypass to GND and to a solid ground plane with a

10μF ceramic capacitor (or 10μF tantalum in parallel with

0.1μF ceramic).

V

(Pin 1): Positive Supply. The V range is 2.35V to

DD

3.6V. V also deﬁnes the input span of the ADC, 0V to

DD

V . Bypass to GND and to a solid ground plane with a

DD

10μF ceramic capacitor (or 10μF tantalum in parallel with

0.1μF ceramic).

V

(Pin 2): Reference Input. V

deﬁnes the input

REF

and the V

GND (Pin 2): Ground. The GND pin must be tied directly

to a solid ground plane.

span of the ADC, 0V to V

range is 1.4V

REF

to V . Bypass to GND and to a solid ground plane with

DD

a 4.7μF ceramic capacitor (or 4.7μF tantalum in parallel

A (Pin 3): Analog Input. A is a single-ended input with

IN

with 0.1μF ceramic).

respect to GND with a range from 0V to V .

DD

GND (Pin 3): Ground. The GND pin must be tied directly

to a solid ground plane.

SCK (Pin 4): Shift Clock Input. The SCK serial clock ad-

vances the conversion process. SDO data transitions on

the falling edge of SCK.

A (Pin 4): Analog Input. A is a single-ended input with

IN

respect to GND with a range from 0V to V

.

REF

SDO (Pin 5): Three-state Serial Data Output. The A/D

conversion result is shifted out on SDO as a serial data

stream with MSB ﬁrst. The data stream consists of two

leading zeros followed by 12 bits of conversion data and

two trailing zeros.

OV (Pin 5): Output Driver Supply for SDO. The OV

DD

range is 1V to 3.6V. Bypass to GND and to a solid ground

plane with a 4.7μF ceramic capacitor (or 4.7μF tantalum

in parallel with 0.1μF ceramic).

CS (Pin 6): Chip Select Input. This active low signal starts

a conversion on the falling edge and frames the serial

data transfer.

SDO (Pin 6): Three-state Serial Data Output. The A/D

conversion result is shifted out on SDO as a serial data

stream with MSB ﬁrst. The data stream consists of two

leading zeros followed by 12 bits of conversion data and

two trailing zeros.

SCK (Pin 7): Shift Clock Input. The SCK serial clock ad-

vances the conversion process. SDO data transitions on

the falling edge of SCK.

CS (Pin 8): Chip Select Input. This active low signal starts

a conversion on the falling edge and frames the serial

data transfer.

23656f

9

LTC2365/LTC2366

BLOCK DIAGRAM

10μF

4.7μF

+

V

OV

DD

1

5

A

IN

ANALOG

THREE-

STATE

4

+

–

INPUT RANGE

OV TO V

REF

12-BIT ADC

SDO

S & H

6

SERIAL

OUTPUT

PORT

V

REF

2

3

7

8

SCK

+

TIMING

LOGIC

4.7μF

GND

CS

TS8 PACKAGE

23656 BD

TIMING DIAGRAMS

t

8

SCK

1.6V

Hi-Z

SDO

23656 TD01

Figure 1. SDO Into Hi-Z State After SCK Falling Edge

t

7

SCK

SDO

1.6V

V

IH

V

IL

23656 TD02

Figure 2. SDO Data Valid Hold Time After SCK Falling Edge

t

4

SCK

SDO

1.6V

V

OH

OL

23656 TD03

Figure 3. SDO Data Valid Access Time After SCK Falling Edge

23656f

10

LTC2365/LTC2366

APPLICATIONS INFORMATION

DC PERFORMANCE

DYNAMIC PERFORMANCE

TheLTC2365/LTC2366haveexcellenthighspeedsampling

capability. Fast fourier transform (FFT) test techniques are

used to test the ADC’s frequency response, distortion and

noise at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined for

frequenciesoutsidethefundamental.Figures5and6show

typical LTC2365 and LTC2366 FFT plots respectively.

The noise of an ADC can be evaluated in two ways: signal-

to-noiseratio(SNR)inthefrequencydomainandhistogram

in the time domain. The LTC2365/LTC2366 excel in both.

Figures 5 and 6 demonstrate that the LTC2365/LTC2366

have an SNR of over 72dB. The noise in the time domain

histogram is the transition noise associated with a 12-bit

resolutionADCwhichcanbemeasuredwithaﬁxedDCsignal

appliedtotheinputoftheADC. Theresultingoutputcodes

are collected over a large number of conversions. The

shape of the distribution of codes will give an indication

of the magnitude of the transition noise. In Figure 4, the

distribution of output codes is shown for a DC input that

has been digitized 16384 times. The distribution is Gaus-

sian and the RMS code transition is about 0.34LSB. This

corresponds to a noise level of 72.7dB relative to a full

scale of 3V.

0

V

= 3V

DD

f

= 1Msps

SMPL

IN

SINAD = 72.8dB

THD = –86.1dB

–20

= 461kHz

–40

–60

–80

–100

–120

–140

100

200

300

500

0

400

INPUT FREQUENCY (kHz)

23656 F05

Figure 5. LTC2365 FFT Plot

0

–20

10000

V

= 3V

V

= 3V

DD

f

= 3Msps

SMPL

IN

SINAD = 72dB

THD = –80.3dB

= 994kHz

8000

6000

4000

–40

–60

–80

–100

–120

–140

2000

0

1000

INPUT FREQUENCY (kHz)

1500

0

250

500

750

1250

2045

2047 2048 2049 2050

CODE

2046

23656 F06

23656 F04

Figure 4. Histogram for 16384 Conversions

Figure 6. LTC2366 FFT Plot

23656f

11

LTC2365/LTC2366

APPLICATIONS INFORMATION

Signal-to-Noise plus Distortion Ratio

sampling rate of 3MHz, the LTC2366 maintains ENOB

above 11 bits up to the Nyquist input frequency of 1.5MHz

(refer to Figure 7).

The signal-to-noise plus distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 6 shows a typical FFT with a 3MHz sam-

pling rate and a 1MHz input. The dynamic performance

is excellent for input frequencies up to and beyond the

Nyquist frequency of 1.5MHz.

Total Harmonic Distortion

Thetotalharmonicdistortion(THD)istheratiooftheRMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

2

V₂+ V₃+ V₄+...V_n

Effective Number of Bits

THD= 20log

V₁

The effective number of bits (ENOB) is a measurement

of the resolution of an ADC and is directly related to

SINAD by the equation:

where V is the RMS amplitude of the fundamental

frequency and V through V are the amplitudes of the

second through nth harmonics. THD versus Input Fre-

quency is shown in Figure 8. The LTC2366 has excellent

distortion performance up to the Nyquist frequency and

beyond.

1

2

n

ENOB = (SINAD – 1.76)/6.02

where ENOB is the effective number of bits of resolu-

tion and SINAD is expressed in dB. At the maximum

73.0

11.83

11.67

11.50

11.34

–72

R

= 10Ω

IN

V

= 3.6V

DD

–74

–76

–78

–80

–82

–84

–86

–88

72.5

V

= 2.35V

DD

72.0

71.5

V

= 3V

DD

V

= 3.6V

DD

71.0

70.5

70.0

V

= 3V

DD

V

= 2.35V

DD

100

1000 1500

100

1000 1500

INPUT FREQUENCY (kHz)

23656 F07

23656 F08

Figure 7. LTC2366 ENOB and SINAD vs Input Frequency

Figure 8. LTC2366 Distortion vs Input Frequency

23656f

12

LTC2365/LTC2366

APPLICATIONS INFORMATION

Intermodulation Distortion

Peak Harmonic or Spurious Noise

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermoduation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

Thepeakharmonicorspuriousnoiseisthelargestspectral

component excluding the input signal and DC. This value

is expressed in decibels relative to the RMS value of a

full-scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which

the amplitude of reconstructed fundamental is reduced by

3dB for full-scale input signal.

If two pure sine waves of frequencies f and f are applied

a

b

totheADCinput,nonlinearitiesintheADCtransferfunction

can create distortion products at the sum and difference

frequencies of mf nf , where m and n = 0, 1, 2, 3, etc.

a

b

The full-linear bandwidth is the input frequency at which

the SINAD has dropped to 68dB (11 effective bits). The

LTC2365/LTC2366 have been designed to optimize input

bandwidth, allowing the ADC to undersample input sig-

nals with frequencies above the converter’s Nyquist Fre-

quency. Thenoiseﬂoorstaysverylowathighfrequencies;

SINAD becomes dominated by distortion at frequencies

far beyond Nyquist.

For example, the 2nd order IMD terms include (f f ).

a

b

If the two input sine waves are equal in magnitude, the

value (in decibels) of the 2nd order IMD products can be

expressed by the following formula:

Amplitude at (f_a± f_b)

IMD(f_a± f_b)= 20log

Amplitude at f_a

The LTC2365/LTC2366 have good IMD as shown in Figure

9a and Figure 9b respectively.

0

V

= 3V

V

= 3V

DD

f

= 1Msps

f

= 3Msps

SMPL

b

SMPL

a

b

–20

= 396kHz

= 424kHz

= 935kHz

= 1.045kHz

–40 IMD = –71.5dB

–40 IMD = –73.5dB

–60

–80

–60

–80

–100

–120

–140

–120

–140

1000

INPUT FREQUENCY (kHz)

1500

0

250

500

750

1250

0

50 100 150 200 250 300 350 400 450 500

INPUT FREQUENCY (kHz)

23656 F09b

23656 F09a

Figure 9a. LTC2365 Intermodulation Distortion Plot

Figure 9b. LTC2366 Intermodulation Distortion Plot

23656f

13

LTC2365/LTC2366

APPLICATIONS INFORMATION

OVERVIEW

Figures11and12detailthetimingdiagramsofconversion

cycles in 14 and 16 SCK cycles respectively.

The LTC2365/LTC2366 use a successive approximation

algorithmandinternalsample-and-holdcircuittoconvertan

analogsignaltoa12-bitserialoutput.Bothdevicesoperate

from a single 2.35V to 3.6V supply. The LTC2366 samples

at a rate of 3Msps with a 48MHz clock while the LTC2365

samples at a rate of 1Msps with a 16MHz clock.

Data Transfer

A falling CS edge starts a conversion and frames the se-

rial data transfer. SCK provides the conversion clock and

controls the data transfer during the conversion.

CS going low clocks out the ﬁrst leading zero and sub-

sequent SCK falling edges clock out the remaining data,

beginning with the second leading zero. (Therefore, the

ﬁrst SCK falling edge captures the ﬁrst leading zero and

clocks out the second leading zero). The timing diagram

in Figure 12 shows that the ﬁnal bit in the data transfer is

valid on the 16th falling edge, since it is clocked out on

the previous 15th falling edge.

TheLTC2365/LTC2366containa12-bit,switched-capacitor

ADC, a sample-and-hold, and a serial interface (see Block

Diagram) and are available in tiny 6- and 8-lead TSOT-23

packages.Thedevicesprovidesleepmodecontrolthrough

the serial interface to save power during inactive periods

(see the SLEEP MODE section).

The S6 package of the LTC2365/LTC2366 uses V as the

DD

reference and has an analog input range of 0V to V . The

DD

In applications with a slower SCK, it is possible to capture

data on each SCK rising edge. In such cases, the ﬁrst fall-

ing edge of SCK clocks out the second leading zero and

can be captured on the ﬁrst rising edge. However, the ﬁrst

leading zero clocked out when CS goes low is missed as

shown in Figures 11 and 12. In Figure 12, the 15th falling

edge of SCK clocks out the last bit and can be captured

on the 15th rising SCK edge.

ADC samples the analog input with respect to GND and

outputs the result through the serial interface.

TheTS8packageprovidestwoadditionalpins:areference

input pin, V , and an output supply pin, OV . The ADC

REF

DD

can operate with reduced spans down to 1.4V and achieve

342μV resolution. OV controls the output swing of the

DD

digital output pin, SDO, and allows the device to com-

municate with 1.8V, 2.5V or 3V digital systems.

If CS goes low while SCK is low, then CS clocks out the

ﬁrst leading zero and can be captured on the SCK rising

edge. The next SCK falling edge clocks out the second

leading zero and can be captured on the following rising

edge as shown in in Figure 10.

SERIAL INTERFACE

TheLTC2365/LTC2366communicatewithmicrocontrollers,

DSPs and other external circuitry via a 3-wire interface.

Figure 10 shows the serial interface timing diagram, while

t

1

CS

t

CONV

t

2

t

6

SCK

SDO

1

2

3

4

5

13

14

15

16

t

5

t

8

t

7

t

4

3

t

QUIET

ZERO

B11

B10

B9

13t

B1

B0

ZERO

Hi-Z STATE

(MSB)

t

SCK

ACQ

t

THROUGHPUT

23656 F10

Figure 10. LTC2365/LTC2366 Serial Interface Timing Diagram

23656f

14

LTC2365/LTC2366

APPLICATIONS INFORMATION

Achieving 3Msps Sample Rate with LTC2366

Serial Data Output (SDO)

CS going low places the sample-and-hold into hold mode

and starts a conversion. The LTC2365/LTC2366 require

at least 14 SCK cycles to ﬁnish the conversion. The

conversion terminates after the 13th falling SCK edge,

which clocks out B0. The 14th falling SCK edge places

the sample-and-hold back into sample mode.

TheSDOoutputremainsinthehighimpedancestatewhile

CS is high. The falling edge of CS starts the conversion

and enables SDO. The A/D conversion result is shifted out

on the SDO pin as a serial data stream with the MSB ﬁrst.

The data stream consists of two leading zeros followed

by 12 bits of conversion data and two trailing zeros. The

SDO output returns to the high impedance state at the

16th falling edge of SCK or sooner by bringing CS high

before the 16th falling edge of SCK.

Ignoring the last two trailing zeros, the user can bring CS

high after the 14th falling SCK edge. The user can also

keep the last two trailing zeros by bringing CS high right

after the 16th falling SCK. In both cases, a sample rate

of 3Msps can be achieved by using a 48MHz SCK clock

The output swing on the SDO pin is controlled by the V

DD

pin voltage in the S6 package and by the OV pin voltage

DD

on the LTC2366, where t

is 333ns.

in the TS8 package.

THROUGHPUT

t

1

CS

t

ACQ

CONV

t

6

2

SCK

SDO

1

2

3

4

5

13

14

t

5

t

7

t

4

9

3

t

QUIET

Z

ZERO

B11

B10

B9

B1

B0

Hi-Z STATE

(MSB)

t

THROUGHPUT

23656 F11

Figure 11. LTC2365/LTC2366 Serial Interface Timing Diagram for 14 SCK Cycles

t

1

CS

t

ACQ

CONV

t

6

2

SCK

SDO

1

2

3

4

5

13

14

15

16

t

5

t OR t

8 9

t

7

t

4

3

t

QUIET

Z

ZERO

B11

B10

B9

B1

B0

ZERO

Hi-Z STATE

(MSB)

t

THROUGHPUT

23656 F12

Figure 12. LTC2365/LTC2366 Serial Interface Timing Diagram for 16 SCK Cycles

23656f

15

LTC2365/LTC2366

APPLICATIONS INFORMATION

SLEEP MODE

Entering Sleep Mode

The LTC2365/LTC2366 provide a sleep mode to conserve

power during inactive periods. Upon power-up, holding

CS high initializes the ADC to sleep mode. In sleep mode,

all bias circuitry is shut down and only leakage currents

remain (0.1μA typ).

The ADC achieves the fastest sampling rate in operational

mode(fullpower-up).Thedevicecanalsobeputintosleep

mode for power savings during inactive periods. To force

the LTC2365/LTC2366 into sleep mode, the user can inter-

rupt the conversion process by bringing CS high between

the 2nd and 10th falling edges of SCK (see Figures 13 and

14). If CS is brought high after the 10th falling edge and

before the 16th falling edge, the device remains powered

up, but the conversion is terminated and SDO returns to

the high impedance state.

CS

1

2

10

12

14

16

SCK

SDO

VALID DATA

23656 F13

Figure 13. LTC2365/LTC2366 Operational Mode

CS

1

2

10

12

14

16

SCK

SDO

Hi-Z STATE

23656 F14

Figure 14. LTC2365/LTC2366 Entering Sleep Mode

23656f

16

LTC2365/LTC2366

APPLICATIONS INFORMATION

Exiting Sleep Mode and Power-Up Time

POWER VERSUS SAMPLING RATE

To exit sleep mode, pull CS low and perform a dummy

conversion. The LTC2365/LTC2366 device power up com-

pletely after the 16th falling edge of SCK. After powering

up, the ADC can continuously acquire an input signal

and perform conversions as described in the SERIAL

INTERFACE section (see Figure 15). The wake-up time is

333ns for the LTC2366 with a 48MHz SCK and 1μs for the

LTC2365 with a 16MHz SCK.

Figure 16 shows the power consumption of the LTC2365/

LTC2366inoperationalmode.BytakingtheADCintosleep

mode when not performing a conversion, the average

powerconsumptionoftheADCdecreasesasthesampling

rate decreases. Figure 17 shows the power consumption

versus sampling rate with the device in sleep mode when

not performing a conversion.

The sample-and-hold is in hold mode while the device is in

sleep mode. The ADC returns to sample mode after the 1st

falling edge of SCK during power-up (see Figure 15).

THE DEVICE BEGINS

TO POWER UP

THE DEVICE BEGINS

TO ACQUIRE INPUT

THE DEVICE IS FULLY

POWERED UP AND READY

TO PERFORM CONVERSION

t

POWER-UP

CS

1

2

10

12

14

16

1

2

10

12

14

16

SCK

SDO

INVALID DATA

VALID DATA

23656 F15

Figure 15. LTC2365/LTC2366 Exiting Sleep Mode

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

8

V

f

= 3V

V

f

= 3V

DD

SCK

DD

SCK

= VARIABLE

= 48MHz

7

6

5

4

3

2

1

0

16 SCKS PER CONVERSION

3.0

500

0

250

750

1000

0

500 1000 1500

SAMPLE RATE (ksps)

3000

2000 2500

SAMPLE RATE (ksps)

23656 F17

23656 F16

Figure 16. Power Consumption vs Sample Rate while

the Device Remains Powered Up Continuously

Figure 17. Power Consumption vs Sample Rate while the Device

Enters Sleep Mode when not Performing Conversions

23656f

17

LTC2365/LTC2366

APPLICATIONS INFORMATION

SINGLE-ENDED ANALOG INPUT

Choosing an Input Ampliﬁer

Choosing an input ampliﬁer is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by ampliﬁer from charging the

sampling capacitor, choose an ampliﬁer that has a low

output impedance (<100Ω) at the closed-loop bandwidth

frequency. For example, if an ampliﬁer is used in a gain

of 1 and has a unitygain bandwidth of 50MHz, then the

output impedance at 50MHz must be less than 100Ω. The

secondrequirementisthattheclosed-loopbandwidthmust

be greater than 40MHz to ensure adequate small signal

settling for full throughput rate. If slower op amps are

used, more time for settling can be provided by increas-

ing the time between conversions. The best choice for an

op amp to drive the LTC2365/LTC2366 will depend on the

application.Generally,applicationsfallintotwocategories:

AC applications where dynamic speciﬁcations are most

critical and time domain applications where DC accuracy

and settling time are most critical. The following list is a

summary of the op amps that are suitable for driving the

LTC2365/LTC2366.(Moredetailedinformationisavailable

on the Linear Technology website at www.linear.com.)

Driving the Analog Input

The analog input of the LTC2365/LTC2366 is easy to drive.

The input draws only one small current spike while charg-

ing the sample-and-hold capacitor at the end of conver-

sion. During the conversion, the analog input draws only

a small leakage current. If the source impedance of the

drivingcircuitislow,thentheinputoftheLTC2365/LT2366

can be driven directly. As source impedance increases,

so will acquisition time. For minimum acquisition time

with high source impedance, a buffer ampliﬁer should be

used. The main requirement is that the ampliﬁer driving

the analog input must settle after the small current spike

before the next conversion starts (settling time must be

less than 56ns for full throughput rate). While choosing

an input ampliﬁer, also keep in mind the amount of noise

and harmonic distortion the ampliﬁer contributes.

23656f

18

LTC2365/LTC2366

APPLICATIONS INFORMATION

LTC1566-1: Low Noise 2.3MHz Continuous Time Low-

Pass Filter.

Input Filtering and Source Impedance

Thenoiseandthedistortionoftheinputampliﬁerandother

circuitry must be considered since they will add to the

LTC2365/LTC2366 noise and distortion. The small-signal

bandwidth of the sample-and-hold circuit is 50MHz. Any

noise or distortion products that are present at the analog

inputs will be summed over this entire bandwidth. Noisy

input circuitry should be ﬁltered prior to the analog inputs

tominimizenoise. Asimple1-poleRCﬁlterissufﬁcientfor

many applications. For example, Figure 18 shows a 47pF

LT1630:Dual30MHzRail-to-RailVoltageFeedbackAmpli-

ﬁer. 2.7V to 15V supplies. Very high A , 500μV offset

VOL

and520nssettlingto0.5LSBfora4Vswing.THDandnoise

are –93dB to 40kHz and below 1LSB to 320kHz (A = 1,

V

2V into 1k, V = 5V), making the part excellent for AC

P-P

S

applications(to1/3Nyquist)whererail-to-railperformance

is desired. Quad version is available as LT1631.

LT1632:Dual45MHzRail-to-RailVoltageFeedbackAmpli-

capacitor from A to ground and a 51Ω source resistor to

IN

ﬁer. 2.7V to 15V supplies. Very high A , 1.5mV offset

VOL

limittheinputbandwidthto47MHz.The47pFcapacitoralso

acts as a charge reservoir for the input sample-and-hold

and isolates the ADC input from sampling-glitch sensitive

circuitry. High quality capacitors and resistors should be

used since these components can add distortion. NPO

and silvermica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalﬁlmsurfacemountresistors

are much less susceptible to both problems. When high

amplitude unwanted signals are close in frequency to the

desired signal frequency, a multiple pole ﬁlter is required.

Highexternalsourceresistance,combinedwiththe20pFof

input capacitance, will reduce the rated 50MHz bandwidth

and increase acquisition time beyond 56ns.

and 400ns settling to 0.5LSB for a 4V swing. It is suitable

for applications with a single 5V supply. THD and noise

are –93dB to 40kHz and below 1LSB to 800kHz (A = 1,

V

2V into 1k, V = 5V), making the part excellent for AC

P-P

S

applications where rail-to-rail performance is desired.

Quad version is available as LT1633.

LT1813: Dual 100MHz 750V/μs 3mA Voltage Feedback

Ampliﬁer. 5V to 5V supplies. Distortion is –86dB to

100kHz and –77dB to 1MHz with 5V supplies (2V

P-P

into 500). Excellent part for fast AC applications with 5V

supplies.

LT1801: 180MHz GBWP, –75dBc at 500kHz, 2mA/Ampli-

ﬁer, 8.5nV/√Hz.

LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at

5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Ampli-

ﬁer, 3.5nV/√Hz.

LTC2366

1

6

5

4

V

CS

SD0

SCK

DD

10μF

LT1810: 180MHz GBWP, –90dBc Distortion at 5MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Ampliﬁer,

16nV/√Hz.

2

3

GND

47pF

51Ω

A

IN

23656 F18

LT1818/LT1819: 400MHz, 2500V/μs, 9mA, Single/Dual

Voltage Mode Operational Ampliﬁer.

Figure 18. RC Input Filter

LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Ampliﬁer,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 3mA/Amplifier,

1.9nV√Hz.

LinearView is a trademark of Linear Technology Corpration

23656f

19

LTC2365/LTC2366

APPLICATIONS INFORMATION

Reference Input

Figure 19 shows the ideal input/output characteristics for

the LTC2365/LTC2366. The code transitions occur mid-

way between successive integer LSB values (i.e. 0.5LSB,

1.5LSB, 2.5LSB, …, FS –1.5LSB). The output code is

On the TS8 package of the LTC2365/LTC2366, the voltage

ontheV pindeﬁnesthefull-scalerangeoftheADC. The

REF

reference voltage can range from V down to 1.4V.

DD

straight binary with 1LSB = V /4096 for the S6 package

DD

Input Range

and 1LSB = V /4096 for the TS8 package.

REF

TheanaloginputoftheLTC2365/LTC2366isdrivensingle-

ended with respect to GND from a single supply. The input

BOARD LAYOUT AND BYPASSING

may swing up to V for the S6 package and to V for

DD

REF

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC2365/LTC2366, a printed circuit

boardwithgroundplaneisrequired. Layoutfortheprinted

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC. The analog

input should be screened by the ground plane.

the TS8 package. The 0V to 2.5V range is also ideally

suited for single-ended input use with V or V = 2.5V

DD

REF

for single supply applications. If the difference between

the A input and GND exceeds V for the S6 package or

IN

DD

V

REF

for the TS8 package, the output code will stay ﬁxed

at all ones, and if this difference goes below 0V, the output

code will stay ﬁxed at all zeros.

111...111

111...110

000...001

000...000

0 1LSB

FS – 1LSB

INPUT VOLTAGE (V)

23656 F19

Figure 19. LTC2365/LTC2366 Transfer Characteristics

23656f

20

LTC2365/LTC2366

APPLICATIONS INFORMATION

High quality tantalum and ceramic bypass capacitors

Figure 20 shows the recommended system ground con-

nections.Allanalogcircuitrygroundsshouldbeterminated

at the LTC2365/LTC2366. The ground return from the

LTC2365/LTC2366 to the power supply should be low

impedancefornoisefreeoperation.Digitalcircuitrygrounds

must be connected to the digital supply common.

should be used at the V and V pins as shown in the

DD

REF

Typical Application circuit on the ﬁrst page of this data

sheet. For optimum performance, a 10μF surface mount

AVX capacitor with a 0.1μF ceramic is recommended for

the V pin and a 4.7μF surface mount AVX capacitor

DD

with a 0.1μF ceramic is recommended for the V

and

REF

InapplicationswheretheADCdataoutputsandcontrolsig-

nalsareconnectedtoacontinuouslyactivemicroprocessor

bus, it is possible to get errors in the conversion results.

These errors are due to feedthrough from the micropro-

cessor to the successive approximation comparator. The

problem can be eliminated by forcing the microprocessor

into a Wait state during conversion or by using three-state

buffers to isolate the ADC data bus.

OV pins. Alternatively, 4.7μF and 10μF ceramic chip

DD

capacitors such as Murata GRM235Y5V106Z016 may

be used. The capacitors must be located as close to the

pins as possible. The traces connecting the pins and the

bypass capacitors must be kept short and should be made

as wide as possible.

CV

DD

+

10μF

PIN 1

V

CS

DD

GND

SDO

SCK

CA

IN

A

IN

VIAS TO GROUND PLANE

23656 F20

Figure 20. Power Supply Ground Practice

23656f

21

LTC2365/LTC2366

PACKAGE DESCRIPTION

S6 Package

6-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1636)

2.90 BSC

(NOTE 4)

0.62

MAX

0.95

REF

1.22 REF

1.4 MIN

1.50 – 1.75

2.80 BSC

3.85 MAX 2.62 REF

(NOTE 4)

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.30 – 0.45

6 PLCS (NOTE 3)

0.95 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.90 BSC

0.09 – 0.20

(NOTE 3)

S6 TSOT-23 0302 REV B

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193

23656f

22

LTC2365/LTC2366

PACKAGE DESCRIPTION

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

2.90 BSC

(NOTE 4)

0.52

MAX

0.65

REF

1.22 REF

1.50 – 1.75

(NOTE 4)

2.80 BSC

1.4 MIN

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.22 – 0.36

8 PLCS (NOTE 3)

0.65 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.95 BSC

0.09 – 0.20

(NOTE 3)

TS8 TSOT-23 0802

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23656f

23

LTC2365/LTC2366

TYPICAL APPLICATION

Low-Jitter Clock Timing with RF Sine Generator Using Clock

Squaring/Level Shifting Circuit and Re-Timing Flip-Flop

V

CC

1k

NC7SVU04P5X

0.1μF

MASTER CLOCK

CC

V

50Ω

1k

PRE

CLR

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

D

Q

CONV

Q

CONVERT ENABLE

NL17SZ74

CONV

LTC2366

SCK

NC7SVU04P5X

100Ω

SDO

2365/2366 TA02

RELATED PARTS

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC1402

12-Bit, 2.2Msps Serial ADC

12-/14-Bit, 2.8Msps Serial Sampling ADC

5V or 5V Supply, 4.096V or 2.5V Span

3V, Differential Input, 12mW, MSOP Package

LTC1403/LTC1403A

LTC1407/LTC1407A

LTC1860

12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package

12-Bit, 250ksps Serial ADC

5V Supply, 1-Channel, 4.3mW, MSOP-8 Package

LTC1860L

12-Bit, 150ksps Serial ADC

3V Supply, 1-Channel, 1.3mW, MSOP-8 Package

LTC1861

12-Bit, 250ksps Serial ADC

5V Supply, 2-Channel, 4.3mW, MSOP-8 Package

LTC1861L

12-Bit, 150ksps Serial ADC

3V Supply, 2-Channel, 1.3mW, MSOP-8 Package

LTC1863

12-Bit, 200ksps Serial ADC 8-Channel ADC

12-Bit, 250ksps Serial ADC 8-Channel ADC

16-Bit, 250ksps Serial ADC

5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867

5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L

5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package

LTC1863L

LTC1864/LTC1865

LTC1867

16-Bit, 200ksps Serial ADC 8-Channel ADC

16-Bit, 175ksps Serial ADC 8-Channel ADC

12-/14-Bit, 3.5Msps Serial ADC

5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L

3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867

3.3V Supply, Differential Input, 18mW, MSOP Package

LTC1867L

LTC2355/LTC2356

LTC2360/LTC2361/LTC2362 12-Bit, 100/250/500ksps Serial ADC in TSOT

3V Supply, Pin- and Software-Compatible to LTC2365/LTC2366

DACs

LTC1592

16-Bit, Serial SoftSpan^™I

DAC

1LSB INL/DNL, Software Selectable Spans

87dB SFDR, 20ns Settling Time

OUT

LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs

LTC2630

12-/10-/8-Bit Single V

DACs

SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)

OUT

References

LT1460-2.5

LT1461-2.5

LT1790-2.5

LT6660

Micropower Series Voltage Reference

Precision Voltage Reference

0.1% Initial Accuracy, 10ppm Drift

0.05% Initial Accuracy, 3ppm Drift

Micropower Series Reference in SOT-23

Ultra-Tiny Micropower Series Reference

0.05% Initial Accuracy, 10ppm Drift

2mm × 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift

SoftSpan is a trademark of Linear Technology Corporation.

23656f

LT 0408 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

型号:	LTC2365HS6#TRMPBF
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ANALOG DEVICES INC
包装说明：	VSSOP,
针数：	6
制造商包装代码：	05-08-1636
Reach Compliance Code：	compliant
风险等级：	4.32
最大模拟输入电压：	3.65 V
最小模拟输入电压：	-0.05 V
转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e3
长度：	2.9 mm
最大线性误差 (EL)：	0.0244%
湿度敏感等级：	1
模拟输入通道数量：	1
位数：	12
功能数量：	1
端子数量：	6
最高工作温度：	125 °C
最低工作温度：	-40 °C
输出位码：	BINARY
输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY
封装代码：	VSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
采样速率：	1 MHz
采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	1 mm
标称供电电压：	3 V
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.95 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	1.625 mm
Base Number Matches：	1

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