LTC2640AITS8-HM12#TRPBF原理和应用中文资料应用文章市场行情现货热卖-中国IC网-芯三七

LTC2640

Single 12-/10-/8-Bit SPI

V DACs with

OUT

10ppm/°C Reference

FEATURES

DESCRIPTION

n

Integrated Precision Reference

The LTC^®2640 is a family of 12-, 10-, and 8-bit voltage-

output DACs with an integrated, high-accuracy, low-drift

referenceinan8-leadTSOT-23package.Ithasarail-to-rail

output buffer that is guaranteed monotonic.

2.5V Full-Scale 10ppm/°C (LTC2640-L)

4.096V Full-Scale 10ppm/°C (LTC2640-H)

n

Maximum INL Error: 1LSB (LTC2640A-12)

n

Bidirectional Reference: Input or 10ppm/°C Output

TheLTC2640-Lhasafull-scaleoutputof2.5V,andoperates

from a single 2.7V to 5.5V supply. The LTC2640-H has a

full-scale output of 4.096V, and operates from a 4.5V to

5.5V supply. A 10ppm/°C reference output is available at

the REF pin.

n

Low Noise (0.7mVpp, 0.1Hz to 200kHz)

n

Guaranteed Monotonic Over Temperature

n

2.7V to 5.5V Supply Range (LTC2640-L)

n

Low Power Operation: 180μA at 3V

n

Power Down to 1.8μA Maximum (C and I Grades)

n

Each DAC can also operate in External Reference mode,

in which a voltage supplied to the REF pin sets the full-

scale output.

Asynchronous DAC Clear Pin (LTC2640-Z)

Power-On Reset to Zero or Mid-Scale options

Double-Buffered Data Latches

Guaranteed Operation from –40°C to 125°C (H-Grade)

8-Lead TSOT-23 (ThinSOT™) Package

The LTC2640 DACs use a SPI/MICROWIRE™ compatible

3-wire serial interface which operates at clock rates up

to 50MHz.

APPLICATIONS

The LTC2640 incorporates a power-on reset circuit. Op-

tions are available for Reset to Zero-Scale or Reset to

Mid-Scale after power-up.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433,

6937178 and 7414561.

n

Mobile Communications

n

Process Control and Industrial Automation

n

Automatic Test Equipment

n

Portable Equipment

n

Automotive

n

Optical Networking

(LTC2640-Z)

BLOCK DIAGRAM

V

CC

REF

Integral Nonlinearity (LTC2640A-LZ12)

1.0

V

= 3V

= 2.5V

INTERNAL

REFERENCE

CC

FS

SWITCH

SDI

0.5

0

CONTROL

DECODE LOGIC

RESISTOR

DIVIDER

24-BIT

SHIFT

REGISTER

SCK

DACREF

DAC

–0.5

–1.0

CS/LD

V

OUT

INPUT

REGISTER

DAC

REGISTER

2048

3072

0

4095

1024

CODE

GND

CLR

2640 TA01b

2640 TA01

2640fb

1

LTC2640

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Voltage (V ) ................................... –0.3V to 6V

Maximum Junction Temperature........................... 150°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

CC

CLR, CS/LD, REF_SEL, SCK, SDI................. –0.3V to 6V

V

, REF ......................... –0.3V to Min(V + 0.3V, 6V)

OUT

CC

Operating Temperature Range

LTC2640C ................................................ 0°C to 70°C

LTC2640I.............................................. –40°C to 85°C

LTC2640H (Note 3) ............................–40°C to 125°C

PIN CONFIGURATION

LTC2640-Z

LTC2640-M

TOP VIEW

CS/LD 1

SCK 2

SDI 3

8 CLR

CS/LD 1

SCK 2

SDI 3

8 REF_SEL

7 V

OUT

6 REF

GND 4

5 V

CC

GND 4

5 V

CC

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

T

= 150°C (NOTE 6), θ = 195°C/W

T

JMAX

= 150°C (NOTE 6), θ = 195°C/W

JMAX

JA

2640fb

2

LTC2640

ORDER INFORMATION

LTC2640

A

C

TS8 –L

M

12

#TRM PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = 2,500-Piece Tape and Reel

TRM = 500-Piece Tape and Reel

RESOLUTION

12 = 12-Bit

10 = 10-Bit

8 = 8-Bit

POWER-ON RESET

M = Reset to Mid-Scale

Z = Reset to Zero-Scale

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

TS8 = 8-Lead Plastic TSOT-23

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

ELECTRICAL GRADE (OPTIONAL)

A = 1LSB Maximum INL (12-Bit)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

2640fb

3

LTC2640

PRODUCT SELECTION GUIDE

V

WITH INTERNAL

POWER-ON RESET

TO CODE

FS

PART NUMBER

LTC2640A-LM12 LTDHV

LTC2640A-LZ12 LTDHW

PART MARKING* REFERENCE

PIN 8

RESOLUTION

12-Bit

10-Bit

8-Bit

V

MAXIMUM INL

1LSB

CC

2.5V • (4095/4096)

4.096V • (4095/4096)

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

Zero

REF_SEL

CLR

2.7V – 5.5V

4.5V – 5.5V

2.7V – 5.5V

4.5V – 5.5V

1LSB

LTC2640A-HM12 LTDHX

LTC2640A-HZ12 LTDHY

Mid-Scale

Zero

REF_SEL

CLR

1LSB

LTC2640-LM12

LTC2640-LM10

LTC2640-LM8

LTC2640-LZ12

LTC2640-LZ10

LTC2640-LZ8

LTDHV

LTDHZ

LTDJF

LTDHW

LTDJB

LTDJG

LTDHX

LTDJC

LTDJH

LTDHY

LTDJD

LTDJJ

Mid-Scale

Zero

REF_SEL

CLR

2.5LSB

1LSB

0.5LSB

2.5LSB

1LSB

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

12-Bit

10-Bit

8-Bit

Zero

CLR

Zero

CLR

0.5LSB

2.5LSB

1LSB

LTC2640-HM12

LTC2640-HM10

LTC2640-HM8

LTC2640-HZ12

LTC2640-HZ10

LTC2640-HZ8

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

Zero

REF_SEL

CLR

12-Bit

10-Bit

8-Bit

0.5LSB

2.5LSB

1LSB

12-Bit

10-Bit

8-Bit

Zero

CLR

Zero

CLR

0.5LSB

*The temperature grade is identiﬁed by a label on the shipping container.

2640fb

4

LTC2640

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (V_FS= 2.5V)

LTC2640-8

LTC2640-10

LTC2640-12

LTC2640A-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

l

8

10

12

Bits

LSB

Monotonicity

V

= 3V, Internal Ref. (Note 4)

CC

DNL

INL

Differential

0.5

5

0.5

1

2.5

5

1

Nonlinearity

l

Integral

Nonlinearity

V

= 3V, Internal Ref. (Note 4)

= 3V, Internal Ref.,

0.05

0.5

0.2

0.5

1

0.5

LSB

mV

CC

ZSE

Zero-Scale Error

5

0.5

5

CC

Code = 0

V

Offset Error

V

= 3V, Internal Ref. (Note 5)

0.5

10

5

0.5

10

5

0.5

10

5

0.5

10

5

mV

OS

CC

V

Temperature

OS

V

μV/°C

OSTC

Coefﬁcient

l

FSE

Full-Scale Error

V

CC

= 3V, Internal Ref. (Note 11)

0.08

0.4

0.08 0.4

0.08 0.4 %FSR

V

Full-Scale Voltage V = 3V, Internal Ref. (Note 10)

CC

FSTC

Temperature

Coefﬁcient

C-Grade

I-Grade

H-Grade

10

ppm/°C

Load Regulation Internal Ref., Mid-Scale,

= 3V 10%,

l

V

0.009 0.016

0.035 0.064

0.14 0.256

0.14 0.256 LSB/mA

CC

–5mA ≤ I

≤ 5mA,

OUT

V

= 5V 10%,

CC

–10mA ≤ I

≤ 10mA

OUT

R

DC Output

Impedance

Internal Ref., Mid-Scale,

= 3V 10%,

OUT

l

V

0.09 0.156

Ω

CC

–5mA ≤ I

≤ 5mA,

OUT

V

= 5V 10%,

CC

–10mA ≤ I

≤ 10mA

OUT

SYMBOL

PARAMETER

DAC Output Span

CONDITIONS

MIN

TYP

MAX

UNITS

V

OUT

External Reference

Internal Reference

0 to V

V

REF

0 to 2.5

PSR

Power Supply Rejection

V

CC

= 3V 10% or 5V 10%

–80

dB

I

SC

Short-Circuit Output Current (Note 6)

V

= V = 5.5V

CC

FS

l

Sinking

Zero-Scale; V

shorted to V

27

–28

48

–48

mA

OUT

CC

l

Sourcing

Full-Scale; V

shorted to GND

OUT

Power Supply

l

V

Positive Supply Voltage

Supply Current (Note 7)

For Speciﬁed Performance

2.7

5.5

V

CC

l

I

CC

V

CC

V

CC

V

CC

V

CC

= 3V, V = 2.5V, External Reference

150

180

160

190

200

240

210

260

μA

REF

= 3V, Internal Reference

= 5V, V = 2.5V, External Reference

REF

= 5V, Internal Reference

l

I

SD

Supply Current in Power-Down Mode

(Note 7)

V

= 5V, C-Grade, I-Grade

= 5V, H-Grade

0.6

1.8

4

μA

CC

2640fb

5

LTC2640

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input

l

Input Voltage Range

Resistance

0

V

kΩ

pF

CC

160

190

7.5

220

Capacitance

l

I

Reference Current, Power-Down Mode

DAC Powered Down

0.005

0.1

μA

REF

Reference Output

Output Voltage

1.240

1.250

10

1.260

V

ppm/°C

kΩ

Reference Temperature Coefﬁcient

Output Impedance

0.5

10

Capacitive Load Driving

Short-Circuit Current

μF

V

CC

= 5.5V; REF Shorted to GND

2.5

mA

Digital I/O

l

V

Digital Input High Voltage

Digital Input Low Voltage

V

= 3.6V to 5.5V

= 2.7V to 3.6V

2.4

2

V

IH

CC

l

V

IL

V

CC

V

CC

= 4.5V to 5.5V

= 2.7V to 4.5V

0.8

0.6

V

l

I

Digital Input Leakage

V

= GND to V

CC

1

μA

pF

LK

IN

C

Digital Input Capacitance

(Note 8)

2.5

IN

AC Performance

t

Settling Time

V

= 3V (Note 9)

S

CC

0.39% ( 1LSB at 8-Bits)

0.098% ( 1LSB at 10-Bits)

0.024% ( 1LSB at 12-Bits)

3.2

3.8

4.1

μs

Voltage Output Slew Rate

Capacitance Load Driving

Glitch Impulse

1

V/μs

pF

500

2.1

300

At Mid-Scale Transition

External Reference

nV•s

kHz

Multiplying Bandwidth

Output Voltage Noise Density

e

n

At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

160

150

nV√Hz

Output Voltage Noise

0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference,

20

650

670

μV

P-P

μV

P-P

μV

P-P

μV

P-P

C

= 0.33μF

REF

2640fb

6

LTC2640

TIMING CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 2.7V to 5.5V. (See Figure 1) (Note 8).

LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

l

t

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

1

4

ns

2

9

ns

3

SCK Low Time

9

ns

4

CS/LD Pulse Width

LSB SCK High to CS/LD High

CS/LD Low to SCK High

CLR Pulse Width

10

7

ns

5

ns

6

7

ns

7

20

7

ns

9

CS/LD High to SCK Pos. Edge

SCK Frequency

ns

10

50% Duty Cycle

50

MHz

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (V_FS= 4.096V)

LTC2640-8

LTC2640-10

LTC2640-12

LTC2640A-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

l

8

10

12

Bits

LSB

Monotonicity

V

= 5V, Internal Ref. (Note 4)

CC

DNL

INL

Differential

0.5

5

0.5

1

2.5

5

1

Nonlinearity

l

Integral

Nonlinearity

V

= 5V, Internal Ref. (Note 4)

= 5V, Internal Ref.,

0.05

0.5

0.2

0.5

1

0.5

LSB

mV

CC

ZSE

Zero-Scale Error

5

0.5

5

CC

Code = 0

V

Offset Error

V

= 5V, Internal Ref. (Note 5)

0.5

10

5

0.5

10

5

0.5

10

5

0.5

10

5

mV

OS

CC

V

OS

Temperature

μV/°C

OSTC

Coefﬁcient

l

FSE

Full-Scale Error

V

CC

= 5V, Internal Ref. (Note 11)

0.08

0.4

0.08 0.4

0.08 0.4 %FSR

V

Full-Scale Voltage V = 5V, Internal Ref. (Note 10)

CC

FSTC

Temperature

Coefﬁcient

C-Grade

I-Grade

H-Grade

10

ppm/°C

l

Load Regulation

V

= 5V 10%,

0.006 0.01

0.022 0.04

0.09 0.16

0.09 0.16 LSB/mA

CC

Internal Ref. Mid-Scale,

–10mA ≤ I ≤ 10mA

OUT

R

DC Output

Impedance

V

= 5V 10%,

0.09 0.156

Ω

OUT

CC

Internal Ref. Mid-Scale,

–10mA ≤ I ≤ 10mA

OUT

2640fb

7

LTC2640

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0 to V

MAX

UNITS

V

OUT

DAC Output Span

External Reference

Internal Reference

V

REF

0 to 4.096

PSR

Power Supply Rejection

V

CC

= 5V 10%

–80

dB

I

Short-Circuit Output Current (Note 6)

V

FS

= V = 5.5V

CC

SC

l

Sinking

Zero-Scale; V

shorted to V

27

–28

48

–48

mA

OUT

CC

Sourcing

Full-Scale; V

shorted to GND

OUT

Power Supply

l

V

Positive Supply Voltage

Supply Current (Note 7)

For Speciﬁed Performance

4.5

5.5

V

CC

l

I

CC

V

CC

V

CC

= 5V, V = 4.096V, External Reference

160

200

220

270

μA

REF

= 5V, Internal Reference

l

I

Supply Current in Power-Down Mode

(Note 7)

V

CC

V

CC

= 5V, C-Grade, I-Grade

= 5V, H-Grade

0.6

1.8

4

μA

SD

Reference Input

l

Input Voltage Range

Resistance

0

V

kΩ

pF

CC

160

190

7.5

220

Capacitance

l

I

Reference Current, Power-Down Mode DAC Powered Down

0.005

0.1

μA

REF

Reference Output

Output Voltage

2.032

2.048

10

2.064

V

ppm/°C

kΩ

Reference Temperature Coefﬁcient

Output Impedance

0.5

10

Capacitive Load Driving

μF

Short-Circuit Current

V

= 5.5V; REF Shorted to GND

4.3

mA

CC

Digital I/O

l

V

Digital Input High Voltage

Digital Input Low Voltage

Digital Input Leakage

2.4

V

IH

IL

V

0.8

1

I

= GND to V

μA

pF

LK

IN

CC

C

Digital Input Capacitance

(Note 8)

2.5

IN

AC Performance

t

Settling Time

V

= 5V (Note 9)

S

CC

0.39% ( 1LSB at 8 Bits)

0.098% ( 1LSB at 10 Bits)

0.024% ( 1LSB at 12 Bits)

3.7

4.2

4.6

μs

Voltage Output Slew Rate

Capacitance Load Driving

Glitch Impulse

1

V/μs

pF

500

3.0

300

At Mid-Scale Transition

External Reference

nV•s

kHz

Multiplying Bandwidth

2640fb

8

LTC2640

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise speciﬁed.

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

e

n

Output Voltage Noise Density

At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

210

200

nV√Hz

Output Voltage Noise

0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference,

20

650

670

μV

P-P

C

= 0.33μF

REF

TIMING CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 4.5V to 5.5V. (See Figure 1) (Note 8).

LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

l

t

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

1

4

ns

2

9

ns

3

SCK Low Time

9

ns

4

CS/LD Pulse Width

LSB SCK High to CS/LD High

CS/LD Low to SCK High

CLR Pulse Width

10

7

ns

5

ns

6

7

ns

7

20

7

ns

9

CS/LD High to SCK Pos. Edge

SCK Frequency

ns

10

50% Duty Cycle

50

MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the speciﬁed maximum operating junction temperature may impair

device reliability.

Note 2: All voltages are with respect to GND.

Note 7: Digital inputs at 0V or V

.

CC

Note 3: High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C.

Note 8: Guaranteed by design and not production tested.

Note 4: Linearity and monotonicity are deﬁned from code k to code

Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND.

L

N

2 – 1, where N is the resolution and k is given by k = 0.016 • (2 / V ),

L

FS

rounded to the nearest whole code. For V = 2.5V and N = 12, k = 26

FS

L

Note 10: Temperature coefﬁcient is calculated by dividing the maximum

change in output voltage by the speciﬁed temperature range.

Note 11: Full-scale error is determined using the reference voltage

measured at the REF pin.

and linearity is deﬁned from code 26 to code 4,095. For V = 4.096V

FS

and N = 12, k = 16 and linearity is deﬁned from code 16 to code 4,095.

L

Note 5: Inferred from measurement at code 16 (LTC2640-12), code 4

(LTC2640-10) or code 1 (LTC2640-8), and at full-scale.

2640fb

9

LTC2640

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2640-L12 (Internal Reference, V_FS= 2.5V)

Reference Output Voltage

vs Temperature

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.260

1.255

1.250

1.245

1.240

1.0

0.5

1.0

0.5

V

CC

= 3V

V

CC

= 3V

V

CC

= 3V

0

–0.5

–1.0

–0.5

–1.0

50

100

125 150

–50 –25

25

75

2048

3072

2048

3072

0

4095

0

4095

1024

TEMPERATURE (°C)

CODE

2640 G03

2640 G01

2640 G02

Full-Scale Output Voltage

vs Temperature

INL vs Temperature

DNL vs Temperature

1.0

0.5

1.0

0.5

2.52

2.51

2.50

2.49

2.48

V

CC

= 3V

V

CC

= 3V

V

CC

= 3V

INL (POS)

DNL (POS)

DNL (NEG)

0

INL (NEG)

–0.5

–1.0

50

100

50

100

50

100

125 150

–50 –25

25

75

125 150

–50 –25

25

75

125 150

–50 –25

25

75

0

TEMPERATURE (°C)

2640 G04

2640 G05

2640 G06

Settling to 1LSB

3/4 SCALE TO 1/4 SCALE STEP

= 3V, V = 2.5V

V

CC

L

FS

R

= 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

CS/LD

2V/DIV

V

OUT

1LSB/DIV

4.1μs

3.6μs

V

OUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

= 3V, V = 2.5V

V

CC

FS

CS/LD

2V/DIV

R

= 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

2μs/DIV

2640 G08

2640 G07

2640fb

10

LTC2640

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2640-H12 (Internal Reference, V_FS= 4.096V)

Reference Output Voltage

vs Temperature

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

2.068

2.058

2.048

2.038

2.028

V

CC

= 5V

V

CC

= 5V

V

CC

= 5V

0.5

0

–0.5

–1.0

–0.5

–1.0

2048

3072

2048

3072

50

100

125 150

0

4095

0

4095

–50 –25

25

75

1024

0

CODE

TEMPERATURE (°C)

2640 G09

2640 G10

2640 G11

Full-Scale Output Voltage

vs Temperature

INL vs Temperature

DNL vs Temperature

1.0

0.5

1.0

0.5

4.115

4.105

4.095

4.085

4.075

V

CC

= 5V

V

CC

= 5V

V

CC

= 5V

INL (POS)

DNL (POS)

DNL (NEG)

0

INL (NEG)

–0.5

–1.0

50

100

50

100

50

–50 –25

25

75

125 150

–50 –25

25

75

125 150

–50 –25

25

75 100 125 150

0

TEMPERATURE (°C)

2640 G12

2640 G13

2640 G14

Settling to 1LSB

CS/LD

5V/DIV

V

OUT

1LSB/DIV

4.6μs

3.9μs

V

OUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

= 5V, V = 4.095V

3/4 SCALE TO 1/4 SCALE STEP

V

CC

FS

V

= 5V, V = 4.095V

CS/LD

5V/DIV

CC

FS

R

= 2k, C = 100pF

L

R

= 2k, C = 100pF

L

AVERAGE OF 256 EVENTS

2μs/DIV

2640 G16

2640 G15

2640fb

11

LTC2640

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2640-10

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

1.0

0.5

1.0

0.5

V

CC

V

FS

= 5V

= 4.096V

V

CC

V

FS

= 5V

= 4.096V

INTERNAL REF.

0

–0.5

–1.0

–0.5

–1.0

512

768

0

1023

256

512

0

768

1023

256

CODE

2640 G17

2640 G18

LTC2640-8

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

0.50

0.25

0

1.0

0.5

V

CC

V

FS

= 3V

= 2.5V

V

CC

V

FS

= 3V

= 2.5V

INTERNAL REF.

0

–0.25

–0.50

–0.5

–1.0

128

192

0

255

128

192

64

0

255

64

CODE

2640 G20

2640 G19

LTC2640

Load Regulation

Current Limiting

Offset Error vs Temperature

3

2

10

0.20

V

CC

V

CC

V

CC

= 5V (LTC2640-H)

= 5V (LTC2640-L)

= 3V (LTC2640-L)

V

CC

V

CC

V

CC

= 5V (LTC2640-H)

= 5V (LTC2640-L)

= 3V (LTC2640-L)

8

0.15

0.10

0.05

0

6

4

1

2

0

–2

–4

–6

–8

–10

–0.05

–0.10

–0.15

–0.20

–1

–2

–3

INTERNAL REF.

CODE = MIDSCALE

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

2640 G23

–30

–20

–10

0

10

20

30

–30

–20

–10

0

10

20

30

I

(mA)

I

(mA)

OUT

2630 G21

2630 G22

2640fb

12

LTC2640

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2640

Gain Error vs V_CC

Gain Error vs Temperature

Large-Signal Response

0.4

0.3

0.4

0.3

EXTERNAL REF.

= 2.5V

EXTERNAL REF.

= 2.5V

V

REF

0.2

0.1

V

0.0

OUT

0.5V/DIV

–0.1

–0.2

–0.3

–0.4

–0.1

–0.2

–0.3

–0.4

V

= V = 5V

CC

FS

1/4 SCALE TO 3/4 SCALE

2.5

3

3.5

4

4.5

5

5.5

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

2640 G25

2μs/DIV

2640 G26

V

(V)

CC

2640 G24

Headroom at Rails

vs Output Current

Power-On Reset Glitch

Mid-Scale-Glitch Impulse

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

LTC2640-L

5V SOURCING

V

CC

CS/LD

5V/DIV

2V/DIV

3V (LTC2640-L) SOURCING

LTC2640-H12, V = 5V:

CC

3.0nV-s TYP

V

OUT

ZERO-SCALE

5mV/DIV

V

OUT

5V SINKING

3V (LTC2640-L) SINKING

2mV/DIV

LTC2640-L12, V = 3V:

CC

2.1nV-s TYP

200μs/DIV

0

1

2

3

4

5

6

7

8

9

10

2μs/DIV

2640 G28

2640 G27

I

(mA)

OUT

2640 G29

Supply Current vs Logic Voltage

Exiting Power-Down to Mid-Scale

Hardware CLR

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

SWEEP SCK, SDI, CS/LD

AND CLR BETWEEN

0V AND V

CC

CS/LD

2V/DIV

V

OUT

1V/DIV

V

= 5V

CC

V

OUT

0.5V/DIV

V

= 3V

CC

(LTC2640-L)

CLR

5V/DIV

LTC2640-LZ

LTC2640-H

0

1

2

3

4

5

1μs/DIV

4μs/DIV

2640 G32

2640 G30

LOGIC VOLTAGE (V)

2640 G31

2640fb

13

LTC2640

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2640

Multiplying Bandwidth

Noise Voltage vs Frequency

0.1Hz to 10Hz Voltage Noise

0

–2

500

400

300

200

100

0

INTERNAL REF.

CODE = MIDSCALE

LTC2640-L, V = 4V

CC

INTERNAL REF.

CODE = MIDSCALE

–4

–6

–8

LTC2640-H

10μV/DIV

(V = 5V)

–10

–12

–14

–16

–18

CC

LTC2640-L

V

= 5V

REF(DC)

REF(AC)

CC

(V = 4V)

= 2V

CC

= 0.2V

P-P

CODE = FULL SCALE

1s/DIV

1k

10k

100k

1000k

10k

100

1k

100k

1M

2640 G35

FREQUENCY (Hz)

2640 G33

2640 G34

PIN FUNCTIONS

CS/LD (Pin 1): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on

SDI into the register. When CS/LD is taken high, SCK

is disabled and the speciﬁed command (see Table 1) is

executed.

full-scale voltage. When Internal Reference is selected,

the 10ppm/°C 1.25V (LTC2640-L) or 2.048V (LTC2640-H)

internal reference is available at the pin. This output may

be bypassed to GND with up to 10μF (0.33μF is recom-

mended), and must be buffered when driving external DC

load current.

SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL

compatible.

V

(Pin 7): DAC Analog Voltage Output.

OUT

SDI (Pin 3): Serial Interface Data Input. Data on SDI is

clockedintotheDAContherisingedgeofSCK.TheLTC2640

accepts input word lengths of either 24- or 32-bits.

CLR (Pin 8, LTC2640-Z): Asynchronous Clear Input. A

logic low at this level-triggered input clears all registers

and causes the DAC voltage output to reset to Zero. CMOS

and TTL compatible.

GND (Pin 4): Ground.

REF_SEL (Pin 8, LTC2640-M): Selects default Reference

V

(Pin 5): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V

CC

at power-up. Tie to V to select the Internal Reference,

CC

(LTC2640-L) or 4.5V ≤ V ≤ 5.5V (LTC2640-H). Bypass

CC

or GND to select an External Reference. After power-up,

the logic state at this pin is ignored and the reference may

be changed only by software command.

to GND with a 0.1μF capacitor.

REF (Pin 6): Reference Voltage Input or Output. When

External Reference mode is selected, REF is an input

(0V ≤ V

≤ V ) where the voltage supplied sets the

REF

CC

2640fb

14

LTC2640

BLOCK DIAGRAMS

LTC2640-Z

V

CC

REF

INTERNAL

REFERENCE

SWITCH

SDI

CONTROL

DECODE LOGIC

RESISTOR

DIVIDER

SCK

24-BIT

SHIFT

REGISTER

DACREF

DAC

CS/LD

V

OUT

INPUT

REGISTER

DAC

REGISTER

CLR

GND

LTC2640-M

V

CC

REF

REF_SEL

INTERNAL

REFERENCE

SWITCH

SDI

CONTROL

DECODE LOGIC

RESISTOR

DIVIDER

SCK

24-BIT

SHIFT

REGISTER

DACREF

DAC

CS/LD

V

OUT

INPUT

REGISTER

DAC

REGISTER

GND

2640 BD

2640fb

15

LTC2640

TIMING DIAGRAM

t

1

t

4

6

2

3

SCK

SDI

1

2

3

23

24

t

10

t

5

t

7

CS/LD

2640 F01

Figure 1. Serial Interface Timing

2640fb

16

LTC2640

OPERATION

The LTC2640 is a family of single voltage-output DACs

in 8-lead ThinSOT packages. Each DAC can operate rail-

to-rail using an external reference, or with its full-scale

voltage set by an integrated reference. 12 combinations

of accuracy (12-, 10-, and 8-bit), power-on reset value

(zeroormid-scale),andfull-scalevoltage(2.5Vor4.096V)

are available. The LTC2640 is controlled using a 3-wire

SPI/MICROWIRE compatible interface.

The LTC2640-HM/LTC2640-LM provide an alternative

reset, setting the output to mid-scale when power is ﬁrst

applied.

DefaultreferencemodeselectionisdescribedintheRefer-

ence Modes section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

–0.3V ≤ V ≤ V + 0.3V (see Absolute Maximum Rat-

Power-On Reset

REF

CC

ings). Particular care should be taken to observe these

TheLTC2640-HZ/LTC2640-LZcleartheoutputtozero-scale

when power is ﬁrst applied, making system initialization

consistent and repeatable.

limitsduringpowersupplyturn-onandturn-offsequences,

when the voltage at V (Pin 5) is in transition.

CC

Transfer Function

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2640

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on if the power supply is ramped

to 5V in 1ms or more. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The digital-to-analog transfer function is:

k

ꢀ

ꢃ

V_{OUT(IDEAL) ꢂ}

=

V

_Nꢅ REF

ꢁ

ꢄ

2

where k is the decimal equivalent of the binary DAC input

code,Nistheresolution,andV iseither2.5V(LTC2640-

LM/LTC2640-LZ) or 4.096V (LTC2640-HM/LTC2640-HZ)

when in Internal Reference mode, and the voltage at REF

(Pin 6) when in External Reference mode.

REF

INPUT WORD (LTC2640-12)

COMMAND

4 DON'T-CARE BITS

DATA (12 BITS + 4 DON'T-CARE BITS)

C3 C2 C1 C0

X

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

MSB

LSB

INPUT WORD (LTC2640-10)

COMMAND

4 DON'T-CARE BITS

DATA (10 BITS + 6 DON'T-CARE BITS)

C3 C2 C1 C0

X

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

X

INPUT WORD (LTC2640-8)

COMMAND

4 DON'T-CARE BITS

DATA (8 BITS + 8 DON'T-CARE BITS)

C3 C2 C1 C0

X

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

X

2640 F02

Figure 2. Command and Data Input Format

2640fb

17

LTC2640

OPERATION

Serial Interface

While the minimum input sequence is 24-bits, it may

optionally be extended to 32-bits to accommodate micro-

processors that have a minimum word width of 16-bits

(2-bytes). To use the 32-bit width, 8 don’t-cares bits are

transferredtothedeviceﬁrst,followedbythe24-bitsequence

described. Figure 3b shows the 32-bit sequence.

The CS/LD input is level triggered. When this input is

taken low, it acts as a chip-select signal, enabling the SDI

and SCK buffers and the input shift register. Data (SDI

input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded ﬁrst, followed by

4 don’t-cares bits, and ﬁnally the 16-bit data word. The

data word comprises the 12-, 10- or 8-bit input code,

ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-cares

bits(LTC2640-12,LTC2640-10andLTC2640-8respectively;

see Figure 2). Data can only be transferred to the device

when the CS/LD signal is low, beginning on the ﬁrst rising

edge of SCK. SCK may be high or low at the falling edge

of CS/LD. The rising edge of CS/LD ends the data transfer

and causes the device to execute the command speciﬁed

in the 24-bit input sequence. The complete sequence is

shown in Figure 3a.

The 16-bit data word is ignored for all commands that do

not include a Write operation.

Reference Modes

For applications where an accurate external reference is

notavailable,theLTC2640hasauser-selectable,integrated

reference. The LTC2640-LM/LTC2640-LZ provide a full-

scaleoutputof2.5V.TheLTC2640-HM/LTC2640-HZprovide

a full-scale output of 4.096V. The internal reference can be

useful in applications where the supply voltage is poorly

regulated.InternalReferencemodecanbeselectedbyusing

command 0110, and is the power-on default for LTC2640-

HZ/LTC2640-LZ, as well as for LTC2640-HM/LTC2640-LM

when REF_SEL is tied high.

The command (C3-C0) assignments are shown in Table 1.

The ﬁrst three commands in the table consist of write and

update operations. A Write operation loads a 16-bit data

word from the 24-bit shift register into the input register.

In an Update operation, the input register is copied to the

DAC register and converted to an analog voltage at the

DAC output. Write to and Update combines the ﬁrst two

commands. The Update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

The 10ppm/°C, 1.25V (LTC2640-LM/LTC2640-LZ) or

2.048V (LTC2640-HM/LTC2640-HZ) internal reference

is available at the REF pin. Adding bypass capacitance

to the REF pin will improve noise performance; 0.33μF

is recommended, and up to 10μF can be driven without

oscillation. This output must be buffered when driving an

external DC load current.

Table 1. Command Codes

COMMAND*

Alternatively, the DAC can operate in External Reference

modeusingcommand0111.Inthismode,aninputvoltage

supplied externally to the REF pin provides the reference

C3

0

C2

0

C1 C0

0

1

0

1

0

1

0

1

Write to Input Register

(0V ≤ V

≤ V ) and the supply current is reduced.

REF

CC

External Reference mode is the power-on default for

LTC2640-HM/LTC2640-LM when REF_SEL is tied low.

0

Update (Power-Up) DAC Register

Write to and Update (Power-Up) DAC Register

Power Down

0

1

The reference mode of LTC2640-HZ/LTC2640-LZ can be

changed only by software command. The same is true for

LTC2640-HM/LTC2640-LMafterpower-on,afterwhichthe

logic state on REF_SEL is ignored.

0

1

Select Internal Reference

0

1

Select External Reference

*Command codes not shown are reserved and should not be used

2640fb

18

LTC2640

OPERATION

Power-Down Mode

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50Ω typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage is

50Ω • 1mA, or 50mV). See the graph “Headroom at Rails

vs. Output Current” in the Typical Performance Charac-

teristics section.

Forpower-constrainedapplications,theLTC2640’spower-

down mode can be used to reduce the supply current

whenever the DAC output is not needed. When in power-

down, the buffer ampliﬁer, bias circuit, and reference

circuit are disabled and draw essentially zero current. The

DAC output is put into a HIGH-impedance state, and the

output pin is passively pulled to ground through a 200k

resistor.InputandDACregistercontentsarenotdisturbed

during power-down.

The ampliﬁer is stable driving capacitive loads of up to

500pF.

Rail-to-Rail Output Considerations

The DAC can be put into power-down mode by using

command 0100. The supply current is reduced to 1.8μA

maximum(CandIgrades)andtheREFpinbecomesHIGH

impedance (typically > 1GΩ).

Inanyrail-to-railvoltageoutputdevice,theoutputislimited

to voltages within the supply range.

SincetheanalogoutputoftheDACcannotgobelowground,

it may limit the lowest codes, as shown in Figure 4b.

Similarly, limiting can occur near full-scale when the REF

pin is tied to V . If V = V and the DAC full-scale error

Normal operation resumes after executing any command

that includes a DAC update, as shown in Table 1. The

DAC is powered up and its voltage output is updated.

Normal settling is delayed while the bias, reference, and

ampliﬁer circuits are re-enabled. When the REF pin output

is bypassed to GND with 1nF or less, the power-up delay

time is 20μs for settling to 12-bits. This delay increases

to 200μs for 0.33μF, and 10ms for 10μF.

CC

REF

CC

(FSE) is positive, the output for the highest codes limits

at V , as shown in Figure 4c. No full-scale limiting can

CC

occur if V is less than V – FSE.

REF

CC

Offset and linearity are deﬁned and tested over the region

of the DAC transfer function where no output limiting can

occur.

Voltage Output

Board Layout

The LTC2640’s integrated rail-to-rail ampliﬁer has guar-

anteed load regulation when sourcing or sinking up to

10mA at 5V, and 5mA at 3V.

ThePCboardshouldhaveseparateareasfortheanalogand

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2640 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2640 is no more susceptible to

Load regulation is a measure of the ampliﬁer’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to ohms. The ampliﬁer’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

2640fb

19

LTC2640

OPERATION

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

analog ground, digital ground, and power ground. When

the LTC2640 is sinking large currents, this current ﬂows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

It is sometimes necessary to interrupt the ground plane

to conﬁne digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

2640fb

20

LTC2640

OPERATION

2640fb

21

LTC2640

OPERATION

POSITIVE

FSE

V

= V

CC

REF

V

= V

CC

REF

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

INPUT CODE

2640 F04

(c)

OUTPUT

VOLTAGE

0V

0

2,048

4,095

INPUT CODE

(a)

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits)

(a) Overall Transfer Function

(b) Effect of Negative Offset for Codes Near Zero

(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

2640fb

22

LTC2640

PACKAGE DESCRIPTION

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

2.90 BSC

(NOTE 4)

0.52

MAX

0.65

REF

1.22 REF

1.50 – 1.75

(NOTE 4)

2.80 BSC

1.4 MIN

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.22 – 0.36

8 PLCS (NOTE 3)

0.65 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.95 BSC

0.09 – 0.20

(NOTE 3)

TS8 TSOT-23 0802

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

2640fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC2640

TYPICAL APPLICATION

Programmable 5V Output

5V

0.1μF

5

4

–

0.1μF

1

10V

7

LTC2054

3

8

9

10

+

0.1μF

M9

M3

M1

5

6

2

V

CC

V

CC

REF

8

3

REF_SEL

6

LT1991

V

= 5V

OUT

SDI

OUT

7

1

2

3

SERIAL

BUS

LTC2640A

-LM12

V

OUT

P1

P3

P9

REF

2

1

5

V

SCK

EE

4

CS/LD

GND

4

0.1μF

–10V

2640 TA03

RELATED PARTS

PART NUMBER

DESCRIPTION

Single 10-Bit V

COMMENTS

LTC1663

DAC in SOT-23

V

CC

= 2.7V to 5.5V, 60μA, Internal Reference, SMBus Interface

OUT

2

LTC1669

V

= 2.7V to 5.5V, 60μA, Internal Reference, I C Interface

LTC2360-LTC2362/

LTC2365-LTC2366

12-Bit SAR ADCs in TSOT23-6/TSOT23-8 Packages 100ksps/250ksps/500ksps/1Msps/3Msps Output Rates

LTC2450/LTC2452

LTC2451/LTC2453

16-Bit Single-Ended/Differential Delta Sigma ADCs

SPI Interface, Tiny DFN Packages, 60Hz Output Rate

2

I C Interface, Tiny DFN and TSOT23-8 Packages, 60Hz Output Rate

LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit V

DACs in 16-Lead SSOP

250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

OUT

LTC2601/LTC2611/LTC2621 Single 16-/14-/12-Bit V

DACs in 10-Lead DFN

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

OUT

LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP

DACs in 16-Lead SSOP

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

OUT

LTC2604/LTC2614/LTC2624 Quad 16-/14-/12-Bit V

LTC2605/LTC2615/LTC2625 Octal 16-/14-/12-Bit V

250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

OUT

2

DACs with I C Interface

250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

OUT

2

I C Interface

2

LTC2606/LTC2616/LTC2626 Single 16-/14-/12-Bit V

DACs with I C Interface 270μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

OUT

2

I C Interface

2

LTC2609/LTC2619/LTC2629 Quad 16-/14-/12-Bit V

DACs with I C Interface

250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output with

OUT

Separate V Pins for Each DAC

REF

LTC2630

LTC2631

Single 12-/10-/8-Bit V

Reference in SC70

DACs with 10ppm/°C

180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

Rail-to-Rail Output, SPI Interface

2

Single 12-/10-/8-Bit I C V

Reference in ThinSOT

DACs with 10ppm/°C 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

OUT

2

Selectable External Ref. Mode, Rail-to-Rail Output, I C Interface

2640fb

LT 1108 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

型号:	LTC2640AITS8-HZ12#PBF
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	VSSOP,
针数：	8
制造商包装代码：	05-08-1637
Reach Compliance Code：	compliant
风险等级：	5.01
最大模拟输出电压：	4.096 V
最小模拟输出电压：
转换器类型：	D/A CONVERTER
输入位码：	BINARY
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	2.9 mm
最大线性误差 (EL)：	0.0244%
湿度敏感等级：	1
位数：	12
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	VSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1 mm
标称安定时间 (tstl)：	4.6 µs
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	1.625 mm
Base Number Matches：	1

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