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产品型号LTC2657CFE-L12#PBF的Datasheet PDF文件预览

LTC2657  
2
Octal I C 16-/12-Bit  
Rail-to-Rail DACs with  
10ppm/°C Max Reference  
DESCRIPTION  
FEATURES  
2
The LTC®2657 is a family of octal I C 16-/12-Bit Rail-to-  
n
Integrated Reference 10ppm/°C Max  
n
Maximum INL Error: ±±LꢀS  
Rail DACs with Integrated 10ppm/°C Max Reference. The  
DACs have built-in high performance, rail-to-rail, output  
buffersandareguaranteedmonotonic. TheLTC2657-Lhas  
afull-scaleoutputof2.5Vwiththeintegratedreferenceand  
operatesfromasingle2.7Vto5.5Vsupply. TheLTC2657-H  
hasafull-scaleoutputof4.096Vwiththeintegratedreference  
andoperatesfroma4.5Vto5.5Vsupply.EachDACcanalso  
operatewithanexternalreference, whichsetsthefull-scale  
output to 2 times the external reference voltage.  
n
Guaranteed Monotonic Over Temperature  
n
ꢀelectable Internal or External Reference  
n
2.7V to 5.5V Supply Range (LTC2657-L)  
n
Integrated Reference Buffers  
n
Ultralow Crosstalk between DACs(0.8nV•s)  
n
Power-On-Reset to Zero-Scale/Mid-Scale  
2
n
400kHz I C Interface  
n
Tiny 20-Lead 4mm × 5mm QFN and 20-Lead  
Thermally enhanced TSSOP packages  
2
The parts use a 2-wire I C compatible serial interface. The  
LTC2657 operates in both the standard mode (maximum  
clock rate of 100kHz) and the fast mode (maximum clock  
rateof400kHz).TheLTC2657incorporatesapower-onreset  
circuitthatiscontrolledbythePORSELpin.IfPORSEListied  
toGNDtheDACsresettozero-scaleatpower-up.IfPORSEL  
APPLICATIONS  
n
Mobile Communications  
n
Process Control and Industrial Automation  
n
Instrumentation  
Automatic Test Equipment  
n
is tied to V , the DACs reset to mid-scale at power-up.  
CC  
n
Automotive  
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other  
trademarks are the property of their respective owners. Protected by U.S. Patents including  
5396245, 6891433 and patent pending.  
BLOCK DIAGRAM  
INTERNAL REFERENCE  
REFCOMP  
REFIN/OUT  
REF  
INL vs Code (LTC2657-16)  
GND  
V
CC  
REFLO  
4
3
V
DAC A  
DAC H  
DAC G  
DAC F  
V
V
V
V
OUTA  
OUTH  
OUTG  
OUTF  
OUTE  
2
1
V
DAC B  
DAC C  
DAC D  
OUTB  
0
–1  
–2  
–3  
–4  
DAC A  
DAC B  
DAC C  
DAC D  
DAC E  
V
OUTC  
DAC F  
DAC G  
DAC H  
32768  
CODE  
128  
16384  
49152  
65535  
V
DAC E  
OUTD  
2657 TA01  
POWER-ON RESET  
PORSEL  
CA0  
CA1  
32-BIT SHIFT REGISTER  
2-WIRE INTERFACE  
SDA  
SCL  
CA2  
LDAC  
2657 BD  
2657f  
1
LTC2657  
ABSOLUTE MAXIMUM RATINGS  
(Notes 1, 2)  
Supply Voltage (V ) ...................................0.3V to 6V  
Operating Temperature Range  
CC  
SCL, SDA, LDAC, REFLO..............................0.3V to 6V  
LTC2657C ................................................ 0°C to 70°C  
LTC2657I..............................................–40°C to 85°C  
Maximum Junction Temperature........................... 150°C  
Storage Temperature Range.......................–65 to 150°C  
Lead Temperature (Soldering FE-Package, 10 sec).. 300°C  
V
to V  
.................0.3V to Min(V + 0.3V, 6V)  
OUTA  
OUTH CC  
REFIN/OUT, REFCOMP......0.3V to Min(V + 0.3V, 6V)  
CC  
PORSEL, CA0, CA1, CA2...0.3V to Min(V + 0.3V, 6V)  
CC  
PIN CONFIGURATION  
TOP VIEW  
TOP VIEW  
REFLO  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
GND  
V
V
CC  
20 19 18 17  
OUTA  
V
V
OUTB  
OUTH  
V
1
2
3
4
5
6
16  
15  
14  
13  
V
V
V
V
OUTB  
OUTH  
OUTG  
OUTF  
OUTE  
REFCOMP  
V
V
V
REFCOMP  
OUTG  
OUTF  
OUTE  
V
V
OUTC  
OUTC  
21  
21  
V
V
OUTD  
OUTD  
REFIN/OUT  
12 PORSEL  
11 CA0  
REFIN/OUT  
LDAC  
PORSEL  
CA0  
LDAC  
CA2  
CA1  
7
8
9 10  
SCL 10  
SDA  
FE PACKAGE  
UFD PACKAGE  
20-LEAD (4mm s 5mm) PLASTIC QFN  
= 150°C, θ = 43°C/W  
20-LEAD PLASTIC TSSOP  
T
= 150°C, θ = 38°C/W, θ = 10°C/W  
JA JC  
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB  
JMAX  
T
JMAX  
JA  
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB  
2657f  
2
LTC2657  
PRODUCT SELECTOR GUIDE  
LTC2657 S  
C
UFD -L 16 #TR  
PSF  
LEAD FREE DEꢀIGNATOR  
TAPE AND REEL  
TR = Tape and Reel  
REꢀOLUTION  
16 = 16-Bit  
12 = 12-Bit  
FULL-ꢀCALE VOLTAGE, INTERNAL REFERENCE MODE  
L = 2.5V  
H = 4.096V  
PACKAGE TYPE  
UFD = 20-Lead (4mm × 5mm) Plastic QFN  
FE = 20-Lead Thermally Enhanced TSSOP  
TEMPERATURE GRADE  
C = Commercial Temperature Range (0°C to 70°C)  
I = Industrial Temperature Range (–40°C to 85°C)  
ELECTRICAL GRADE (OPTIONAL)  
B = 4LSB INL (MAX)  
PRODUCT PART NUMSER  
Consult LTC Marketing for information on non-standard lead based finish parts.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  
2657f  
3
LTC2657  
ORDER INFORMATION  
TEMPERATURE MAXIMUM  
LEAD FREE FINIꢀH  
TAPE AND REEL  
PART MARKING* PACKAGE DEꢀCRIPTION  
RANGE  
INL  
LTC2657BCFE-L16#PBF  
LTC2657BIFE-L16#PBF  
LTC2657BCFE-L16#TRPBF  
LTC2657BIFE-L16#TRPBF  
LTC2657FE-L16  
LTC2657FE-L16  
20-Lead Thermally Enhanced TSSOP  
0°C to 70°C  
4
20-Lead Thermally Enhanced TSSOP  
20-Lead (4mm × 5mm) Plastic QFN  
20-Lead (4mm × 5mm) Plastic QFN  
–40°C to 85°C  
0°C to 70°C  
4
LTC2657BCUFD-L16#PBF LTC2657BCUFD-L16#TRPBF 57L16  
4
LTC2657BIUFD-L16#PBF  
LTC2657BCFE-H16#PBF  
LTC2657BIFE-H16#PBF  
LTC2657BIUFD-L16#TRPBF 57L16  
–40°C to 85°C  
0°C to 70°C  
4
LTC2657BCFE-H16#TRPBF  
LTC2657BIFE-H16#TRPBF  
LTC2657FE-H16 20-Lead Thermally Enhanced TSSOP  
LTC2657FE-H16 20-Lead Thermally Enhanced TSSOP  
4
–40°C to 85°C  
0°C to 70°C  
4
LTC2657BCUFD-H16#PBF LTC2657BCUFD-H16#TRPBF 57H16  
LTC2657BIUFD-H16#PBF LTC2657BIUFD-H16#TRPBF 57H16  
4
20-Lead (4mm × 5mm) Plastic QFN  
20-Lead (4mm × 5mm) Plastic QFN  
20-Lead Thermally Enhanced TSSOP  
20-Lead Thermally Enhanced TSSOP  
20-Lead (4mm × 5mm) Plastic QFN  
20-Lead (4mm × 5mm) Plastic QFN  
–40°C to 85°C  
0°C to 70°C  
4
LTC2657CFE-L12#PBF  
LTC2657IFE-L12#PBF  
LTC2657CUFD-L12#PBF  
LTC2657IUFD-L12#PBF  
LTC2657CFE-H12#PBF  
LTC2657IFE-H12#PBF  
LTC2657CUFD-H12#PBF  
LTC2657IUFD-H12#PBF  
LTC2657CFE-L12#TRPBF  
LTC2657IFE-L12#TRPBF  
LTC2657CUFD-L12#TRPBF  
LTC2657IUFD-L12#TRPBF  
LTC2657CFE-H12#TRPBF  
LTC2657IFE-H12#TRPBF  
LTC2657FE-L12  
LTC2657FE-L12  
57L12  
1
–40°C to 85°C  
0°C to 70°C  
1
1
57L12  
–40°C to 85°C  
0°C to 70°C  
1
LTC2657FE-H12 20-Lead Thermally Enhanced TSSOP  
LTC2657FE-H12 20-Lead Thermally Enhanced TSSOP  
1
–40°C to 85°C  
0°C to 70°C  
1
LTC2657CUFD-H12#TRPBF 57H12  
LTC2657IUFD-H12#TRPBF 57H12  
1
20-Lead (4mm × 5mm) Plastic QFN  
20-Lead (4mm × 5mm) Plastic QFN  
–40°C to 85°C  
1
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the  
shipping container.Consult LTC Marketing for information on non-standard lead based finish parts.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.  
LTC2657S-L16/LTC2657-L12 (Internal Reference = 1.25V)  
LTC2657-12  
LTC2657S-16  
ꢀYMSOL PARAMETER  
DC Performance  
Resolution  
CONDITIONꢀ  
MIN TYP MAX MIN TYP MAX  
UNITꢀ  
l
l
l
l
l
12  
12  
16  
16  
Bits  
Bits  
Monotonicity  
(Note 3)  
(Note 3)  
DNL  
INL  
Differential Nonlinearity  
0.1  
0.5  
0.5  
1
0.3  
2
1
4
LSB  
Integral Nonlinearity (Note 3)  
Load Regulation  
V
CC  
= 5.5V, V = 2.5V  
LSB  
REF  
V
= 5V 10ꢀ, Internal Reference, Mid-Scale,  
0.04 0.125  
0.6  
2
LSB/mA  
CC  
–15mA ≤ I  
≤ 15mA  
OUT  
l
V
= 3V 10ꢀ, Internal Reference, Mid-Scale,  
0.06 0.25  
1
4
LSB/mA  
CC  
–7.5mA ≤ I  
≤ 7.5mA  
OUT  
l
l
ZSE  
Zero-Scale Error  
Offset Error  
1
3
1
1
2
3
mV  
mV  
V
OS  
(Note 4) V = 1.25V  
1
2
2
REF  
V
Temperature Coefficient  
2
μV/°C  
ꢀFSR  
ppm/°C  
OS  
l
GE  
Gain Error  
0.02 0.1  
1
0.02 0.1  
1
Gain Temperature Coefficient  
2657f  
4
LTC2657  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.  
LTC2657S-L16/LTC2657-L12 (Internal Reference = 1.25V)  
ꢀYMSOL PARAMETER  
CONDITIONꢀ  
MIN  
TYP  
MAX  
UNITꢀ  
V
DAC Output Span  
Internal Reference  
External Reference = V  
0 to 2.5  
0 to 2 • V  
EXTREF  
V
V
OUT  
EXTREF  
PSR  
Power Supply Rejection  
DC Output Impedance  
V
V
10ꢀ  
–80  
dB  
Ω
CC  
l
l
R
OUT  
= 5V 10ꢀ, Internal Reference, Mid-Scale,  
≤ 15mA  
0.04  
0.15  
0.15  
CC  
–15mA ≤ I  
OUT  
V
CC  
= 3V 10ꢀ, Internal Reference, Mid-Scale,  
0.04  
Ω
–7.5mA ≤ I  
≤ 7.5mA  
OUT  
DC Crosstalk (Note 5)  
Due to Full-Scale Output Change  
Due to Load Current Change  
Due to Powering Down (per Channel)  
1.5  
2
1
μV  
μV/mA  
μV  
I
Short-Circuit Output Current (Note 6)  
V
= 5.5V, V  
= 2.8V  
SC  
CC  
EXTREF  
l
l
Code: Zero-Scale, Forcing Output to V  
20  
20  
65  
65  
mA  
mA  
CC  
Code: Full-Scale, Forcing Output to GND  
V
= 2.7V, V = 1.4V  
CC  
EXTREF  
l
l
Code: Zero-Scale, Forcing Output to V  
10  
10  
40  
40  
mA  
mA  
CC  
Code: Full-Scale, Forcing Output to GND  
Reference  
Reference Output Voltage  
1.248  
1.25  
2
1.252  
10  
V
ppm/°C  
dB  
Reference Temperature Coefficient  
Reference Line Regulation  
(Note 7) C-Grade Only  
V
V
V
V
10ꢀ  
–80  
CC  
CC  
CC  
CC  
l
l
Reference Short-Circuit Current  
REFCOMP Pin Short-Circuit Current  
Reference Load Regulation  
= 5.5V, Forcing REFIN/OUT to GND  
= 5.5V, Forcing REFCOMP to GND  
5
mA  
200  
μA  
= 3V 10ꢀ or 5V 10ꢀ, I  
Sourcing  
= 100μA  
40  
30  
mV/mA  
OUT  
Reference Output Voltage Noise Density  
Reference Input Range  
C
= C  
= 0.1μF at f = 1kHz  
REFIN/OUT  
nV/√Hz  
REFCOMP  
l
l
External Reference Mode (Note 14)  
0.5  
2.7  
V
/2  
CC  
V
μA  
pF  
Reference Input Current  
0.001  
40  
1
Reference Input Capacitance  
(Note 9)  
Power ꢀupply  
l
V
Positive Supply Voltage  
Supply Current (Note 8)  
For Specified Performance  
5.5  
V
CC  
l
l
l
l
I
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 5V, Internal Reference On  
= 5V, Internal Reference Off  
= 3V, Internal Reference On  
= 3V, Internal Reference Off  
3.1  
2.7  
3
4.25  
3.7  
3.8  
3.2  
mA  
mA  
mA  
mA  
2.6  
l
I
SD  
Supply Current in Shutdown Mode  
(Note 8)  
V
CC  
= 5V  
3
μA  
Digital I/O  
l
l
V
V
V
Low Level Input Voltage  
(SDA and SCL)  
0.3V  
V
V
IL  
CC  
High Level Input Voltage  
(SDA and SCL)  
0.7V  
CC  
IH  
l
l
l
l
Low Level Input Voltage (LDAC)  
V
CC  
V
CC  
V
CC  
V
CC  
= 4.5V to 5.5V  
= 2.7V to 4.5V  
= 3.6V to 5.5V  
= 2.7V to 3.6V  
0.8  
0.6  
V
V
V
V
IL(LDAC)  
V
High Level Input Voltage (LDAC)  
2.4  
2
IH(LDAC)  
2657f  
5
LTC2657  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.  
LTC2657S-L16/LTC2657-L12 (Internal Reference = 1.25V)  
ꢀYMSOL PARAMETER  
CONDITIONꢀ  
MIN  
TYP  
MAX  
UNITꢀ  
l
l
l
V
V
Low Level Input Voltage (CA0 and CA2) See Test Circuit 1  
High Level Input Voltage (CA0 and CA2) See Test Circuit 1  
0.15V  
V
V
IL(CA)  
IH(CA)  
CC  
0.85V  
CC  
R
R
R
See Test Circuit 2  
See Test Circuit 2  
See Test Circuit 2  
Sink Current = 3mA  
10  
10  
kΩ  
Resistance from CA (n = 0,1, 2)  
INH  
INL  
INF  
OL  
n
to V to Set CA = V  
CC  
CC  
n
l
l
kΩ  
Resistance from CA (n = 0,1, 2)  
n
to GND to Set CA = GND  
n
2
0
MΩ  
Resistance from CA (n = 0,1, 2)  
n
to V or GND to Set CA =FLOAT  
CC  
n
l
l
V
Low Level Output Voltage  
Output Fall Time  
0.4  
V
t
t
I
V = V  
to V = V  
,
20+0.1C  
250  
ns  
OF  
O
IH(MIN)  
O
IL(MAX)  
B
C = 10pF to 400pF (Note 13)  
B
l
Pulse Width of Spikes Suppressed by  
Input Filter  
0
50  
ns  
SP  
IN  
l
l
l
l
Input Leakage  
0.1V ≤ V ≤ 0.9VCC  
1
μA  
pF  
pF  
pF  
CC  
IN  
C
C
C
I/O Pin Capacitance  
(Note 9)  
10  
IN  
Capacitance Load for Each Bus Line  
400  
10  
B
External Capacitive Load on Address  
Pins CA0, CA1 and CA2  
CAn  
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.  
VCC = ±.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657S-H16/LTC2657-H12 (Internal Reference = 2.0±8V)  
LTC2657-12  
LTC2657S-16  
ꢀYMSOL PARAMETER  
DC Performance  
Resolution  
CONDITIONꢀ  
MIN TYP MAX MIN TYP MAX  
UNITꢀ  
l
l
l
l
l
12  
12  
16  
16  
Bits  
Bits  
Monotonicity  
(Note 3)  
(Note 3)  
DNL  
INL  
Differential Nonlinearity  
0.1  
0.5  
0.5  
1
0.3  
2
1
4
LSB  
Integral Nonlinearity (Note 3)  
Load Regulation  
V
= 5.5V, V = 2.5V  
LSB  
CC  
REF  
V
= 5V 10ꢀ, Internal Reference,  
0.04 0.125  
0.6  
2
LSB/mA  
CC  
Mid-Scale, –15mA ≤ I  
≤ 15mA  
OUT  
l
l
ZSE  
Zero-Scale Error  
Offset Error  
1
3
1
1
3
mV  
mV  
V
OS  
(Note 4) V = 2.048V  
1
2
2
REF  
V
Temperature Coefficient  
2
2
μV/°C  
ꢀFSR  
ppm/°C  
OS  
l
GE  
Gain Error  
0.02  
1
0.1  
0.02  
1
0.1  
Gain Temperature Coefficient  
2657f  
6
LTC2657  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VCC = ±.5V to 5.5V, VOUT unloaded unless otherwise specified.  
LTC2657S-H16/LTC2657-H12 (Internal Reference = 2.0±8V)  
ꢀYMSOL PARAMETER  
CONDITIONꢀ  
MIN  
TYP  
MAX  
UNITꢀ  
V
DAC Output Span  
Internal Reference  
External Reference = V  
0 to 4.096  
0 to 2 • V  
EXTREF  
V
V
OUT  
EXTREF  
PSR  
Power Supply Rejection  
DC Output Impedance  
V
V
10ꢀ  
–80  
dB  
Ω
CC  
l
R
OUT  
= 5V 10ꢀ, Internal Reference, Mid-  
Scale,  
0.04  
0.15  
CC  
–15mA ≤ I  
≤ 15mA  
OUT  
DC Crosstalk  
Due to Full-Scale Output Change  
Due to Load Current Change  
Due to Powering Down (per Channel)  
1.5  
2
1
μV  
μV/mA  
μV  
I
SC  
Short-Circuit Output Current (Note 4)  
V
= 5.5V, V  
= 2.8V  
CC  
EXTREF  
l
l
Code: Zero-Scale, Forcing Output to V  
20  
20  
65  
65  
mA  
mA  
CC  
Code: Full-Scale, Forcing Output to GND  
Reference  
Reference Output Voltage  
2.044  
2.048  
2
2.052  
10  
V
ppm/°C  
dB  
Reference Temperature Coefficient  
Reference Line Regulation  
(Note 7) C-Grade Only  
V
V
V
V
10ꢀ  
–80  
CC  
CC  
CC  
CC  
l
l
Reference Short-Circuit Current  
REFCOMP Pin Short-Circuit Current  
Reference Load Regulation  
= 5.5V, Forcing REFIN/OUT to GND  
= 5.5V, Forcing REFCOMP to GND  
5
mA  
200  
μA  
= 3V 10ꢀ or 5V 10ꢀ, I  
Sourcing  
= 100μA  
40  
35  
mV/mA  
OUT  
Reference Output Voltage Noise Density  
Reference Input Range  
C
= C  
= 0.1μF at f = 1kHz  
REFIN/OUT  
nV/√Hz  
REFCOMP  
l
l
l
External Reference Mode (Note 14)  
0.5  
4.5  
V /2  
CC  
V
μA  
pF  
Reference Input Current  
0.001  
40  
1
Reference Input Capacitance  
(Note 9)  
Power ꢀupply  
l
V
Positive Supply Voltage  
Supply Current (Note 8)  
For Specified Performance  
5.5  
V
CC  
l
l
I
CC  
V
CC  
V
CC  
= 5V, Internal Reference On  
= 5V, Internal Reference Off  
3.3  
3
4.25  
3.7  
mA  
mA  
l
I
SD  
Supply Current in Shutdown Mode (Note 8) V = 5V  
3
μA  
CC  
Digital I/O  
l
l
l
l
l
l
l
V
V
V
V
V
V
Low Level Input Voltage (SDA and SCL)  
High Level Input Voltage (SDA and SCL)  
0.3V  
V
V
IL  
CC  
0.7V  
IH  
CC  
Low Level Input Voltage (LDAC)  
High Level Input Voltage (LDAC)  
Low Level Input Voltage (CA0 to CA2)  
High Level Input Voltage (CA0 to CA2)  
V
V
= 4.5Vto 5.5V  
= 4.5Vto 5.5V  
0.8V  
V
IL(LDAC)  
IH(LDAC)  
IL(CA)  
IH(CA)  
CC  
2.4  
V
CC  
See Test Circuit 1  
See Test Circuit 1  
See Test Circuit 2  
0.15V  
V
CC  
0.85V  
V
CC  
R
INH  
R
INL  
R
INF  
OL  
10  
10  
kΩ  
Resistance from CA (n = 0,1, 2)  
n
to V to Set CA = V  
CC  
n
CC  
l
l
l
See Test Circuit 2  
See Test Circuit 2  
Sink Current = 3mA  
kΩ  
MΩ  
V
Resistance from CA (n = 0,1, 2)  
n
to GND to Set CA = GND  
n
2
0
Resistance from CA (n = 0,1, 2)  
n
to V or GND to Set CA = FLOAT  
CC  
n
V
Low Level Ouput Voltage  
0.4  
2657f  
7
LTC2657  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VCC = ±.5V to 5.5V, VOUT unloaded unless otherwise specified.  
LTC2657S-H16/LTC2657-H12 (Internal Reference = 2.0±8V)  
ꢀYMSOL PARAMETER  
CONDITIONꢀ  
V = V  
MIN  
TYP  
MAX  
UNITꢀ  
l
l
t
t
I
Output Fall Time  
to V = V  
,
20+0.1C  
B
250  
ns  
OF  
SP  
IN  
O
IH(MIN)  
O
IL(MAX)  
C = 10pF to 400pF (Note 13)  
B
Pulse Width of Spikes Suppressed by Input  
Filter  
0
50  
ns  
l
l
l
l
Input Leakage  
0.1V ≤ V ≤ 0.9V  
1
μA  
pF  
pF  
pF  
CC  
IN  
CC  
C
C
C
I/O Pin Capacitance  
(Note 9)  
10  
IN  
Capacitance Load for Each Bus Line  
400  
10  
B
External Capacitive Load on Address Pins  
CA0, CA1 and CA2  
CAn  
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.  
VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2657S-H16/LTC2657-H12/ LTC2657S-L16/LTC2657-L12  
ꢀYMSOL PARAMETER  
AC Performance  
CONDITIONꢀ  
MIN  
TYP  
MAX  
UNITꢀ  
t
Settling Time (Note 10)  
0.024ꢀ ( 1LSB at 12 Bits)  
0.0015ꢀ ( 1LSB at 16 Bits)  
3.9  
9.1  
μs  
μs  
S
Settling Time for 1LSB Step  
0.024ꢀ ( 1LSB at 12 Bits)  
0.0015ꢀ ( 1LSB at 16 Bits)  
2.4  
4.5  
μs  
μs  
Voltage Output Slew Rate  
Capacitive Load Driving  
Glitch Impulse (Note 11)  
1.8  
1000  
4
V/μs  
pF  
At Mid-Scale Transition, L-Option  
At Mid-Scale Transition, H-Option  
nV•s  
nV•s  
nV•s  
kHz  
7
DAC-to-DAC Crosstalk (Note 12)  
Multiplying Bandwidth  
C
= C  
= 0.22μF  
REFIN/OUT  
0.8  
150  
REFCOMP  
e
Output Voltage Noise Density  
At f = 1kHz  
At f = 10kHz  
85  
80  
nV/√Hz  
nV/√Hz  
n
Output Voltage Noise  
0.1Hz to 10Hz, Internal Reference (L-Options)  
0.1Hz to 10Hz, Internal Reference (H-Options)  
0.1Hz to 200kHz, Internal Reference (L-Options)  
0.1Hz to 200kHz, Internal Reference (H-Options)  
8
μV  
μV  
μV  
μV  
P-P  
P-P  
P-P  
P-P  
12  
600  
650  
2657f  
8
LTC2657  
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature  
range, otherwise specifications are at TA = 25°C. LTC2657S-L16/LTC2657-L12/LTC2657S-H16/LTC2657-H12 (see Figure 1).  
ꢀYMSOL PARAMETER  
CONDITIONꢀ  
MIN  
TYP  
MAX  
UNITꢀ  
V
CC  
= 2.7V to 5.5V  
l
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency  
0
0.6  
400  
kHz  
μs  
μs  
μs  
μs  
μs  
ns  
ns  
ns  
μs  
μs  
ns  
SCL  
Hold Time (Repeated) Start Condition  
Low Period of the SCL Clock Pin  
High Period of the SCL Clock Pin  
Set-Up Time for a Repeated Start Program  
Data Hold Time  
HD(STA)  
LOW  
HIGH  
SU(STA)  
HD(DAT)  
SU(DAT)  
r
1.3  
0.6  
0.6  
0
0.9  
Data Set-Up Time  
100  
20+0.1C  
20+0.1C  
0.6  
Rise Time of Both SDA and SCL Signals  
Fall Time of Both SDA and SCL Signals  
Set-Up Time for Stop Condition  
Bus Free Time Between a Stop and Start Condition  
300  
300  
B
B
f
SU(STO)  
BUF  
1.3  
Falling edge of the 9th Clock of the 3rd Input Byte  
to LDAC High or Low Transition  
400  
1
l
t
2
LDAC Low Pulse Width  
20  
ns  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 7: Temperature coefficient is calculated by dividing the maximum  
change in output voltage by the specified temperature range.  
Note 8: Digital inputs at 0V or V  
.
CC  
Note 9: Guaranteed by design and not production tested.  
Note 10: Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale  
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 200pF to GND.  
Note 2: All voltages are with respect to GND.  
Note 3: Linearity and monotonicity are defined from code kL to code  
N
2 – 1, where N is the resolution and kL is the lower end code for which  
Note 11: V = 5V (H-Options) or V = 3V (L-Options), internal reference  
CC  
CC  
no output limiting occurs. For V = 2.5V and N = 16, kL = 128 and  
REF  
mode. DAC is stepped 1LSB between half-scale and half-scale –1. Load is  
2k in parallel with 200pF to GND.  
Note 12: DAC-to-DAC crosstalk is the glitch that appears at the output  
linearity is defined from code 128 to code 65535. For V = 2.5V and  
REF  
N = 12, kL = 8 and linearity is defined from code 8 to code 4,095.  
Note ±: Inferred from measurement at code 128 (LTC2657-16) or code 8  
(LTC2657-12).  
of one DAC due to a full-scale change at the output of another DAC. It is  
measured with V = 5V, using internal reference, with the measured DAC  
CC  
Note 5: DC crosstalk is measured with V = 5V and using internal  
CC  
at mid-scale.  
reference with the measured DAC at mid-scale.  
Note 13: C = capacitance of one bus line in pF.  
B
Note 6: This IC includes current limiting that is intended to protect the  
device during momentary overload conditions. Junction temperature can  
exceed the rated maximum during current limiting. Continuous operation  
above the specified maximum operating junction temperature may impair  
device reliability.  
Note 1±: Gain error specification may be degraded for reference input  
voltages less than 1V. See Gain Error vs Reference Input curve in the  
Typical Performance Characteristics section.  
2657f  
9
LTC2657  
LTC2657-L16, TA = 25°C unless otherwise noted.  
TYPICAL PERFORMANCE CHARACTERISTICS  
Integral Nonlinearity (INL)  
Differential Nonlinearity (DNL)  
INL vs Temperature  
4
3
1
0.5  
0
4
V
= 3V  
V
= 3V  
V
= 3V  
CC  
CC  
CC  
3
2
2
1
INL (POS)  
INL (NEG)  
1
0
0
–1  
–2  
–3  
–4  
–1  
–2  
–3  
–4  
–0.5  
–1  
128  
16384  
32768  
CODE  
49152  
65535  
128  
16384  
32768 49152  
CODE  
65535  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
2657 G01  
2657 G02  
2657 G03  
REFIN/OUT Output Voltage  
vs Temperature  
DNL vs Temperature  
1
1.253  
1.252  
1.251  
1.250  
1.249  
1.248  
1.247  
V
= 3V  
CC  
V
= 3V  
CC  
0.5  
DNL (POS)  
0
DNL (NEG)  
–0.5  
–1  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
3586 G35  
2657 G05  
ꢀettling to ±1LꢀS Rising  
ꢀettling to ±1LꢀS Falling  
3/4 SCALE TO 1/4 SCALE STEP  
9TH CLOCK OF  
3RD DATA BYTE  
SCL  
3V/DIV  
V
R
= 3V, V = 2.5V  
CC  
L
FS  
= 2k, C = 200pF  
L
AVERAGE OF 2048 EVENTS  
1/4 SCALE TO 3/4  
SCALE STEP  
= 3V, V = 2.5V  
V
OUT  
100μV/DIV  
V
R
CC  
L
FS  
L
= 2k, C = 200pF  
AVERAGE OF 2048  
EVENTS  
8.6μs  
SCL  
3V/DIV  
V
9TH CLOCK OF  
3RD DATA BYTE  
OUT  
150μV/DIV  
9μs  
2μs/DIV  
2μs/DIV  
2657 G07  
2657 G08  
2657f  
10  
LTC2657  
LTC2657-H16, TA = 25°C unless otherwise noted.  
TYPICAL PERFORMANCE CHARACTERISTICS  
Integral Nonlinearity (INL)  
Differential Nonlinearity (DNL)  
INL vs Temperature  
4
3
1
4
V
= 5V  
V
= 5V  
V
= 5V  
CC  
CC  
CC  
3
2
0.5  
2
INL (POS)  
INL (NEG)  
1
1
0
0
0
–1  
–2  
–3  
–4  
–1  
–2  
–3  
–4  
–0.5  
–1  
128  
16384  
32768  
CODE  
49152  
65535  
128  
16384  
32768  
CODE  
49152  
65535  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
2657 G10  
2657 G011  
3586 G35  
REFIN/OUT Output Voltage  
vs Temperature  
DNL vs Temperature  
2.054  
2.052  
2.050  
2.048  
2.046  
2.044  
2.042  
1
V
= 5V  
V
= 5V  
CC  
CC  
0.5  
DNL (POS)  
DNL (NEG)  
0
–0.5  
–1  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
2657 G14  
2657 G13  
ꢀettling to ±1LꢀS Rising  
ꢀettling to ±1LꢀS Falling  
9TH CLOCK OF  
3RD DATA BYTE  
9.2μs  
SCL  
5V/DIV  
V
OUT  
250μV/DIV  
9.7μs  
3/4 SCALE TO 1/4 SCALE  
STEP  
9TH CLOCK OF  
3RD DATA BYTE  
V
V
R
= 5V, V = 4.096V  
= 2k, C = 200pF  
OUT  
CC  
L
FS  
L
250μV/DIV  
1/4 SCALE TO 3/4  
SCALE STEP  
AVERAGE OF 2048  
EVENTS  
SCL  
5V/DIV  
V
R
= 5V, V = 4.096V  
CC  
L
FS  
= 2k, C = 200pF  
L
AVERAGE OF 2048 EVENTS  
2μs/DIV  
2μs/DIV  
2657 G16  
2657 G17  
2657f  
11  
LTC2657  
LTC2657-12, TA = 25°C unless otherwise noted.  
TYPICAL PERFORMANCE CHARACTERISTICS  
Integral Nonlinearity (INL)  
Differential Nonlinearity (DNL)  
ꢀettling to ±1LꢀS  
1
1
V
V
= 5V  
REF  
V
V
= 5V  
REF  
CC  
CC  
3/4 SCALE TO 1/4 SCALE STEP  
= 2.048V  
= 2.048V  
V
R
= 3V, V = 2.5V  
= 2k, C = 200pF  
CC  
L
FS  
L
0.5  
0.5  
AVERAGE OF 2048 EVENTS  
V
OUT  
500μV/DIV  
3.5μs  
0
0
–0.5  
–1  
–0.5  
SCL  
3V/DIV  
9TH CLOCK OF  
3RD DATA BYTE  
–1  
8
1024  
2048  
3072  
4095  
8
1024  
2048  
3072  
4095  
2μs/DIV  
CODE  
CODE  
2657 G21  
2657 G19  
2657 G20  
LTC2657  
Load Regulation  
Headroom at Rails  
vs Output Current  
Current Limiting  
10  
0.20  
0.15  
0.10  
0.05  
0
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
V
V
= 5V (LTC2657-H)  
= 3V (LTC2657-L)  
V
CC  
V
CC  
= 5V (LTC2657-H)  
= 3V (LTC2657-L)  
CC  
CC  
5V SOURCING  
8
6
INTERNAL REF.  
CODE = MID-SCALE  
INTERNAL REF.  
CODE = MID-SCALE  
3V SOURCING  
(LTC2657-L)  
4
2
0
–2  
–4  
–6  
–8  
–10  
–0.05  
–0.10  
–0.15  
–0.20  
5V  
SINKING  
3V SINKING  
(LTC2657-L)  
–50 –40 –30 –20 –10  
0
10 20 30 40 50  
–50 –40 –30 –20 –10  
0
10 20 30 40 50  
0
1
2
3
4
5
6
7
8
9
10  
I
(mA)  
I
(mA)  
I
(mA)  
OUT  
OUT  
OUT  
2657 G22  
2657 G23  
2657 G24  
Offset Error vs Temperature  
Zero-ꢀcale Error vs Temperature  
Gain Eror vs Temperature  
1
3
2.5  
2
64  
0.75  
0.5  
48  
32  
16  
0
0.25  
0
–0.25  
–0.5  
–0.75  
–1  
1.5  
1
–16  
–32  
–48  
–64  
0.5  
0
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
2657 G25  
2657 G26  
2657 G27  
2657f  
12  
LTC2657  
LTC2657, TA = 25°C unless otherwise noted.  
TYPICAL PERFORMANCE CHARACTERISTICS  
Offset Error vs Reference Input  
Gain Error vs Reference Input  
ICC ꢀhutdown vs VCC  
2
64  
48  
450  
400  
350  
300  
250  
200  
150  
100  
50  
V
= 5.5V  
V
= 5.5V  
CC  
CC  
GAIN ERROR OF 8 CHANNELS  
GAIN ERROR OF 8 CHANNELS  
1.5  
1
32  
0.5  
16  
0
0.5  
–1  
0
–16  
–32  
–48  
–1.5  
–2  
–64  
0
0.5  
1
1.5  
2
2.5  
0.5  
1
1.5  
2
2.5  
2.5  
3.0  
3.5  
4.0  
(V)  
4.5  
5.0  
5.5  
REFERENCE VOLTAGE (V)  
REFERENCE VOLTAGE (V)  
V
CC  
2657 G28  
2657 G29  
2657 G30  
ꢀupply Current vs Logic Voltage  
ꢀupply Current vs Temperature  
ICC ꢀhutdown vs Temperature  
4.0  
3.6  
3.2  
2.8  
2.4  
2.0  
4.0  
3.5  
3
2
V
= 5V  
SWEEP SCL, SDA  
BETWEEN OV AND V  
CC  
(LTC2657-H)  
CC  
LTC2657-H  
= 5V, CODE = MID-SCALE  
INTERNAL REFERENCE  
V
CC  
3.0  
2.5  
1
LTC2657-L  
LTC2657-H  
V
= 3V, CODE = MID-SCALE  
V
= 3V  
CC  
CC  
V
CC  
= 5V  
INTERNAL REFERENCE  
(LTC2657-L)  
LTC2657-L  
= 3V  
V
CC  
2.0  
0
0
1
2
3
4
5
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
–50 –30 –10 10 30 50 70 90 110 130  
TEMPERATURE (°C)  
LOGIC VOLTAGE (V)  
2657 G31  
2657 G32  
2657 G33  
Multiplying Sandwidth  
Large ꢀignal Response  
Mid-ꢀcale Glitch Impulse  
8
6
9th CLOCK OF  
3RD DATA BYTE  
SCL  
5V/DIV  
4
2
0
V
OUT  
LTC2657-H16,  
0.5V/DIV  
V
V
= 5V  
REF  
ZERO SCALE  
CC  
V
= 5V  
–2  
–4  
–6  
–8  
–10  
–12  
CC  
= 2.048V  
7nV-s TYP  
TO FULL SCALE  
LTC2657-L16,  
V
OUT  
V
= 3V  
CC  
5mV/DIV  
V
V
V
= 5V  
REF(DC)  
REF(AC)  
CC  
4nV-s TYP  
= 2V  
= 0.2V  
PP  
CODE = FULL-SCALE  
1k  
10k  
100k  
1M  
2μs/DIV  
2μs/DIV  
FREQUENCY (Hz)  
2657 G36  
2657 G35  
2657 G34  
2657f  
13  
LTC2657  
LTC2657  
TYPICAL PERFORMANCE CHARACTERISTICS  
DAC to DAC Crosstalk (Dynamic)  
Power On Reset to Zero-ꢀcale  
Power On Reset to Mid-ꢀcale  
LTC2657-H  
ONE DAC  
SWITCH FS-0  
2V/DIV  
V
CC  
V
CC  
2V/DIV  
2V/DIV  
LTC2657-H16, V = 5V, 0.8nV • s TYP  
REFCOMP  
CC  
V
OUT  
C
= C  
= 0.22μF  
REFOUT  
ZERO-SCALE  
V
10mV/DIV  
V
OUT  
OUT  
1V/DIV  
0.5mV/DIV  
200μs/DIV  
250μs/DIV  
2μs/DIV  
2657 G38  
2657 G39  
2657 G37  
Noise Voltage Density  
vs Frequency  
DAC Output 0.1Hz to 10Hz  
Voltage Noise  
Reference Output 0.1Hz to 10Hz  
Voltage Noise  
1200  
1000  
800  
600  
400  
200  
0
V
= 5V  
V
= 5V, V = 2.5V  
V
C
= 1.25V  
REFOUT  
REFCOMP  
CC  
CC  
FS  
CODE = MID-SCALE  
INTERNAL REF  
CODE = MID-SCALE  
INTERNAL REF  
= C  
= 0.1μF  
REFOUT  
C
= C  
= 0.1μF  
C
= C  
= 0.1μF  
REFCOMP  
REFOUT  
REFCOMP  
REFOUT  
5μV/DIV  
2μV/DIV  
LTC2657-H  
LTC2657-L  
10  
1
100  
1k  
10k 100k  
1M  
1 SEC/DIV  
1 SEC/DIV  
FREQUENCY (Hz)  
2657 G41  
2657 G42  
2657 G40  
2657f  
14  
LTC2657  
(QFN/TꢀꢀOP)  
PIN FUNCTIONS  
V
toV  
(Pins1,3,±,13,1±,15,16,20/Pins2, This high impedance pin requires a pull-up resistor or  
OUTA  
OUTH  
3, 5, 6, 15, 16, 17, 18): DAC Analog Voltage Outputs.  
The output range is 0V to 2 times the voltage at the  
REFIN/OUT pin.  
current source to V .  
CC  
ꢀDA (Pin 9/Pin 11 ): Serial Data Bidirectional Pin. Data  
is shifted into the SDA pin and acknowledged by the  
REFCOMP(Pin2/Pin±):InternalReferenceCompensation SDA pin. This is a high impedance pin while data is  
pin. For low noise and reference stability, tie 0.1μF cap  
shifted in. It is an open-drain N-channel output during  
to GND. Connect to GND to use an external reference acknowledgement. This pin requires a pull-up resistor  
at start-up. Command 0111b must still be issued to or current source to V .  
turn off internal reference.  
CC  
CA1 (Pin 10/Pin 12): Chip Address Bit 1. Tie this pin  
2
REFIN/OUT (Pin 5/Pin 7): This pin acts as the Internal to V , GND or leave it floating to select an I C slave  
Reference output in Internal Reference mode and acts address for the part (See Table 2)  
as the Reference Input pin in External Reference mode.  
When acting as an output the nominal voltage at this  
pin is 1.25V for-L Options and 2.048V for-H Options.  
For low noise and reference stability tie a capacitor  
to GND. Capacitor value must be <= C  
In External Reference mode, the allowable reference  
input voltage range is 0.5V to V /2  
CC  
CA0 (Pin 11/Pin 13): Chip Address Bit 0. Tie this pin  
2
to V , GND or leave it floating to select an I C slave  
CC  
address for the part (See Table 2).  
PORꢀEL(Pin12/Pin1±):Power-On-ResetSelectpin.If  
.
REFCOMP  
tiedtoGND, thepartresetstoZero-Scaleatpowerup. If  
tied to V , the part resets to Mid-Scale at power up.  
.
CC  
CC  
V
(Pin 17/Pin 19): Supply Voltage Input. For –L  
LDAC (Pin 6/Pin 8): Asynchronous DAC Update Pin.  
A falling edge on this input after four bytes have been  
written into the part immediately updates the DAC  
register with the contents of the input register. A low  
on this input without a complete 32-bit (four bytes  
including the slave address) data write transfer to the  
part does not update the DAC output. Software power-  
down is disabled when LDAC is low.  
CC  
Options, 2.7V ≤ V ≤ 5.5V, and for –H Options, 4.5V  
CC  
≤ V ≤ 5.5V. Bypass to ground with a 0.1μF capacitor  
placed as close to pin as possible.  
CC  
GND (Pin 18/Pin 20): Ground.  
REFLO (Pin 19/Pin 1): Reference Low pin. The voltage  
at this pin sets the zero-scale voltage of all DACs. This  
pin should be tied to GND.  
CA2 (Pin 9/Pin 7): Chip Address Bit 2. Tie this pin  
2
ExposedPad(Pin21/Pin21):Ground.MustbeSoldered  
to PCB Ground.  
to V , GND or leave it floating to select an I C slave  
CC  
address for the part (See Table 2).  
ꢀCL (Pin 8/Pin 10): Serial Clock Input Pin. Data is  
shifted into the SDA pin at the rising edges of the clock.  
2657f  
15  
LTC2657  
BLOCK DIAGRAM  
INTERNAL REFERENCE  
REFCOMP  
GND  
REFIN/OUT  
REF  
V
CC  
REFLO  
V
DAC A  
DAC H  
DAC G  
DAC F  
V
V
V
V
OUTA  
OUTH  
OUTG  
OUTF  
OUTE  
V
OUTB  
DAC B  
DAC C  
DAC D  
V
OUTC  
V
OUTD  
DAC E  
POWER-ON RESET  
PORSEL  
CA0  
CA1  
32-BIT SHIFT REGISTER  
2-WIRE INTERFACE  
SDA  
SCL  
CA2  
LDAC  
2657 BD  
TEST CIRCUIT  
Test Circuit 1  
Test Circuit 2  
V
DD  
1007  
CA  
n
R /R /R  
INH INL INF  
V
/V  
CAn  
IH(CA ) IL(CA )  
n
n
2606 TC  
GND  
2657f  
16  
LTC2657  
TIMING DIAGRAM  
SDA  
t
t
f
SU(DAT)  
t
f
t
t
r
t
t
SP  
t
r
t
BUF  
LOW  
HD(STA)  
SCL  
t
t
t
SU(STO)  
HD(STA)  
SU(STA)  
t
t
HIGH  
S
S
P
S
HD(DAT)  
r
2657 F01  
ALL VOLTAGE LEVELS REFER TO V  
AND V  
LEVELS  
IL(MAX)  
IH(MIN)  
9TH CLOCK  
OF 3RD  
DATA BYTE  
SCL  
t
1
LDAC  
2657 F01b  
Figure 1  
2657f  
17  
LTC2657  
OPERATION  
The LTC2657 is a family of octal voltage output DACs  
in 20-lead 4mm × 5mm QFN and in 20-lead thermally  
enhanced TSSOP packages. Each DAC can operate rail-  
to-rail in external reference mode, or with its full-scale  
voltage set by an integrated reference. Four combinations  
of accuracy (16- and 12-bit), and full-scale voltage (2.5V  
or 4.096V) are available. The LTC2657 is controlled using  
Transfer Function  
The digital-to-analog transfer function is:  
k
VOUT(IDEAL)  
=
2V REFLO + REFLO  
REF  
N
2
where k is the decimal equivalent of the binary DAC input  
code, N is the resolution, and V is the voltage at the  
2
REF  
a 2-wire I C compatible interface.  
REFIN/OUT Pin. The resulting DAC output span is 0V to  
2 • V , as it is necessary to tie REFLO to GND. V is  
Power-On Reset  
REF  
REF  
nominally1.25VforLTC2657-Land2.048VforLTC2657-H,  
in Internal Reference Mode.  
The LTC2657-L/-H clear the output to zero-scale if the  
PORSEL pin is tied to GND when power is first applied,  
makingsysteminitializationconsistentandrepeatable.For  
some applications, downstream circuits are active during  
DAC power-up, and may be sensitive to nonzero outputs  
from the DAC during this time. The LTC2657 contains  
circuitrytoreducethepower-onglitch.Theanalogoutputs  
typicallyriselessthan10mVabovezero-scaleduringpower  
on if the power supply is ramped to 5V in 1ms or more. In  
general,theglitchamplitudedecreasesasthepowersupply  
ramp time is increased. See “Power-On Reset Glitch” in  
the Typical Performance Characteristics section.  
Table 1. Command and Address Codes  
COMMAND*  
C3 C2 C1 C0  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write to Input Register n  
Update (Power Up) DAC Register n  
Write to Input Register n, Update (Power Up) All  
Write to and Update (Power Up) n  
Power Down n  
Power Down Chip (All DACs and Reference)  
Select Internal Reference (Power-Up Reference)  
Select External Reference (Power-Down  
Reference)  
1
1
1
1
No Operation  
Alternatively, if PORSEL is tied to V , The LTC2657-L/-H  
CC  
ADDREꢀꢀ (n)*  
A3 A2 A1 A0  
set the output to mid-scale when power is first applied.  
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
DAC A  
DAC B  
DAC C  
DAC D  
DAC E  
DAC F  
DAC G  
DAC H  
All DACs  
Power ꢀupply ꢀequencing and ꢀtart-Up  
For the LTC2657 family of parts, the internal reference is  
powered-upatstart-upbydefault.Ifanexternalreferenceis  
to be used, the REFCOMP pin (Pin 4 –TSSOP, Pin 2 -QFN )  
must be hardwired to GND. This configuration allows the  
use of an external reference at start-up and converts the  
REFIN/OUTpintoaninput.However,theinternalreference  
will still be ON and draw supply current. In order to use  
an external reference, command 0111b should be used  
to turn the Internal Reference OFF.(See Table1.)  
*Command and address codes not shown are reserved and should not be used.  
ꢀerial Interface  
The voltage at REFIN/OUT (Pin 7 –TSSOP, Pin 5 -QFN)  
should be kept within the range –0.3V ≤ REFIN/OUT  
The LTC2657 communicates with a host using the stan-  
2
dard 2-wire I C interface. The Timing Diagrams (Figures  
≤ V + 0.3V (see Absolute Maximum Ratings). Particular  
1 and 2) show the timing relationship of the signals on  
the bus. The two bus lines, SDA and SCL, must be high  
when the bus is not in use. External pull-up resistors or  
current sources are required on these lines. The value of  
CC  
care should be taken to observe these limits during power  
supply turn-on and turn-off sequences, when the voltage  
at V (Pin 19 –TSSOP, Pin 17 -QFN ) is in transition.  
CC  
2657f  
18  
LTC2657  
OPERATION  
these pull-up resistors is dependent on the power supply  
Table 2. ꢀlave Address Map  
2
and can be obtained from the I C specifications. For an  
CA2  
GND  
GND  
GND  
CA1  
CA0  
A6  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5  
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A±  
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A3  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
I C bus operating in the fast mode, an active pull-up will  
GND  
GND  
be necessary if the bus capacitance is greater than 200pF.  
The LTC2657 is a receive-only (slave) device. The master  
can write to the LTC2657. The LTC2657 does not respond  
to a read command from the master.  
GND FLOAT  
GND  
V
CC  
GND FLOAT GND  
GND FLOAT FLOAT  
GND FLOAT  
V
CC  
The ꢀTART (ꢀ) and ꢀTOP (P) Conditions  
GND  
GND  
GND  
V
V
V
GND  
CC  
CC  
CC  
Whenthebusisnotinuse,bothSCLandSDAmustbehigh.  
A bus master signals the beginning of a communication  
to a slave device by transmitting a START condition (See  
Figure 1). A START condition is generated by transitioning  
SDA from high to low while SCL is high. When the master  
hasnishedcommunicatingwiththeslave,itissuesaSTOP  
condition. A STOP condition is generated by transitioning  
SDA from low to high while SCL is high. The bus is then  
FLOAT  
V
CC  
FLOAT GND  
FLOAT GND FLOAT  
FLOAT GND  
GND  
V
CC  
FLOAT FLOAT GND  
FLOAT FLOAT FLOAT  
FLOAT FLOAT  
V
CC  
2
free for communication with another I C device.  
FLOAT  
FLOAT  
FLOAT  
V
V
V
GND  
CC  
CC  
CC  
FLOAT  
Acknowledge  
V
CC  
The Acknowledge signal is used for handshaking between  
the master and the slave. An Acknowledge (active LOW)  
generated by the slave lets the master know that the  
latest byte of information was received. The Acknowledge  
related clock pulse is generated by the master. The master  
releases the SDA line (HIGH) during the Acknowledge  
clock pulse. The slave-receiver must pull down the SDA  
bus line during the Acknowledge clock pulse so that it  
remains a stable LOW during the HIGH period of this clock  
pulse. The LTC2657 responds to a write by a master in  
this manner. The LTC2657 does not acknowledge a read  
(retains SDA HIGH during the period of the Acknowledge  
clock pulse).  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
GND  
GND FLOAT  
GND  
GND  
V
CC  
FLOAT GND  
FLOAT FLOAT  
FLOAT  
V
CC  
V
V
V
GND  
CC  
CC  
CC  
FLOAT  
V
CC  
GLOBAL ADDRESS  
Inadditiontotheaddressselectedbytheaddresspins, the  
partsalsorespondtoaglobaladdress.Thisaddressallows  
a common write to all LTC2657 parts to be accomplished  
2
Chip Address  
with one 3-byte write transaction on the I C bus. The  
global address is a 7-bit on-chip hardwired address and  
is not selectable by CA0, CA1 and CA2. The addresses  
corresponding to the states of CA0, CA1 and CA2 and  
the global address are shown in Table 2. The maximum  
capacitive load allowed on the address pins (CA0, CA1  
and CA2) is 10pF, as these pins are driven during address  
detection to determine if they are floating.  
The state of CA0, CA1 and CA2 decides the slave address  
of the part. The pins CA0, CA1 and CA2 can be each set  
to any one of three states: V , GND or float. This results  
CC  
in 27 selectable addresses for the part. The slave address  
assignments are shown in Table 2.  
2657f  
19  
LTC2657  
OPERATION  
Write Word Protocol  
combination with the appropriate DAC address, (n). The  
integrated reference is automatically powered down when  
external reference mode is selected using command  
0111b. In addition, all the DAC channels and the integrated  
reference together can be put into power-down mode  
using “Power-Down Chip” command 0101b. For all power-  
down commands the 16-bit data word is ignored, but still  
required in order to complete a full communication cycle.  
The master initiates communication with the LTC2657  
with a START condition and a 7-bit slave address followed  
by the Write bit (W) = 0. The LTC2657 acknowledges by  
pulling the SDA pin low at the 9th clock if the 7-bit slave  
address matches the address of the part (set by CA0, CA1  
and CA2) or the global address. The master then transmits  
three bytes of write data. The LTC2657 acknowledges each  
byte of data by pulling the SDA line low at the 9th clock of  
eachdatabytetransmission.Afterreceivingthreecomplete  
bytesofdata,theLTC2657executesthecommandspecified  
in the 24-bit input word. If more than three data bytes are  
transmitted after a valid 7-bit slave address, the LTC2657  
does not acknowledge the extra bytes of data (SDA is  
high during the 9th clock). The first byte of the input word  
consists of the 4-bit command followed by 4-bit address.  
The next two bytes consist of the 16-bit data word. The  
16-bit data word consists of the 16- or 12-bit input code,  
MSB to LSB, followed by 0 or 4 don’t care bits (LTC2657-  
16 and LTC2657-12, respectively). A typical LTC2657 write  
transaction is shown in Figure 2. The command (C3-C0)  
and address (A3-A0) assignments are shown in Table 1.  
The first four commands in the table consist of write and  
update operations. A write operation loads a 16-bit data  
word from the 32-bit shift register into the input register.  
In an update operation, the data word is copied from the  
inputregistertotheDACregisterandconvertedtoananalog  
voltageattheDACoutput.Theupdateoperationalsopowers  
up the DAC if it had been in power-down mode. The data  
path and registers are shown in the Block Diagram.  
Normal operation resumes by executing any command  
whichincludesaDACupdate,insoftwareasshowninTable  
1 or using the asynchronous LDAC pin. The selected DAC  
is powered up as its voltage output is updated. When a  
DAC which is in a powered-down state is powered up and  
updated,normalsettlingisdelayed.IflessthaneightDACs  
areinapowered-downstatepriortotheupdatecommand,  
the power-up delay time is 12ꢁs. If on the other hand,  
all eight DACs and the integrated reference are powered  
down,thenthemainbiasgenerationcircuitblockhasbeen  
automatically shut down in addition to the individual DAC  
amplifiers and reference inputs. In this case, the power  
up delay time is 14ꢁs. The power up of the integrated  
referencedependsonthecommandthatpowereditdown.  
IfthereferenceispowereddownusingtheSelectExternal  
Referencecommand(0111b),thenitcanonlybepowered  
back up by sending “Select Internal Reference” command  
(0110b). However if the reference was powered down by  
sending “Power Down Chip” command (0101b), then in  
additiontoSelectInternalReferencecommand(0110b),  
any command that powers up the DACs will also power  
up the integrated reference.  
Power-Down Mode  
Reference Modes  
For power-constrained applications, power-down mode  
can be used to reduce the supply current whenever less  
than eight outputs are needed. When in power-down, the  
buffer amplifiers, bias circuits and integrated reference  
circuits are disabled, and draw essentially zero current.  
The DAC outputs are put into a high-impedance state, and  
the output pins are passively pulled to ground through  
individual 80k resistors. Input- and DAC-register contents  
are not disturbed during power-down.  
For applications where an accurate external reference is  
notavailable,theLTC2657hasauser-selectable,integrated  
reference. The LTC2657-L has a 1.25V reference that  
provides a full-scale output of 2.5V. The LTC2657-H has  
a 2.048V reference that provides a full-scale output of  
4.096V. Both references exhibit a typical temperature drift  
of 2ppm/°C. Internal Reference mode can be selected  
by using command 0110b, and is the power-on default.  
A buffer is needed if the internal reference is required to  
drive external circuitry. For reference stability and low  
noise, it is recommended that a 0.1μF capacitor be tied  
Any channel or combination of channels can be put  
into power-down mode by using command 0100b in  
between REFCOMP and GND. In this configuration, the  
2657f  
20  
LTC2657  
OPERATION  
The amplifiers are stable driving capacitive loads of up  
to 1000pF.  
internal reference can drive up to 0.1μF capacitive load  
without any stability problems. In order to ensure stable  
operation,thecapacitiveloadontheREFIN/OUTpinshould  
not exceed the capacitive load on the REFCOMP pin.  
Soard Layout  
TheexcellentloadregulationandDCcrosstalkperformance  
of these devices is achieved in part by keeping “signal”  
and “power” grounds separate.  
TheDACcanalsooperateinExternalReferencemodeusing  
command0111b. Inthismode, theREFIN/OUTpinactsas  
aninput thatsetstheDAC’sreferencevoltage. Theinputis  
high impedance and does not load the external reference  
source. The acceptable voltage range at this pin is 0.5V ≤  
The PC board should have separate areas for the analog  
anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals  
away from sensitive analog signals and facilitates the use  
of separate digital and analog ground planes which have  
minimal capacitive and resistive interaction with each  
other.  
REFIN/OUT≤V /2.Theresultingfull-scaleoutputvoltage  
CC  
is 2 • V  
. For using External Reference at Start-Up,  
REFIN/OUT  
see the Power Supply Sequencing and Start-Up Section.  
Integrated Reference Suffers  
Digital and analog ground planes should be joined at only  
one point, establishing a system star ground as close to  
the device’s ground pin as possible. Ideally, the analog  
ground plane should be located on the component side of  
the board, and should be allowed to run under the part to  
shielditfromnoise.Analoggroundshouldbeacontinuous  
and uninterrupted plane, except for necessary lead pads  
and vias, with signal traces on another layer.  
Each of the eight DACs in LTC2657 has its own integrated  
high performance reference buffer. The buffers have very  
highinputimpedanceanddonotloadthereferencevoltage  
source. These buffers shield the Reference Voltage from  
glitches caused by DAC switching and thus minimize  
DAC-to-DAC Dynamic Crosstalk. See the curve DAC-  
to-DAC Crosstalk (Dynamic) in the Typical Performance  
Characteristics section.  
The GND pin functions as a return path for power supply  
currents in the device and should be con-nected to analog  
ground. The REFLO pin should be connected to system  
star ground. Resistance from the REFLO pin to system  
star ground should be as low as possible.  
Voltage Outputs  
Eachoftheeightrail-to-railamplifierscontainedinLTC2657  
has guaranteed load regulation when sourcing or sinking  
up to 15mA at 5V (7.5mA at 3V).  
Rail-to-Rail Output Considerations  
Load regulation is a measure of the amplifier’s ability to  
maintain the rated voltage accuracy over a wide range of  
load conditions. The measured change in output voltage  
permilliampereofforcedloadcurrentchangeisexpressed  
in LSB/mA.  
Inanyrail-to-railvoltageoutputdevice,theoutputislimited  
to voltages within the supply range.  
Since the analog outputs of the device cannot go below  
ground, they may limit for the lowest codes as shown in  
Figure 3b. Similarly, limiting can occur in External Refer-  
ence mode near full-scale when the REFIN/OUT pin is at  
DC output impedance is equivalent to load regulation, and  
maybederivedfromitbysimplycalculatingachangeinunits  
fromLSB/mAtoOhms.TheamplifiersDCoutputimpedance  
is 0.040Ω when driving a load well away from the rails.  
V /2 . If V  
= V /2 and the DAC full-scale error  
CC  
REFIN/OUT  
CC  
(FSE) is positive, the output for the highest codes limits  
at V as shown in Figure 3c. No full-scale limiting can  
When drawing a load current from either rail, the output  
voltage headroom with respect to that rail is limited by the  
30Ω typical channel resistance of the output devices; e.g.,  
whensinking1mA,theminimumoutputvoltage=30Ω1mA  
=30mV.SeethegraphHeadroomatRailsvsOutputCurrent  
in the Typical Performance Characteristics section.  
CC  
occur if V  
≤ (V – FSE)/2.  
REFIN/OUT  
CC  
Offset and linearity are defined and tested over the region  
of the DAC transfer function where no output limiting can  
occur.  
2657f  
21  
LTC2657  
OPERATION  
2657f  
22  
LTC2657  
OPERATION  
POSITIVE  
FSE  
V
= V  
CC  
REF  
V
= V  
CC  
REF  
OUTPUT  
VOLTAGE  
OUTPUT  
VOLTAGE  
INPUT CODE  
2657 F03  
(c)  
OUTPUT  
VOLTAGE  
0
32, 768  
65, 535  
INPUT CODE  
(a)  
0V  
NEGATIVE  
OFFSET  
INPUT CODE  
(b)  
Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of  
Negative Offset for Codes Near Zero-ꢀcale (c) Effect of Positive Full-ꢀcale Error for Codes Near Full-ꢀcale  
PACKAGE DESCRIPTION  
FE Package  
20-Lead Plastic TꢀꢀOP (±.±mm)  
(Reference LTC DWG # 05-08-1663)  
Exposed Pad Variation CS  
6.40 – 6.60*  
(.252 – .260)  
3.86  
(.152)  
3.86  
(.152)  
20 1918 17 16 15 14 1312 11  
6.60 0.10  
2.74  
(.108)  
4.50 0.10  
6.40  
(.252)  
BSC  
2.74  
(.108)  
SEE NOTE 4  
0.45 0.05  
1.05 0.10  
0.65 BSC  
5
7
8
1
2
3
4
6
9 10  
RECOMMENDED SOLDER PAD LAYOUT  
1.20  
(.047)  
MAX  
4.30 – 4.50*  
(.169 – .177)  
0.25  
REF  
0° – 8°  
0.65  
(.0256)  
BSC  
0.09 – 0.20  
(.0035 – .0079)  
0.50 – 0.75  
(.020 – .030)  
0.05 – 0.15  
(.002 – .006)  
FE20 (CB) TSSOP 0204  
0.195 – 0.30  
(.0077 – .0118)  
TYP  
NOTE:  
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE  
FOR EXPOSED PAD ATTACHMENT  
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH  
SHALL NOT EXCEED 0.150mm (.006") PER SIDE  
MILLIMETERS  
(INCHES)  
2. DIMENSIONS ARE IN  
3. DRAWING NOT TO SCALE  
2657f  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
23  
LTC2657  
PACKAGE DESCRIPTION  
UFD Package  
20-Lead Plastic QFN (±mm × 5mm)  
(Reference LTC DWG # 05-08-1711 Rev B)  
PIN 1 NOTCH  
R = 0.20 OR  
C = 0.35  
0.75 0.05  
1.50 REF  
19  
4.00 0.10  
(2 SIDES)  
R = 0.05 TYP  
20  
0.70 0.05  
0.40 0.10  
PIN 1  
TOP MARK  
(NOTE 6)  
1
2
2.65 0.05  
4.50 0.05  
3.10 0.05  
1.50 REF  
5.00 0.10  
(2 SIDES)  
2.50 REF  
3.65 0.05  
3.65 0.10  
2.65 0.10  
PACKAGE  
OUTLINE  
0.25 0.05  
0.50 BSC  
2.50 REF  
(UFD20) QFN 0506 REV  
B
0.25 0.05  
0.50 BSC  
0.200 REF  
R = 0.115  
TYP  
0.00 – 0.05  
4.10 0.05  
5.50 0.05  
BOTTOM VIEW—EXPOSED PAD  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
NOTE:  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION  
ON THE TOP AND BOTTOM OF PACKAGE  
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
RELATED PARTS  
PART NUMSER  
DEꢀCRIPTION  
COMMENTꢀ  
V = 2.7V to 5.5V, Micropower, Rail-to-Rail Output  
CC  
LTC1664  
Quad 10-Bit V  
DAC in 16-Pin Narrow SSOP  
OUT  
LTC1821  
Single 16-Bit V  
DAC with 1LSB INL, DNL  
Parallel Interface, Precision 16-Bit Settling in 2ꢁs for 10V Step  
OUT  
LTC2600/LTC2610/ Octal 16-/14-/12-Bit V  
LTC2620  
DACs in 16-Lead Narrow SSOP  
250ꢁA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,  
SPI Serial Interface  
OUT  
LTC2601/LTC2611/ Single 16-/14-/12-Bit V  
LTC2621  
DACs in 10-Lead DFN  
300ꢁA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,  
SPI Serial Interface  
OUT  
LTC2602/LTC2612/ Dual 16-/14-/12-Bit V  
LTC2622  
DACs in 8-Lead MSOP  
DACs in 16-Lead SSOP  
300ꢁA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,  
SPI Serial Interface  
OUT  
LTC2604/LTC2614/ Quad 16-/14-/12-Bit V  
LTC2624  
250ꢁA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,  
SPI Serial Interface  
OUT  
OUT  
2
LTC2605/LTC2615/ Octal 16-/14-/12-Bit V  
LTC2625  
DACs with I C Interface  
250ꢁA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output  
270ꢁA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output  
250ꢁA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with  
2
LTC2606/LTC2616/ Single 16-/14-/12-Bit V  
LTC2626  
DACs with I C Interface  
OUT  
2
LTC2609/LTC2619/ Quad 16-/14-/12-Bit V  
LTC2629  
DACs with I C Interface  
OUT  
Separate V Pins for Each DAC  
REF  
2
LTC2637  
Octal I C 12-/10-/8-Bit V  
DACs with 10ppm/°C  
125ꢁA per DAC, 2.7V to 5.5V Supply Range, Internal 1.25V or 2.048V  
OUT  
2
Reference  
Reference, Rail-to-Rail Output, I C Interface  
LTC2641/LTC2642  
Single 16-/14-/12-Bit V  
DACs with 1LSB INL, DNL  
1LSB (Max) INL, DNL, 3mm × 3mm DFN and MSOP Packages,  
120ꢁA Supply Current, SPI Interface  
OUT  
LTC2704  
LTC2754  
LTC2656  
Quad 16-/14-/12-Bit V  
DACs with 2LSB INL, 1LSB DNL Software Programmable Output Ranges Up to 10V, SPI Interface  
DACs with 1LSB INL, 1LSB DNL Software Programmable Output Ranges Up to 10V, SPI Interface  
OUT  
Quad 16-/14-/12-Bit I  
OUT  
Octal 16-/12-Bit V  
DACs with 4 LSB INL, 1 LSB DNL  
4mm × 5mm QFN-20, TSSOP-20 Packages, SPI Packages, Internal  
10ppm/°C (Max) Reference  
OUT  
2657f  
LT 0909 • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
24  
© LINEAR TECHNOLOGY CORPORATION 2009  
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  
配单直通车
LTC2657CFE-L12#PBF产品参数
型号:LTC2657CFE-L12#PBF
Brand Name:Linear Technology
是否Rohs认证: 符合
生命周期:Transferred
零件包装代码:TSSOP
包装说明:HTSSOP, TSSOP20,.25
针数:20
制造商包装代码:FE
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.08
最大模拟输出电压:2.5 V
最小模拟输出电压:
转换器类型:D/A CONVERTER
输入位码:BINARY
输入格式:SERIAL
JESD-30 代码:R-PDSO-G20
JESD-609代码:e3
长度:6.5 mm
最大线性误差 (EL):0.0244%
湿度敏感等级:1
位数:12
功能数量:1
端子数量:20
最高工作温度:70 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装代码:HTSSOP
封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:3/5 V
认证状态:Not Qualified
座面最大高度:1.2 mm
标称安定时间 (tstl):3.9 µs
子类别:Other Converters
最大压摆率:4.25 mA
标称供电电压:3 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
宽度:4.4 mm
Base Number Matches:1
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