LTC4100
U
OPERATIO
Overview (Refer to Block Diagram)
comparator IREV, or the beginning of the next cycle.
The oscillator uses the equation,
The LTC4100 is composed of a battery charger section, a
charger controller, a 10-bit DAC to control charger cur-
rent,an11-bitDACtocontrolchargervoltage,aSafetySignal
decoder, limit decoder and an SMBus controller block. If
no battery is present, the SafetySignal decoder indicates a
RES_ORconditionandchargingisdisabledbythecharger
controller (CHGEN = Low). Charging will also be disabled
if DCDIV is low, or the SafetySignal is decoded as
RES_HOT. If a battery is inserted and AC power is con-
nected, the battery will be charged with an 80mA “wake-
up” current. The wake-up current is discontinued after
tTIMEOUT if the SafetySignal is decoded as RES_UR or
RES_C0LD, and the battery or host doesn’t transmit
charging commands.
(VDCIN – VBAT
)
tOFF
=
(VDCIN • fOSC
)
to set the bottom MOSFET on time. The result is quasi-
constant frequency operation: the converter frequency
remains nearly constant over a wide range of output
voltages. This activity is diagrammed in Figure 3.
OFF
TGATE
ON
ON
t
BGATE
OFF
OFF
TRIP POINT SET
BY I VOLTAGE
The SMBus interface and control block receives
ChargingCurrent() and ChargingVoltage() commands via
the SMBus. If ChargingCurrent() and ChargingVoltage()
command pairs are received within a tTIMEOUT interval, the
values are stored in the current and voltage DACs and the
charger controller asserts the CHGEN line if the decoded
SafetySignal value will allow charging to commence.
ChargingCurrent()andChargingVoltage()valuesarecom-
pared against limits programmed by the limit decoder
block; if the commands exceed the programmed limits
these limits are substituted and overrange flags are set.
TH
INDUCTOR
CURRENT
4100 F01
Figure 3.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by the IDAC at the IDC pin and adjusts
The charger controller will assert SMBALERT whenever a
status change is detected, namely: AC_PRESENT,
BATTERY_PRESENT, ALARM_INHIBITED, or VDD
power-fail. The host may query the charger, via the
SMBus,toobtainChargerStatus()information.SMBALERT
will be deasserted upon a successful read of
ChargerStatus() or a successful Alert Response
Address (ARA) request.
ITH for the desired voltage across RSENSE
.
The voltage at BAT is divided down by an internal resistor
divider set by the VDAC and is used by error amp EA to
decrease ITH if the divider voltage is above the 1.19V
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH
voltage to reduce charging current.
Battery Charger Controller
The LTC4100 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator ICMP resets the SR latch. While
the top MOSFET is off, the bottom MOSFET is turned
on until either the inductor current trips the current
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries that "load dump" themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
sn4100 4100is
8