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LTC5586

6GHz High Linearity

I/Q Demodulator with

Wideband IF Amplifier

FeaTures

DescripTion

n

300MHz to 6GHz Operating Frequency

The LTC^®5586 is a direct conversion quadrature demod-

ulator optimized for high linearity zero-IF and low IF

receiver applications in the 300MHz to 6GHz frequency

range. The very wide IF bandwidth of more than 1GHz

makes the LTC5586 particularly suited for demodulation

of very wideband signals, especially in digital predistor-

tion (DPD) applications. The outstanding dynamic range

of the LTC5586 makes the device suitable for demanding

infrastructure direct conversion applications. Proprietary

technology inside the LTC5586 provides the capability

to optimize OIP2 to 80dBm, and achieve image rejection

better than 60dB. The DC offset control function allows

nulling of the DC offset at the A/D converter input, thereby

optimizing the dynamic range of true zero-IF receivers

that use DC coupled IF signal paths. The wideband RF

and LO input ports make it possible to cover all the major

wireless infrastructure frequency bands using a single

device. The IF outputs of the LTC5586 are designed to

interface directly with most common A/D converter input

interfaces. The high OIP3 and high conversion gain of the

device eliminate the need for additional amplifiers in the

IF signal path.

n

Wide IF Bandwidth: DC to 1GHz (–1dB Bandwidth)

n

High Mixer IIP3: 30dBm at 1.9GHz

n

High Total OIP3: 40dBm at 1.9GHz

n

High Total OIP2: 74dBm at 1.9GHz

n

User Adjustable OIP2 to 80dBm

n

User Adjustable Image Rejection to 60dB

n

User Adjustable DC Offset Null

Serial Interface

n

Power Conversion Gain: 7.7dB at 1.9GHz

n

31dB RF Attenuator with 1dB Step Size

n

RF Switch with 40dB Isolation at 1.9GHz

n

Single-Ended RF Inputs with On-Chip Transformer

n

IF Amplifier Gain Adjustable in 8 Steps

n

Operating Temperature Range (T ): –40°C to 105°C

C

n

32-Lead 5mm × 5mm QFN Package

applicaTions

n

4G and 5G Base Station Receivers

n

Wideband DPD Receivers

n

Point-To-Point Broadband Radios

n

High Linearity Direct Conversion I/Q Receivers

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog

Devices, Inc. All other trademarks are the property of their respective owners.

n

Image Rejection Receivers

Typical applicaTion

Gain, OIP3 and OIP2 vs Temperature (T_C)

(Unoptimized)

Dual Band Transmitter with DPD Receiver

90

OIP2

80

RF

1

PA

1

70

60

50

LTC5586

IFIP

OIP3

ADC

40

30

20

10

0

RFA

IFIM

8 STEPS

RFB

0º

GAIN

f

LO

90º

RFSW

8 STEPS

IFQP

ATTEN

0dB – 31dB

-10

0

1

2

3

4

5

6

SPI

ADC

RF FREQUENCY (GHz)

IFQM

5586 G01

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

RF

2

PA

2

5586 TA01

5586fa

1

For more information www.linear.com/LTC5586

LTC5586

absoluTe MaxiMuM raTings

pin conFiguraTion

TOP VIEW

(Note 1)

VCC, VCCN Supply Voltage (Note 21) ....... –0.3V to 5.5V

OVDD, SDO Voltage (Note 18)................... –0.3V to 3.8V

RFA, RFB DC Voltage ...................................1.5V to 2.0V

LOP, LOM DC Voltage ..................................2.1V to 2.8V

IFIM, IFIP, IFQP, IFQM DC Voltage............. –0.3V to 3.5V

AIM, AIP, AQM, AQP

32 31 30 29 28 27 26 25

GND

RFA

1

2

3

4

5

6

7

8

24 OVDD

SCK

SDI

23

22

TEMP

RFSW

VCCN

VCM

RFB

21 SDO

20 LOM

19 LOP

33

GND

DC Voltage........................... V – 1.7V to V – 1.2V

CC

MIM, MIP, MQM, MQP

18

17

VCC

CSB

DC Voltage........................... V – 1.7V to V – 1.2V

CC

GND

Voltage on Any Other Pin.......................... –0.3V to 5.5V

LOP, LOM, RFA, RFB Input Power (Note 17) ......+20dBm

Output Short Circuit Duration (Notes 14, 17)... Indefinite

9

10 11 12 13 14 15 16

UH PACKAGE

Maximum Junction Temperature (T

)............. 150°C

JMAX

32-LEAD (5mm × 5mm) PLASTIC QFN

Case Operating Temperature Range (T )–40°C to 105°C

T

JMAX

= 150°C, θ = 7.7°C/W

C

JC

EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB

Storage Temperature Range .................. –65°C to 150°C

orDer inForMaTion ^{http://www.linear.com/product/LTC5586#orderinfo}

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC5586IUH#PBF

LTC5586IUH#TRPBF

5586

32-Lead (5mm x 5mm) Plastic QFN

–40°C to 105°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

5586fa

2

For more information www.linear.com/LTC5586

LTC5586

elecTrical characTerisTics ^T_C^{= 25°C, V}_CC= V_CCN= 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V,

VCM = 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values unless otherwise noted.

(Notes 2, 3, 6, 9, 19, 22)

SYMBOL

PARAMETER

CONDITIONS

(Note 12)

MIN

TYP

MAX

UNITS

GHz

f

RF Input Frequency Range

LO Input Frequency Range

RF Input Return Loss

0.3 to 6.0

RF(RANGE)

LO(RANGE)

(Note 12)

GHz

RL

f

= 300MHz to 500MHz (Note 5)

= 500MHz to 6.0GHz

>10

dB

RF

RL

LO Input Return Loss

LO Input Power Range

f

= 300MHz to 6.0GHz

>10

dB

LO

P

(Note 12)

–6 to 12

dBm

LO(RANGE)

G

Maximum Power Conversion Gain

ATT = 0x00, AMPG = 0x06,

LOAD

f

RF

f

RF

f

RF

f

RF

f

RF

f

RF

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

7.4

9.2

7.7

7.1

4.3

0.7

dB

P(MAX)

R

= 100Ω Differential (Note 8)

G

Power Conversion Gain at Maximum

Attenuation. ATT = 0x1F, AMPG = 0x06,

LOAD

f

RF

f

RF

f

RF

f

RF

f

RF

f

RF

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

–23.3

–21.3

–21.8

–23.5

–24.0

–23.9

dB

P(MIN)

R

= 100Ω, Differential (Note 8)

Attenuation Step Size

Attenuation Step Accuracy

RFA, RFB Gain Error

1.0

0.2

dB

ns

0.05

100

RFA, RFB Switching Time

RFA, RFB Isolation

AB

NF

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

49

48

40

42

38

25

dB

ISO

RF

Noise Figure, Double Side Band (Note 4)

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

19.0

17.8

19.5

21.1

23.2

31.0

dB

RF

NF

Noise Figure Under Blocking Conditions

f

RF

f

RF

f

RF

f

RF

f

RF

f

RF

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

19.7

18.9

20.8

22.5

24.8

30.2

dB

BLOCKING

Double Side Band, P ,

= 1.5dBm

IF BLOCKER

(Note 7)

OIP3

OIP2

Output 3rd Order Intercept

Unadjusted/Adjusted

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

41/44

42/43

40/42

38/40

35/36

32/33

dBm

RF

Output 2nd Order Intercept

Unadjusted/Adjusted

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

75/80

74/80

65/80

60/70

49/56

dBm

RF

5586fa

3

For more information www.linear.com/LTC5586

LTC5586

elecTrical characTerisTics ^T_C^{= 25°C, V}_CC= V_CCN= 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V,

VCM = 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values unless otherwise noted.

(Notes 2, 3, 6, 9, 19, 22)

SYMBOL

IIP3

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input 3rd Order Intercept Without Amplifier

Unadjusted

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

31

29

30

32

dBm

DEMOD

RF

OIP3

HD2

HD3

Output 3rd Order Intercept, Amplifier Only

(Note 15)

f

= 10MHz

42

41

38

37

35

30

dBm

AMP

IF

= 100MHz

= 200MHz

= 300MHz

= 500MHz

= 1000MHz

2nd Order Harmonic Distortion

Unadjusted/Adjusted

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

–63/–85

–62/–90

–63/–90

–61/–90

–64/–85

–52/–74

dBc

RF

3rd Order Harmonic Distortion

Unadjusted/Adjusted

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

–83/–84

–80/–81

–80/–80

–79/–78

–69/–73

dBc

RF

P1dB

Output 1dB Compression Point

DC Offset, Unadjusted (Note 13)

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

10.5

13

dBm

RF

13

12.5

DC

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

20

21

22

25

35

45

mV

OFFSET

RF

DC

∆G

DC Offset Adjustment Range

DC Offset Step Size

DCOI, DCOQ = 0x00 to 0xFF

–75 to 75

640

mV

µV

OFF(RANGE)

OFF(STEP)

I/Q Gain Mismatch, Unadjusted

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

0.04

0.05

0.06

0.07

0.10

dB

RF

∆G

I/Q Gain Mismatch Adjustment Range

I/Q Gain Mismatch Adjustment Step Size

I/Q Phase Mismatch, Unadjusted

GERR = 0x00 to 0x3F

–0.5 to 0.5

0.016

dB

(RANGE)

∆G(STEP)

∆φ

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

0.4

1.1

2.3

3.2

0.3

Deg

RF

∆φ

(RANGE)

I/Q Phase Mismatch Adjustment Range

PHA = 0x000 to 0x1FF

–2.5 to 2.5

Deg

5586fa

4

For more information www.linear.com/LTC5586

LTC5586

elecTrical characTerisTics ^T_C^{= 25°C, V}_CC= V_CCN= 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V,

VCM = 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values unless otherwise noted.

(Notes 2, 3, 6, 9, 19, 22)

SYMBOL

∆φ

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I/Q Phase Mismatch Adjustment Step Size

0.05

Deg

(STEP)

IRR

Image Rejection Ratio

Unadjusted/Adjusted

(Note 10)

f

= 400MHz

= 700MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

51/68

44/70

45/68

39/69

33/70

39/70

dB

RF

LR

RL

LO to RF Leakage

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

–67

–63

–56

–55

–45

–47

dBm

LEAK

LO

RF to LO Isolation

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

59

65

66

62

57

52

dB

ISO

RF

RI

RF to IF Isolation (Note 16)

LO to IF Leakage (Note 16)

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

70

65

50

53

48

47

dB

ISO

RF

LI

f

= 400MHz

= 900MHz

= 1900MHz

= 2600MHz

= 3500MHz

= 5800MHz

–37

–36

–34

–33

–42

–36

dBm

LEAK

LO

Power Supply and Other Parameters

V

, V

Supply Voltage

4.75

430

5.0

440

5.25

470

V

mA

µA

CC CCN

I

Supply Current

CC

VCCN

Supply Current to VCCN Pin

Digital I/O Supply Voltage

RFSW Input High Voltage (On)

RFSW Input Low Voltage (Off)

RFSW Pin Input Current

700

OV

1.2 to 3.3

V

DD

V

0.7 • OV

V

DH

DD

0.3 • OV

V

DL

DD

I

RFSW = 3.3V

1

μA

RFSW

V

TEMP Diode Bias Voltage

TEMP Diode Temperature Slope

Mixer Output Impedance

I

= 100μA into TEMP pin

0.774

V

TEMP

–1.52

mV/°C

Ω||pF

V

Z

Differential

100||0.6

3.6

MIX(OUT)

V

Mixer Output DC Voltage

Common-Mode

Differential

MIX(OUT)

AMP(IN)

Z

Amplifier Input Impedance

Amplifier DC Input Voltage

Amplifier Output Impedance

Amplifier DC Output Short Circuit Current

VCM Pin Voltage Range (Notes 11, 12)

200||0.2

3.0 to 4.0

4||0.5

Ω||pF

V

Common-Mode

Differential

AMP(IN)

AMP(OUT)

AMP(SC)

Z

kΩ||pF

mA

V

I

IFIP = IFIM = IFQP = IFQM = 0V

100

V

0.5 to 2.0

CM(RANGE)

5586fa

5

For more information www.linear.com/LTC5586

LTC5586

elecTrical characTerisTics ^T_C^{= 25°C, V}_CC= V_CCN= 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V,

VCM = 0.9V, P_IF= 1.5dBm (–1.5dBm/tone for 2-tone tests), P_LO= 6dBm, all registers at default values unless otherwise noted.

(Notes 2, 3, 6, 9, 19, 22)

SYMBOL

BW

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

IF Output Bandwidth

–1dB Corner Frequency (Note 20)

1.0

GHz

IF

Serial Interface Pins

V

High Level Input Voltage

Low Level Input Voltage

Input Hysteresis Voltage

Input Current

CSB, SDI, SCK

0.7 • OV

V

IH

DD

CSB, SDI, SCK

0.3 • OV

30

IL

DD

CSB, SDI, SCK

250

mV

μA

V

IHYS

IN(SER)

I

CSB, SDI, SCK (Note 17)

SDO, 10mA Current Sink

SDO, 10mA Current Source

V

High Level Output Voltage

Low Level Output Voltage

0.7 • OV

OH

DD

0.3 • OV

V

OL

DD

Serial Interface Timing

t

SCK High Time

25

10

6

ns

CKH

CKL

CSS

CSH

DS

SCK Low Time

CSB Setup Time

CSB High Time

SDI to SCK Setup Time

SDI to SCK Hold Time

SCK to SDO Time

6

DH

To V /V /Hi-Z with 30pF Load

16

DO

IH IL

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Rating condition for extended periods may affect device reliability and

Note 9: Input P adjusted so that P = –1.5dBm/tone at the amplifier

RF IF

output. RF tone spacing set at 4MHz with high-side LO, f = f + 30MHz.

LO

RF

Note 10: Image rejection is measured at f = 12MHz and calculated from

IF

lifetime. The voltage on all pins should not exceed V + 0.3V or be less than

CC

the measured gain error and phase error.

Note 11: If the VCM pin is left floating, it will self bias to a nominal 0.9V.

Note 12: This is the recommended operating range, operation outside the

listed range is possible with degraded performance to some parameters.

Note 13: DC offset measured differentially between IFIP and IFIM and

between IFQP and IFQM. The reported value is the mean of the absolute

values of the characterization data distribution.

Note 14: IF outputs shorted to ground.

Note 15: IF tone spacing set at 1MHz.

–0.3V, otherwise damage to the ESD diodes may occur.

Note 2: Tests are performed with the test circuit of Figure 1.

Note 3: The LTC5586 is guaranteed to be functional over the –40°C to

105°C case temperature operating range.

Note 4: DSB noise figure is measured at the baseband frequency of 15MHz

with a small-signal noise source without any filtering on the RF input and

no other RF signal applied.

Note 5: A 4.7pF shunt capacitor is used on the RF inputs for 300MHz to

500MHz. 0.3pF is used for 500MHz to 6GHz.

Note 16: Worst case leakage or isolation measured to each IF single-ended

port.

Note 17: Guaranteed by design characterization, not tested in production.

Note 6: The differential amplifier outputs (IFIP, IFIM and IFQP, IFQM) are

combined using a 180° combiner.

Note 7: Noise figure under blocking conditions (NF

) is measured

BLOCKING

Note 18: The voltage on the OVDD pin must never exceed V + 0.3V,

CC

at an output frequency of 60MHz with RF input signal at f + 1MHz. Both

LO

otherwise damage to the ESD diodes may occur.

Note 19: Refer to Appendix for register definition and default values.

Note 20: Mixer outputs directly connected to amplifier inputs. Bandwidth

measured on single amplifier output, I or Q.

RF and LO input signals are appropriately filtered, as well as the baseband

output.

Note 8: Power conversion gain is defined from the RFA (or RFB) input

to the I or Q output. Power conversion gain is measured with a 100Ω

differential load impedance on the I and Q outputs. Any losses due to IF

combiner and spectrum analyzer termination have been de-embedded.

Note 21: V should be ramped up slower than 5V/ms to prevent damage.

CC

Note 22: P measured at amplifier differential outputs.

IF

5586fa

6

For more information www.linear.com/LTC5586

LTC5586

V_CC= V_CCN= 5V, T_C= 25°C, P_LO= 6dBm, HSLO, RF

Typical perForMance characTerisTics

tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180°

combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz

interstage filter.

TEMP Diode Voltage

vs Temperature (T_C)

Noise Figure and Conversion

Gain vs Temperature (T_C)

Supply Current vs Supply Voltage

500

490

480

470

460

450

440

430

420

410

400

1.0

0.9

0.8

0.7

0.6

0.5

40

35

30

25

20

15

10

5

T

= 105°C

= 85°C

= 25°C

= –40°C

105°C

85°C

C

NF

25°C

–40°C

GAIN

0

–5

–10

4.75

5.00

SUPPLY VOLTAGE (V)

5.25

-40 -20

0

20 40 60 80 100 120

0

1

2

3

4

5

6

TEMPERATURE (°C)

RF FREQUENCY (GHz)

5586 G02

5586 G03

5586 G04

Noise Figure and Conversion

Gain vs LO Power

Gain vs IF Frequency for Various

Fixed LO Frequencies

Conversion Gain vs ATT Setting

45

40

35

30

25

20

15

10

5

10

5

20

15

HSLO

–6dBm

ATT = 0

0dBm

6dBm

12dBm

NF

10

0

5

–5

0

–10

–15

–20

–25

–30

–5

–10

–15

–20

–25

–30

I, 400MHz

I, 900MHz

I, 1900MHz

I, 2600MHz

I, 3500MHz

I, 5800MHz

Q, 400MHz

Q, 900MHz

Q, 1900MHz

Q, 2600MHz

Q, 3500MHz

Q, 5800MHz

GAIN

0

ATT = 31

–5

–10

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

RF FREQUENCY (GHz)

IF FREQUENCY (GHz)

5586 G05

5586 G06

5586 G07

Gain vs IF Frequency for Various

Fixed LO Frequencies

Gain vs AMPG Register Value

Noise Figure vs ATT Setting

20

15

10

5

60

55

50

45

40

35

30

25

20

15

LSLO

f

= 1900MHz

RF

ATT = 31

10

5

0

–5

0

–10

–15

–20

–25

–30

–5

–10

–15

I, 400MHz

I, 900MHz

I, 1900MHz

I, 2600MHz

I, 3500MHz

Q, 400MHz

Q, 900MHz

Q, 1900MHz

Q, 2600MHz

Q, 3500MHz

0

1

2

3

4

5

6

7

ATT = 0

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0

1

2

3

4

5

6

IF FREQUENCY (GHz)

RF FREQUENCY (GHz)

5586 G08

5586 G09

5586 G10

5586fa

7

For more information www.linear.com/LTC5586

LTC5586

V

_CC= V_CCN= 5V, T_C= 25°C, P_LO= 6dBm, HSLO, RF

Typical perForMance characTerisTics

tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180°

combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz

interstage filter.

RFA to RFB Isolation vs RFSW

Output Referred P1dB

OIP3 vs IF Frequency

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

18

17

16

15

14

13

12

11

10

9

50

45

40

35

30

25

20

15

RFSW = 1

RFSW = 0

RFA

RFB

I, 30MHz

Q, 30MHz

I, 100MHz

I, 200MHz

I, 300MHz

I, 500MHz

Q, 100MHz

Q, 200MHz

Q, 300MHz

Q, 500MHz

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

0

1

2

3

4

5

6

RF FREQUENCY (GHz)

5586 G11

5586 G12

5586 G13

OIP3 vs IF Frequency for LSLO

OIP3 vs Temperature (T_C)

OIP3 vs Supply Voltage (V_CC)

50

45

40

35

30

25

20

15

50

45

40

35

30

25

20

15

50

45

40

35

30

25

20

15

LSLO

I, 30MHz

Q, 30MHz

I, 100MHz

I, 200MHz

I, 300MHz

I, 500MHz

Q, 100MHz

Q, 200MHz

Q, 300MHz

Q, 500MHz

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

I, 4.75V

I, 5V

I, 5.25V

Q, 4.75V

Q, 5V

Q, 5.25V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

RF FREQUENCY (GHz)

5586 G14

5586 G15

5586 G16

Optimized OIP3

vs Temperature (T_C)

OIP3 vs LO Power

OIP3 vs IF Tone Power

50

45

40

35

30

25

20

15

50

45

40

35

30

25

20

15

50

45

40

35

30

25

20

15

OPTIMIZED AT 25°C

I, –6dBm

I, 0dBm

I, 6dBm

I, 12dBm

Q, –6dBm

Q, 0dBm

Q, 6dBm

Q, 12dBm

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

I, –4.5dBm

I, –1.5dBm

I, 1.5dBm

Q, –4.5dBm

Q, –1.5dBm

Q, 1.5dBm

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

RF FREQUENCY (GHz)

5586 G17

5586 G18

5586 G19

5586fa

8

For more information www.linear.com/LTC5586

LTC5586

V

_CC= V_CCN= 5V, T_C= 25°C, P_LO= 6dBm, HSLO, RF

Typical perForMance characTerisTics

tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180°

combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz

interstage filter.

OIP3 vs Temperature (T_C) and

Register Value, I-Channel

OIP3 vs Temperature (T_C) and

Register Value, Q-Channel

OIP3 vs IP3CC Register Value

50

45

40

35

30

25

20

15

50

45

40

35

30

25

20

15

50

45

40

35

30

25

20

15

I-CHANNEL

f_RF= 1900MHz

Q-CHANNEL

f_RF= 1900MHz

I, 0

I, 1

I, 2

I, 3

Q, 0

Q, 1

Q, 2

Q, 3

IM3IY, 105°C

IM3IY, 85°C

IM3IY, 25°C

IM3IY, –40°C

IM3IX, 105°C

IM3IX, 85°C

IM3IX, 25°C

IM3IX, –40°C

IM3QY, 105°C

IM3QY, 85°C

IM3QY, 25°C

IM3QY, –40°C

IM3QX, 105°C

IM3QX, 85°C

IM3QX, 25°C

IM3QX, –40°C

0

32 64 96 128 160 192 224 256

0

32 64 96 128 160 192 224 256

0

1

2

3

4

5

6

REGISTER VALUE (INTEGER)

RF FREQUENCY (GHz)

5586 G20

5586 G21

5586 G22

OIP3 vs IP3IC Register Value

OIP3 vs LVCM Register Value

OIP2 vs Temperature (T_C)

50

45

40

35

30

25

20

15

50

45

40

35

30

25

20

15

100

90

80

70

60

50

40

30

20

10

0

I, 0

I, 1

I, 2

I, 3

I, 4

I, 5

I, 6

I, 7

Q, 0

Q, 1

Q, 2

Q, 3

Q, 4

Q, 5

Q, 6

Q, 7

I, 0

I, 1

I, 2

I, 3

I, 4

I, 5

I, 6

I, 7

Q, 0

Q, 1

Q, 2

Q, 3

Q, 4

Q, 5

Q, 6

Q, 7

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

RF FREQUENCY (GHz)

5586 G23

5586 G24

5586 G25

Optimized OIP2

vs Temperature (T_C)

OIP2 vs Temperature (T_C) and

Register Value, I-Channel

OIP2 vs LO Power

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

OPTIMIZED AT 25°C

I-CHANNEL

f_RF= 1900MHz

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

IM2IX, 105°C

I, –6dBm

I, 0dBm

I, 6dBm

I, 12dBm

Q, –6dBm

Q, 0dBm

Q, 6dBm

Q, 12dBm

IM2IX, 85°C

IM2IX, 25°C

IM2IX, –40°C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

32 64 96 128 160 192 224 256

RF FREQUENCY (GHz)

REGISTER VALUE (INTEGER)

5586 G26

5586 G27

5586 G28

5586fa

9

For more information www.linear.com/LTC5586

LTC5586

V

_CC= V_CCN= 5V, T_C= 25°C, P_LO= 6dBm, HSLO, RF

Typical perForMance characTerisTics

tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180°

combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz

interstage filter.

OIP2 vs Temperature (T_C)

and Register Value, Q-Channel

HD2 vs Temperature (T_C)

HD2 vs LO Power

100

90

80

70

60

50

40

30

20

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Q-CHANNEL

f_RF= 1900MHz

I, –6dBm

I, 0dBm

I, 6dBm

I, 12dBm

Q, –6dBm

Q, 0dBm

Q, 6dBm

Q, 12dBm

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

IM2QX, 105°C

IM2QX, 85°C

IM2QX, 25°C

IM2QX, –40°C

0

32 64 96 128 160 192 224 256

0

1

2

3

4

5

6

0

1

2

3

4

5

6

REGISTER VALUE (INTEGER)

RF FREQUENCY (GHz)

5586 G29

5586 G30

5586 G31

Optimized HD2

vs Temperature (T_C)

HD2 vs Temperature (T_C)

and Register Value, I-Channel

HD2 vs Temperature (T_C)

and Register Value, Q-Channel

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Q-CHANNEL

f_RF= 1900MHz

I-CHANNEL

f_RF= 1900MHz

OPTIMIZED AT 25°C

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

HD2QY, 105°C

HD2QY, 85°C

HD2QY, 25°C

HD2QY, –40°C

HD2QX, 105°C

HD2QX, 85°C

HD2QX, 25°C

HD2QX, –40°C

HD2IY, 105°C

HD2IY, 85°C

HD2IY, 25°C

HD2IY, –40°C

HD2IX, 105°C

HD2IX, 85°C

HD2IX, 25°C

HD2IX, –40°C

0

1

2

3

4

5

6

0

32 64 96 128 160 192 224 256

0

32 64 96 128 160 192 224 256

RF FREQUENCY (GHz)

REGISTER VALUE (INTEGER)

5586 G32

5586 G33

5586 G34

Optimized HD3

vs Temperature (T_C)

HD3 vs Temperature (T_C)

HD3 vs LO Power

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

OPTIMIZED AT 25°C

I, –6dBm

I, 0dBm

I, 6dBm

I, 12dBm

Q, –6dBm

Q, 0dBm

Q, 6dBm

Q, 12dBm

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

RF FREQUENCY (GHz)

5586 G35

5586 G36

5586 G37

5586fa

10

For more information www.linear.com/LTC5586

LTC5586

V

_CC= V_CCN= 5V, T_C= 25°C, P_LO= 6dBm, HSLO, RF

Typical perForMance characTerisTics

tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180°

combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz

interstage filter.

HD3 vs Temperature (T_C)

and Register Value, I-Channel

HD3 vs Temperature (T_C)

and Register Value, Q-Channel

Image Rejection

vs Temperature (T_C)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

105°C

85°C

HD3IY, 105°C

HD3IY, 85°C

HD3IY, 25°C

HD3IY, –40°C

HD3IX, 105°C

HD3IX, 85°C

HD3IX, 25°C

HD3IX, –40°C

HD3QY, 105°C

HD3QY, 85°C

HD3QY, 25°C

HD3QY, –40°C

HD3QX, 105°C

HD3QX, 85°C

HD3QX, 25°C

HD3QX, –40°C

25°C

–40°C

I-CHANNEL

f_RF= 1900MHz

Q-CHANNEL

f_RF= 1900MHz

0

32 64 96 128 160 192 224 256

0

32 64 96 128 160 192 224 256

0

1

2

3

4

5

6

REGISTER VALUE (INTEGER)

LO FREQUENCY (GHz)

5586 G38

5586 G39

5586 G40

Optimized Image Rejection

vs Temperature (T_C)

Gain Error vs Temperature (T_C)

and GERR Register Value

Phase Error vs Temperature (T_C)

and PHA Register Value

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1.0

0.8

3

2

105°C

85°C

OPTIMIZED AT 25°C

f_RF= 1900MHz

25°C

0.6

–40°C

1

0.4

0

0.2

0

–1

–2

–3

–4

–5

–0.2

–0.4

–0.6

–0.8

–1.0

105°C

85°C

25°C

–40°C

85°C

25°C

–40°C

0

1

2

3

4

5

6

0

8

16 24 32 40 48 56 64

0

64 128 192 256 320 384 448 512

RF FREQUENCY (GHz)

REGISTER VALUE (INTEGER)

5586 G41

5586 G43

5586 G42

Optimized DC Offset vs

Temperature (T_C)

DC Offset vs Temperature (T_C)

DC Offset vs LO Power

50

45

40

35

30

25

20

15

10

5

30

25

20

15

105°C

85°C

25°C

–40°C

OPTIMIZED AT 25°C

20

15

10

5

0

–5

–10

–15

–20

–25

–30

0

–10

–15

–20

105°C

85°C

25°C

–40°C

–6dBm

0dBm

6dBm

12dBm

–5

–10

–15

–20

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LO FREQUENCY (GHz)

5586 G44

5586 G45

5586 G46

5586fa

11

For more information www.linear.com/LTC5586

LTC5586

V

_CC= V_CCN= 5V, T_C= 25°C, P_LO= 6dBm, HSLO, RF

Typical perForMance characTerisTics

tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180°

combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz

interstage filter.

DC Offset vs Temperature (T_C)

and Register Value

Blocking Noise Figure

vs LO Power

RFSW Transient Response

100

80

40

35

30

25

20

15

10

2.0

1.5

1.0

0.5

0

20

15

10

5

f_LO= 1900MHz

f_{RF, BLOCK}= 1960MHz

f_{IF, NOISE}= 30MHz

f_RF= 2.1GHz

f_LO= 2.102GHz

RFSW

IFIP

–6dBm

0dBm

IFIM

6dBm

60

12dBm

40

20

0

–20

–40

–60

–80

–100

105°C

85°C

25°C

–40°C

0

32 64 96 128 160 192 224 256

–30

–25

–20

–15

–10

–5

0

1

2

3

4

5

6

7

8

9

10

DC OFFSET DAC (INTEGER)

RF INPUT POWER (dBm)

TIME (µs)

5586 G47

5586 G48

5586 G49

Gain, IIP3 and IIP2 for Mixer Only

RF to LO Isolation

LO to RF Leakage

90

80

70

60

50

40

30

20

10

0

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

RFA

RFB

RFA

RFB

I

Q

IIP2

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

IIP3

GAIN

–10

–20

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

RF FREQUENCY (GHz)

LO FREQUENCY (GHz)

5586 G50

5586 G51

5586 G52

RF to IF Isolation

LO to IF Isolation

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

T_C= 25°C

RFSW = 1

RFA INPUT

T

= 25°C

IFQP

IFQM

IFIM

IFIP

IFQP

IFQM

IFIM

IFIP

C

BAND = 1

CF = 0

LF1 = 0

CF2 = 0

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

RF FREQUENCY (GHz)

LO FREQUENCY (GHz)

5586 G53

5586 G54

5586fa

12

For more information www.linear.com/LTC5586

LTC5586

V

_CC= V_CCN= 5V, T_C= 25°C, P_LO= 6dBm, HSLO, RF

Typical perForMance characTerisTics

tone spacing = 4MHz, f_IF= 30MHz, P_IF= –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180°

combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz

interstage filter.

OIP3 Distribution

vs Temperature (T_C)

OIP2 Distribution

vs Temperature (T_C)

Conversion Gain Distribution

vs Temperature (T_C)

100

80

60

40

20

0

100

80

60

40

20

0

100

80

60

40

20

0

f_RF= 2GHz

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

105°C

85°C

25°C

–40°C

30

32

34

36

38

40

42

30

40

50

60

70

80

90 100

5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0

OIP3 (dBm)

OIP2 (dBm)

GAIN (dB)

5586 G55

5586 G56

5586 G57

Noise Figure Distribution

vs Temperature (T_C)

Gain Error Distribution

vs Temperature (T_C)

Phase Error Distribution

vs Temperature (T_C)

100

80

60

40

20

0

100

80

60

40

20

0

100

f_RF= 2GHz

80

60

40

20

0

I, 105°C

I, 85°C

I, 25°C

I, –40°C

Q, 105°C

Q, 85°C

Q, 25°C

Q, –40°C

105°C

85°C

25°C

–40°C

105°C

85°C

25°C

–40°C

10

12

14

16

18

20

22

24

–0.20

–0.15

–0.10

–0.05

0

0.5

1.0

1.5

2.0

NF (dB)

GAIN ERROR (dB)

PHASE ERROR (dB)

5586 G58

5586 G59

5586 G60

Image Rejection Distribution

vs Temperature (T_C)

Optimized Image Rejection

vs IF Frequency

100

0

OPTIMIZED AT f = 1750MHz

T_C= 55°C

f_RF= 2GHz

RF

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

FIXED f = 1900MHz

LO

WITHOUT INTERSTAGE FILTER

80

60

40

20

0

105°C

85°C

25°C

–40°C

HSLO, DEFAULT

LSLO, DEFAULT

HSLO, OPTIMIZED

LSLO, OPTIMIZED

–50

–45

–40

–35

–30

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

–IMAGE REJECTION (dB)

IF FREQUENCY (GHz)

5586 G61

5586 G62

5586fa

13

For more information www.linear.com/LTC5586

LTC5586

pin FuncTions

RFA (Pin 2): 50Ω switched RF input. The pin should

be DC-blocked with coupling capacitor; 1000pF is

recommended.

IFQM, IFQP, IFIP, IFIM (Pins 15, 16, 25, 26): IF amplifier

output pins. The current used by the output amplifiers

is set by a resistance of 25Ω to 200Ω from each pin to

ground and the VCM control voltage.

TEMP (Pin 3): Temperature monitoring diode. The diode

to ground at this pin can be used to measure the die

temperature. A forward bias current of 100µA can be

used into this pin and the forward voltage drop can be

measured as a function of die temperature.

CSB (Pin 17): Chip Select Bar. When CSB is low, the serial

interface is enabled. It can be driven with 1.2V to 3.3V

logic levels.

VCC (Pin 18): Positive supply pin. This pin should be

bypassed with a 1000pF and 4.7µF capacitor to ground.

RFSW (Pin 4): RF channel select. The state of the RF

switch is the logical AND of the RFSW pin and the RFSW

register value. (See Appendix). This pin should not be left

floating. Either tie high or low.

LOP, LOM (Pins 19, 20): LO inputs. External matching

is not needed. Can be driven 50Ω single-ended or 100Ω

differentially. The LO pins should be DC-blocked with cou-

pling capacitor; 1000pF is recommended. When driven

single-ended, the unused pin should be terminated with

50Ω in series with the DC-blocking capacitor.

VCCN (Pin 5): Positive Supply Pin. This pin must be tied

to the VCC pin.

VCM (Pin 6): IF amplifier common-mode output voltage

adjust. Source resistance should be 1kΩ or lower. If this

pin is left unconnected, it will internally self-bias to 0.9V.

SDO (Pin 21): Serial Data Output. This output can accom-

modate logic levels from 1.2V to 3.3V. During read-mode,

data is read out MSB first.

RFB (Pin 7): 50Ω switched RF input. The pin should

be DC-blocked with coupling capacitor; 1000pF is

recommended.

SDI (Pins 22): Serial Data Input. Data is clocked MSB first

into the mode-control registers on the rising edge of SCK.

SDI can be driven with 1.2V to 3.3V logic levels.

MQP, MQM, MIM, MIP (Pins 9, 10, 31, 32): Mixer dif-

ferential output pins. When connected to the amplifier

SCK (Pin 23): Serial Clock Input. SDI can be driven with

1.2V to 3.3V logic levels.

input pins, the DC bias point is V – 1.4V for each pin. A

CC

low-pass filter is typically used between the MQM(P) or

MIM(P) pins and the AQM(P) or AIM(P) pins to suppress

the high frequency mixing products. See the Applications

section for more information.

OVDD (Pin 24): Positive digital interface supply pin. This

pin sets the logic levels for the digital interface. 1.2V to

3.3V can be used. This pin should be bypassed with a

1µF capacitor to ground. The VCC supply must be applied

before the OVDD supply to prevent damage to the ESD

diodes.

DNC (Pins 11, 14, 27, 30): DO NOT CONNECT. No con-

nection should be made to these pins.

AQM, AQP, AIP, AIM (Pins 12, 13, 28, 29): Amplifier

GND (Pins 1, 8, Exposed Pad Pin 33): Ground. These

pins must be soldered to the circuit board RF ground

plane. The backside exposed pad ground connection

should have a low-inductance connection and good ther-

mal contact to the printed circuit board ground plane

using many through-hole vias. See layout information.

differential input pins. When connected to the mixer out-

put pins, the DC bias point is V – 1.4V for each pin. A

CC

low-pass filter is typically used between the AQM(P) or

AIM(P) pins and the MQM(P) or MIM(P) pins to suppress

the high frequency mixing products. See the Applications

section for more information.

5586fa

14

For more information www.linear.com/LTC5586

LTC5586

block DiagraM

18

VCC

32 31

29

28

MIP MIM

AIM AIP

VCCN

FINE GAIN/DC OFFSET/

DISTORTION ADJUST

BIAS

5

VCM

IFIP

TEMP

6

3

+

–

25

26

IFIM

8 STEPS

RFA

2

LOM

LOP

RFB

20

19

0º

LO MATCH

ADJUST

7

90º

RFSW

4

ATTEN

0dB TO 31dB

–

+

IFQM

IFQP

15

16

SCK

23

SDI

22

ADJUST

REGISTERS

8 STEPS

SPI

SDO

21

CSB

GND

17

1

8

FINE GAIN/DC OFFSET/

DISTORTION ADJUST

EXPOSED

PAD

OVDD

24

MQP

MQM

10

AQM AQP

12 13

9

33

5586 BD01

5586fa

15

For more information www.linear.com/LTC5586

LTC5586

TiMing DiagraMs

SPI Port Timing (Readback Mode)

t

DO

t

AUTO-INCREMENT

t

CKL

AUTO-INCREMENT

CSS

CKH

CSB

SCK

SDI

t

CSH

t

DH

DS

R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX

HIGH-Z

SDO

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7

(SDO_MODE=1)

HIGH-Z

SDO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7

(SDO_MODE=0)

5586 TD01

SPI Port Timing (Write Mode)

t

DO

t

AUTO-INCREMENT

t

CKL

AUTO-INCREMENT

CSS

CKH

CSB

SCK

SDI

t

CSH

t

DH

DS

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

HIGH-Z

SDO

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7

(SDO_MODE=1)

HIGH-Z

SDO

(SDO_MODE=0)

5586 TD02

5586fa

16

For more information www.linear.com/LTC5586

LTC5586

TesT circuiT

RF

C10

C9

C12

0.015"

0.062"

IFIM

OUTPUT

GND

DC

GND

NELCO N4000-13

R3

R4

0.015"

R5

L1

L2

C11

IFIP

OUTPUT

32

31

30

29

28

27

26

25

OV

DD

MIP MIM DNC AIM AIP DNC IFIM IFIP

1

2

24

GND

OVDD

SCK

SDI

23 SCK

22 SDI

21 SDO

20

C1

C3

C40

RFA

TEMP 3

RFSW 4

INPUT

C6

R1

C2

C4

TEMP

RFSW

VCCN

VCM

RFB

SDO

LOM

LO

INPUT

V

CC

5

C5

U1

VCM 6

LTC5586IUH

7

8

33

19

RFB

INPUT

LOP

C7

C8

GND

18

17 CSB

V

CC

VCC

CSB

4.75V TO 5.25V

C42

C43

V

CC

MQP MQM DNC AQM AQP DNC IFQM IFQP

10 11 12 13 14 15 16

C15

9

IFQP

OUTPUT

C13

R20

R11

R13

TEMP

L3

L4

C16

C14

R12

IFQM

OUTPUT

5586 F01

REF DES

C1, C3, C6, C8, C42

C2, C4, C5, C7

C9-C16

VALUE

SIZE

VENDOR

Murata

REF DES

VALUE

22nH

SIZE

VENDOR

Coilcraft

1000pF

0.3pF

3.0pF

1μF

0402

0201

0603

0805

L1-L4

0805

0402

R1, R3, R4, R11, R12

49.9Ω

0Ω

R5, R13

R20

C40

40.2kΩ

C43

4.7μF

Figure 1. Test Circuit Schematic

5586fa

17

For more information www.linear.com/LTC5586

LTC5586

TesT circuiT

Figure 2. Component Side of Evaluation Board

Figure 3. Bottom Side of Evaluation Board

5586fa

18

For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

The LTC5586 is an IQ demodulator designed for high

dynamic range receiver applications. It consists of RF

switches, a step attenuator, I/Q mixers, quadrature LO

amplifiers, IF amplifiers, and correction circuitry for DC

offset, image rejection, and non-linearity.

a resolution of about 0.016dB in order to compensate

for gain mismatches in the IF signal path, either caused

internally by the device or by external amplifiers and fil-

ters. The DC offset in both IF channels can be adjusted in

order to minimize the accumulated DC offset at the A/D

converter input.

Operation

The RF switch state, attenuation, IF gain, gain error and

phase error adjust, DC offset adjust, and non-linearity

adjust registers are digitally controlled through a 4-wire

SPI interface. The register map is detailed in the Appendix.

As shown in the Block Diagram for the LTC5586, the RF

inputs, RFA and RFB, are selected by an internal switch.

The RF signal is then converted to a differential signal by

the on-chip balun transformer covering the 300MHz to

6GHz band. A differential 0 to 31dB step attenuator then

scales the RF input level to the I and Q channel mixers.

RF Input Ports

Figure 4 shows a simplified schematic of the demodula-

tor’s RF inputs (the RFA input is identical to RFB input)

which consist of an RF switch, balun transformer, and

step-attenuator. External DC voltage should not be applied

to the RF input pins. DC current flowing into the pins may

cause damage to the chip. Series DC blocking capacitors

should be used to couple the RF input pins to the RF sig-

nal sources. The RF switch can be selected by the RFSW

pin, and by the RFSW register 0x17 bit[0]. The RFA input

is selected when the logical AND of the value of RFSW in

register 0x17 and the logic level of the RFSW pin is 1 (see

digital input pins section and register map). The switch

state is detailed in Table 1.

The LO inputs are impedance matched using a program-

mable network, and then accurately shifted in phase by

90° by an internal precision phase shifter. This phase

shifter maintains the accurate quadrature relation over

the full LO input range from 300MHz to 6GHz. In addi-

tion, the phase shifter allows fine tuning of the phase

difference between the I- and Q-channel LO with a resolu-

tion of around 0.05 degrees to compensate for any phase

mismatch between the mixers and phase mismatch intro-

duced into the IF path by any filter component mismatch.

The differential mixer IF output signals are filtered off-chip

to remove the f + f signal and other high frequency

RF

LO

Table 1. RF Switch State vs Logic Levels

mixing products before being applied to the on-chip IF

amplifiers. The IF amplifiers have adjustable gain and

common-mode output voltage to allow for direct interfac-

ing with A/D converters. The gain balance between both

IF output channels of the LTC5586 can be fine tuned with

RFSW

RFSW Pin

Register

0

1

0

1

RFB

RFA

V

CC

LTC5586

C1

1000pF

RFA

RFB

INPUT

(MATCHED)

C2

0.3pF

5586 F04

GND

RFSW

Figure 4. Simplified Schematic of the RF Input with External Matching Components

5586fa

19

For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

5

0

As shown in Figure 5, the RF input ports are well matched

with return loss greater than 10dB over the frequency

range of 500MHz to 6GHz with a 0.3pF capacitor on C2.

The RF pins can be externally matched over the 300MHz

to 500MHz frequency range by changing C2 to 4.7pF.

Figure 6 shows the RF input return loss with C2 set to

4.7pF. Table 2 shows the impedance and input reflec-

tion coefficient for the RF input with C2 = 0.3pF. The

input transmission line length is de-embedded from the

measurement.

C2 = 0.3pF

T_C= 25°C

–5

–10

–15

–20

–25

–30

–35

RFA, RFA SELECTED

RFB, RFB SELECTED

RFA, RFB SELECTED

RFB, RFA SELECTED

0

1

2

3

4

5

6

7

8

Table 2. RF Input Impedance

RF FREQUENCY (GHz)

5586 F05

S11

FREQUENCY

Figure 5. RF Input Return Loss

(MHz)

300

INPUT IMPEDANCE (Ω)

24.9 + j27.6

39.1 + j37.3

60.1 + j36.9

77.4 – j1.9

MAG

0.468

0.403

0.330

0.215

0.211

0.297

0.310

0.303

0.228

0.185

0.120

0.202

0.259

0.188

0.138

ANGLE (°)

112.0

83.5

5

400

C2 = 4.7pF

T_C= 25°C

RFA, RFA SELECTED

500

56.2

0

–5

700

–3.2

1000

1500

2000

2500

3000

3500

4000

4500

5000

5500

6000

43.7 – j19.2

27.2 – j2.1

–96.7

–173.2

134.4

96.0

–10

–15

–20

–25

–30

29.6 + j14.5

39.3 + j26.0

48.9 + j23.1

52.4 + j19.2

60.5 + j8.2

79.9

72.3

33.8

69.2 + j15.0

82.4 + j11.5

71.2 – j8.6

30.8

0

1

2

3

4

5

6

7

8

RF FREQUENCY (GHz)

14.6

5586 F06

–18.0

–96.1

Figure 6. RF Input Return Loss with C2 = 4.7pF

46.8 – j13.1

LO Input Port

V

CC

The demodulator’s LO input interface is shown in Figure 7.

The input consists of a programmable input match and a

high precision quadrature phase shifter which generates

0° and 90° phase shifted LO signals for the LO buffer

amplifiers to drive the I/Q mixers. DC blocking capacitors

are required on the LOP and LOM inputs. When using a

LTC5586

C6

1000pF

LO

INPUT

(MATCHED)

LOM

C5

0.3pF

LO

MATCH

ADJUST

0º

R1

49.9Ω

90º

LOP

C8

1000pF

C7

0.3pF

5586 F07

GND

Figure 7. Simplified Schematic of the LO Inputs

with Single-Ended Drive

5586fa

20

For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

single-ended LO input, it is necessary to terminate the

unused LO input (LOP in Figure 7) into 50Ω.

The LO inputs can also be driven differentially. Figure 10

compares the uncalibrated OIP2 performance of single

ended versus differential LO drive using the ANAREN

B4859A53 balun as shown in the schematic of Figure 9.

The programmable input match adjust is controlled by

the BAND, CF1, LF1, and CF2 registers as detailed in the

5

V

CC

T_C= 25°C

0

–5

LTC5586

C6

ANAREN

1000pF

LO

INPUT

(MATCHED)

B4859A53

LOM

–10

–15

–20

–25

–30

–35

C5

0.3pF

LO

MATCH

ADJUST

0º

C8

1000pF

90º

LOP

C7

0.3pF

5586 F09

GND

0

1

2

3

4

5

6

7

8

Figure 9. Simplified Schematic of the LO Inputs

Using a Balun for Differential Drive

LO FREQUENCY (GHz)

0, 31, 3, 31

0, 17, 2, 31

0, 14, 1, 27

1, 21, 3, 28

1, 15, 1, 31

1, 2, 1, 10

1, 1, 0, 19

1, 0, 0, 0

5586 F08

100

T_C= 25°C

90

Figure 8. Single-Ended LO Input Return Loss vs

BAND, CF1, LF1, and CF2

80

70

60

50

40

register map shown in Table 3. The return loss for the

register setting in Table 3 is shown in Figure 8.

Table 3. Register Settings for Single-Ended LO Matching

30

I, SINGLE-ENDED

LO FREQUENCY (MHz)

BAND

CF1

31

21

14

17

10

15

14

8

LF1

CF2

31

24

23

31

23

31

27

21

31

28

26

31

3

20

10

0

Q, SINGLE-ENDED

I, DIFFERENTIAL

Q, DIFFERENTIAL

300 - 339

0

1

3

339 - 398

3

0

1

2

3

4

5

6

398 - 419

3

RF FREQUENCY (GHz)

419 - 556

2

5586 F10

556 - 625

2

Figure 10. OIP2 vs Single-Ended and Differential LO Input

625 - 801

1

801 - 831

1

831 - 1046

1046 - 1242

1242 - 1411

1411 - 1696

1696 - 2070

Default

1

31

21

17

15

8

3

2

1

3

2070 - 2470

2470 - 2980

2980 - 3500

3500 - 6000

8

1

21

10

19

0

2

1

0

5586fa

21

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LTC5586

applicaTions inForMaTion

Interstage Filter

lengths on the amplifier inputs can lead to instability. As

shown in Figure 12, a 50Ω common-mode termination

resistor can be used to better ensure stability with long

line lengths and/or higher order filtering. The placement

of C9 and C11 should be as close as possible to the mixer

An interstage IF filter should be used between the MIP

(MIM) and AIP (AIM) pins and the MQP (MQM) and AQP

(AQM) pins to suppress the large f + f and other mix-

RF LO

ing products from the mixer outputs. Without the filter, the

linearity of the amplifier can be degraded for the desired

signal. Figure 11 shows a recommended lowpass filter.

Table 4 shows typical values used for a lowpass response

of various bandwidths.

outputs for effective filtering of the 2xLO, f + f , and

RF

LO

other mixing products.

MIP

MIM

C11

C9

Table 4. Component Values for Interstage Lowpass Filter

1dB BW (MHz)

L1, L2 (nH)

C9, C11 (pF)

C10, C12 (pF)

L2

C12

L1

C10

20

50

330

150

68

33

22

8

39

15

120

47

AIM

AIP

100

300

500

1000

10

22

5586 F12

4.7

3.0

0.5

6.8

3.0

1.0

50Ω

Figure 12. Interstage IF Filter with Common-Mode Termination

It is important that the placement of C10 and C12 be

as close as possible to the amplifier inputs. Long line

By adjusting the values of the capacitors in the filter, it

is possible to add or remove frequency slope of the IF

V

CC

LTC5586

PACKAGE

PARASITICS

1pF 50Ω

50Ω

1pF

1.5nH

2k

MIP

0.2pF

1.5nH

MIM

0.2pF

C11

C9

42mA

AC CURRENT

SOURCE

L2

L1

VCC

PACKAGE

PARASITICS

1.5nH

100Ω

C12

C10

AIM

0.2pF

1.5nH

AIP

0.2pF

0.6pF

50Ω

0.6pF

50Ω

5586 F11

GND

Figure 11. Simplified Schematic of the Mixer Output and IF Amplifier Input with Interstage Filter

5586fa

22

For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

response. The RF input has a frequency slope above 2GHz

of approximately –2dB/GHz. If a high-side LO (HSLO) is

used the resulting IF slope will be 2dB/GHz. If a low-side

LO (LSLO) is used the resulting IF slope will be –2dB/GHz.

The IF filter component values can be adjusted so that

approximately 1dB of peaking or roll-off can be achieved

over the filter bandwidth to give an overall flat IF response

for the HSLO or LSLO case.

45

40

35

30

25

20

15

IF TONESPACING = 1MHz

P

T

= –1.5dB/TONE

= 55°C

IF

C

0.5V

0.7V

0.9V

1.2V

1.5V

1.8V

2.0V

I-Channel and Q-Channel Outputs

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

The phase relationship between the I-channel output sig-

nal and the Q-channel output signal is fixed. When the

LO input frequency is higher (or lower) than the RF input

frequency, the Q-channel outputs (IFQP, IFQM) lead (or

lag) the I-channel outputs (IFIP, IFIM) by 90°.

IF Frequency (GHz)

5586 F13

Figure 13. OIP3 of Amplifier Only vs Output

Common-Mode Voltage (VCM)

Figure 14 shows a simplified schematic of the IF amplifier

outputs. The current-mode outputs require a terminating

resistance to establish a common-mode voltage level. The

optimum operating current is 18mA per output. A 50Ω ter-

mination to ground is recommended on each output for a

0.9V common-mode voltage. Operation at higher or lower

common-mode voltages is possible with the addition of

a common-mode termination. For example, to operate

at 1.8V, an additional common-mode resistance of 25Ω

(R5 = 66.5Ω and R6 = 0Ω, or R5 = R6 = 43.2Ω) would be

used to maintain an output current of 18mA. Alternatively,

a 100Ω termination to ground on each output can be used

for 1.8V common-mode voltage with 6dB more conver-

sion gain. To operate at lower common-mode voltages, a

lower termination resistance can be used on each output

at the expense of conversion gain, or a negative supply

can be used at the connection of the termination resis-

tors. Figure 13 shows the OIP3 of the amplifier alone with

various common-mode voltages.

The amplifier gain can be adjusted in 8 steps of roughly

1dB from 8dB to 15dB using the AMPG register. Setting

AMPG = 0x7 sets the gain at about 15dB and setting

AMPG = 0x0 sets the gain to about 8dB.

V

CC

LTC5586

5TH ORDER

ANTI-ALIAS

FILTER

L5

L7

C20

0.9V

VCM

PACKAGE

PARASITICS

1.5nH

2k

R3

R7

C23

C17

68.1Ω

200Ω

IFIP

AC CURRENT

SOURCE

R5

R6

0Ω

0.2pF

R2

24.9Ω

R9

0Ω

24.9Ω

1.5nH

IFIM

R4

R8

200Ω

0.2pF

C24

Z

= 100Ω

OUT

C18

68.1Ω

L6

L8

C21

0.9V

5586 F14

GND

Figure 14. Simplified Schematic of the IF Amplifier Output with Anti-Alias Filter

5586fa

23

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LTC5586

applicaTions inForMaTion

A typical anti-alias filter is shown in Figure 14 for inter-

face with an ADC. The parallel combinations R3||R7 and

R4||R8 set the differential impedance for the ADC. The

input and output of the filter contain a common-mode ter-

mination for high frequencies. These are formed by C17,

C18 and 24.9Ω at the input and C23, C24 and 24.9Ω at

the output. The common-mode termination at the ampli-

fier output ensures stability and the common-mode ter-

mination at the ADC input provides a termination for the

high-frequency kickback from the sampling capacitors in

the ADC. Table 5 shows some typical values vs 1dB cutoff

frequency for the anti-alias filter. To optimize the flatness

and ripple of the IF band, both the IF interstage filter and

the anti-alias filter can be designed together in a simulator

including package parasitics. The additional slope due to

RF slope and HSLO or LSLO can be compensated by using

this method. The layout of the anti-alias filter should be

done so that the amplifier outputs and ADC inputs are as

close as possible. This is to prevent long line lengths from

introducing additional parasitics.

Table 6. IF Amplifier S-Parameters (Differential-Mode)

IF

S

11

S

22

21

12

MAG ANG MAG ANG MAG ANG MAG ANG

(MHz)

0.001 0.204 –179.9 2.129 180.0 1.8e-4 164.8 0.014 178.5

100 0.203 176.0 2.154 171.9 5.4e-4 118.0 0.026 –120.9

200 0.205 172.2 2.170 163.7 1.0e-4 102.8 0.050 –112.0

300 0.207 168.5 2.197 155.6 1.7e-4 92.8 0.079 –113.5

400 0.210 164.8 2.239 147.3 2.8e-4 93.7 0.111 –118.3

500 0.215 160.9 2.292 138.8 3.2e-4 95.4 0.147 –125.0

600 0.221 157.0 2.363 130.1 4.0e-4 92.0 0.186 –132.1

700 0.227 153.0 2.445 121.2 5.0e-4 92.1 0.230 –140.0

800 0.235 149.0 2.535 112.0 5.5e-4 86.2 0.279 –148.1

900 0.242 144.6 2.642 102.0 6.9e-4 93.2 0.334 –157.0

1000 0.251 140.6 2.770 92.3 7.9e-4 92.7 0.396 –166.2

1500 0.303 117.6 3.420 32.3 0.003 92.6 0.738 134.4

2000 0.365 90.2 3.318 –45.5 0.005 33.2 0.828 70.0

2500 0.385 56.1 2.232 –105.2 0.005 –3.1 0.666 13.1

3000 0.365 16.6 2.620 –160.2 0.005 –34.2 0.488 –38.4

3500 0.319 –28.2 1.021 157.4 0.005 –61.9 0.418 –94.7

4000 0.307 –83.4 0.742 113.3 0.005 –79.5 0.409 –150.6

Table 7. IF Amplifier S-Parameters (Common-Mode)

Table 5. Component Values for Anti-Alias Lowpass Filter

IF

S

11

S

22

21

12

1dB BW

(MHz)

L5 – L8

(nH)

C17, C18

(pF)

C20, C21

(pF)

C23, C24

(pF)

MAG ANG MAG ANG MAG ANG MAG ANG

(MHz)

0.001 0.184 –138.7 9.2e-4 –112.8 0.037 –65.3 0.985 179.8

100 0.186 172.5 0.085 –118.9 0.013 –68.6 0.152 126.7

200 0.188 166.6 0.173 –134.7 0.007 –91.8 0.125 116.7

300 0.191 160.2 0.237 –150.0 0.004 –113.1 0.097 97.3

400 0.196 154.4 0.291 –163.8 0.002 –145.4 0.067 75.2

500 0.202 148.4 0.340 –176.8 0.002 170.2 0.037 43.6

600 0.210 142.8 0.387 170.9 0.002 137.0 0.023 –38.0

700 0.219 137.2 0.436 159.1 0.003 118.1 0.051 –97.8

800 0.230 132.0 0.488 147.1 0.003 107.8 0.094 –121.5

900 0.243 126.5 0.550 134.9 0.004 106.6 0.148 –137.0

1000 0.252 120.9 0.612 122.2 0.006 104.8 0.211 –151.3

1500 0.325 96.7 0.981 43.4 0.020 80.4 0.749 136.1

2000 0.438 72.1 0.776 –46.1 0.036 18.6 1.000 55.9

20

50

560

240

120

33

56

22

180

68

82

33

100

300

500

1000

12

39

22

3.9

1.8

1.0

8.2

6.8

3.3

6.8

3.3

1.8

22

8

Tables 6 and 7 show the differential and common-mode

S-parameters for the amplifier by itself with 50Ω termina-

tions on all ports. In addition, common-mode termina-

tions were used on the input and output ports having a

value of 2pF in series with 50Ω.

2500 0.549 40.1 0.496 –97.1 0.041 –21.9 0.873

2.9

3000 0.601 6.9 0.397 –143.2 0.042 –52.2 0.764 –37.3

3500 0.618 –27.5 0.281 –175.7 0.044 –80.3 0.668 –72.7

4000 0.595 –60.3 0.254 147.3 0.046 –101.2 0.620 –107.0

5586fa

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For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

The common-mode feedback amplifier holds the com-

mon-mode output voltage within about 20mV of the VCM

pin voltage. The VCM pin interface is shown in Figure 15.

The VCM pin should be driven by a voltage source with an

output impedance lower than 1kΩ. When the VCM pin is

unbiased, the output common-mode voltage will be held

at a nominal 0.9V given by the internal voltage divider

formed by the 40kΩ and 8kΩ resistors. Connecting the

VCM pin to an ADC common-mode reference pin allows

the output common-mode voltage of the IF amplifier to

track the ADC common-mode.

Digital Input Pins

Figure 17 show the simplified schematics for the digital

input pins, SCK, CSB, SDI, and RFSW. These pins should

not be left floating, since there is no internal pull-down

or pull-up.

V

CC

LTC5586

2k

DIGITAL

INPUT

V

CC

LTC5586

40k

20k

5586 F17

GND

250Ω

V

CM

Figure 17. Simplified Schematic of the Digital Input Pins

(SCK, CSB, SDI, RFSW)

8k

6.5pF

OVDD Interface

5586 F15

GND

Figure 18 shows the simplified schematic of the OVDD

interface. The OVDD pin supplies the voltage for the digital

inputs and SDO pin. By setting the pin at 1.2V to 3.3V, the

serial port can function with 1.2V to 3.3V logic levels. It is

important that when sequencing the supply voltages for

the chip that the VCC supply be brought up first before the

OVDD supply. This is to prevent the ESD diode connected

between OVDD and VCC from getting damaged.

Figure 15. Simplified Schematic of the VCM Input Pin

Temperature Diode

A schematic of the TEMP pin is shown in Figure 16. The

temperature diode can be used to directly measure the

die temperature. A 40kΩ resistor is recommended to V

CC

to generate a 100µA current source for the diode readout.

V

CC

The temperature slope is about –1.52mV/°C.

LTC5586

V

CC

LTC5586

SDO

R20

40.2k

100Ω

OV

DD

TEMP

V

TEMP

DIGITAL

INPUTS

5586 F18

5586 F16

GND

Figure 16. Schematic of the TEMP Pin

Figure 18. Simplified Schematic of the OVDD Pin Interface

5586fa

25

For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

SERIAL PORT

SDO_MODE Control Bit

The SPI-compatible serial port provides control and moni

toring functionality.

-

The SDO output has two modes of operation as shown

in the timing diagram. When register 0x16 control bit

SDO_MODE = 0, the SDO pin functions as a normal output

which is High-Z during a write command. If SDO_MODE

= 1, the SDO output is put into a serial repeater mode

where SDO echoes the command written to SDI before

readback of register contents either in read or write mode.

This can be used in high bus noise environments where

it is necessary to perform error-checking on commands

sent to the serial port.

Communication Sequence

The serial bus is comprised of CSB, SCK, SDI and SDO.

Data transfers to the part are accomplished by the

serial bus master device first taking CSB low to enable

the LTC5586’s port. Input data applied on SDI is clocked

on the rising edge of SCK, with all transfers MSB first.

The communication burst is terminated by the serial bus

master returning CSB high. See the timing diagrams for

details.

A simplified schematic of the SDO output is shown in

Figure 19. The OVDD supply sets the logic level of the out-

put, and a 25Ω series resistor limits the output current.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC5586 or other serial device connected in parallel on

the serial bus), as SDO is high impedance (Hi-Z) when

CSB = 1.

OV

V

CC

DD

LTC5586

Single Byte Transfers

25Ω

The serial port is arranged as a simple memory map, with

status and control available in 23 registers as shown in

the appendix. All data bursts are comprised of at least

two 8-bit bytes. The most significant bit of the first byte

is the read/write bit. Setting this bit to 1 puts the serial

port into read mode. The next 7 bits of the first byte are

address bits and can be set from 0x00 to 0x17. The subse-

quent byte, or bytes, is data from/to the specified register

address. See the timing diagrams for details. Note that the

written data is transferred to the internal register at the

SDO

5586 F19

GND

Figure 19. Simplified Schematic of the SDO Pin Interface

th

falling edge of the 16 clock cycle (parallel load).

Register Defaults

Multiple Byte Transfers

The register map and defaults are given in Tables 8 and 9

in the appendix. When the device is powered up, the reg-

isters may not be reset to their default values. By writing

a 1 to the SRST bit (bit[3]) of register 0x16, the device

will go into soft reset and the registers will be reset to

their default values.

More efficient data transfer of multiple bytes is accom-

plished by using the LTC5586’s register address auto-

increment feature as shown in the timing diagram. The

serial port master sends the destination register address

in the first byte and reads or writes data in the second

byte as before, but on the third byte the address pointer is

auto-incremented by 1 and the serial port master can read

or write to subsequent registers. If the register address

pointer attempts to increment past 23 (0x17), it is auto-

matically reset to 0.

5586fa

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For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

Impairment Minimization

In the DSP, a complex-FFT can be used to extract gain

error and phase error for image rejection optimization,

while the FFT of each channel can be used to optimize

DC offset and nonlinearities independently. One possible

general optimization method would be to sequentially

apply a 1-D minimization algorithm to each impairment. A

simple bisection method or more complicated (but faster

converging) Brent’s method[1] could be used for the 1-D

minimization.

The LTC5586 contains circuitry for minimizing receiver

impairments such as DC offset, Phase and Gain Error,

and non-linearity. An example block diagram of a DPD

transmitter application is shown in Figure 20. A DSP is

used to implement a 2-tone source and minimization algo-

rithms for calibration of impairments. To setup the DSP

for impairment calibration, the DATA ENCODER would

be configured to produce symbols for two tones in the

band of interest. The tones would be modulated up to

the carrier frequency of f_LObefore being applied to the

LTC5586 RFA input. The tones are then down-converted

to baseband for the DSP.

Figure 21 shows the non-optimized spectrum and

Figure 22 shows the optimized spectrum for a 2-tone

test signal at 2GHz. The Upper Sideband spectrum is the

desired signal while the Lower Sideband is the image

signal.

[1] Saul Teukolsky, William T. Vetterling, William H. Press, and Brian P. Flannery, “Numerical

Recipes in C: The Art of Scientific Computing,” p. 352, 1988.

LTC5588-1

LTC2000-14

DSP

I

DAC

0º

COMPLEX GAIN

PREDISTORTER

DATA

INPUT

PA

90º

LTC2000-14

Q

DAC

DATA

ENCODER

LTC6946

ADAPTIVE

LUT

f

LO

LTC2158-14

LTC5586

FEEDBACK

SIGNAL

PROCESSING

I

ADC

RFA

RFB

LINEARITY

DC OFFSET

IMAGE

0º

FFT

90º

ADJUST

RFSW

Q

EXTRACT

FFT BIN

ADC

SPI

IMPAIRMENT

MINIMIZATION

SPI

5586 F20

Figure 20. Example Block Diagram of a DPD Transmitter with DSP for Impairment Minimization

5586fa

27

For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

Figure 21. Non-Optimized 2-Tone Spectrum at 2GHz with 100MHz Anti-Alias Filter

5586fa

28

For more information www.linear.com/LTC5586

LTC5586

applicaTions inForMaTion

Figure 22. Optimized 2-Tone Spectrum at 2GHz with 100MHz Anti-Alias Filter

5586fa

29

For more information www.linear.com/LTC5586

LTC5586

appenDix

Table 8. Serial Port Register Contents

ADDR

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

MSB

[6]

[5]

[4]

[3]

[2]

[1]

LSB

R/W

DEFAULT

0x80

0x04

0x82

0x48

0xE3

0x80

0x6A

0xF0

0x01

IM3QY[7]

IM3QX[7]

IM3IY[7]

IM3IX[7]

IM2QX[7]

IM2IX[7]

IM3QY[6]

IM3QX[6]

IM3IY[6]

IM3IX[6]

IM2QX[6]

IM2IX[6]

IM3QY[5]

IM3QX[5]

IM3IY[5]

IM3IX[5]

IM2QX[5]

IM2IX[5]

IM3QY[4]

IM3QX[4]

IM3IY[4]

IM3IX[4]

IM2QX[4]

IM2IX[4]

IM3QY[3]

IM3QX[3]

IM3IY[3]

IM3IX[3]

IM2QX[3]

IM2IX[3]

IM3QY[2]

IM3QX[2]

IM3IY[2]

IM3IX[2]

IM2QX[2]

IM2IX[2]

IM3QY[1]

IM3QX[1]

IM3IY[1]

IM3IX[1]

IM2QX[1]

IM2IX[1]

IM3QY[0]

IM3QX[0]

IM3IY[0]

IM3IX[0]

IM2QX[0]

IM2IX[0]

HD3QY[7] HD3QY[6] HD3QY[5]

HD3QX[7] HD3QX[6] HD3QX[5]

HD3QY[4] HD3QY[3] HD3QY[2] HD3QY[1] HD3QY[0]

HD3QX[4] HD3QX[3] HD3QX[2] HD3QX[1] HD3QX[0]

HD3IY[7]

HD3IX[7]

HD3IY[6]

HD3IX[6]

HD3IY[5]

HD3IX[5]

HD3IY[4]

HD3IX[4]

HD3IY[3]

HD3IX[3]

HD3IY[2]

HD3IX[2]

HD3IY[1]

HD3IX[1]

HD3IY[0]

HD3IX[0]

HD2QY[7] HD2QY[6] HD2QY[5]

HD2QX[7] HD2QX[6] HD2QX[5]

HD2QY[4] HD2QY[3] HD2QY[2] HD2QY[1] HD2QY[0]

HD2QX[4] HD2QX[3] HD2QX[2] HD2QX[1] HD2QX[0]

HD2IY[7]

HD2IX[7]

DCOI[7]

DCOQ[7]

ATT[4]

HD2IY[6]

HD2IX[6]

DCOI[6]

DCOQ[6]

ATT[3]

HD2IY[5]

HD2IX[5]

DCOI[5]

DCOQ[5]

ATT[2]

GERR[3]

LVCM[0]

LF1[0]

HD2IY[4]

HD2IX[4]

DCOI[4]

DCOQ[4]

ATT[1]

GERR[2]

CF1[4]

CF2[4]

PHA[5]

AMPG[0]

1*

HD2IY[3]

HD2IX[3]

DCOI[3]

DCOQ[3]

ATT[0]

HD2IY[2]

HD2IX[2]

DCOI[2]

DCOQ[2]

IP3IC[2]

GERR[0]

CF1[2]

HD2IY[1]

HD2IX[1]

DCOI[1]

DCOQ[1]

IP3IC[1]

IP3CC[1]

CF1[1]

HD2IY[0]

HD2IX[0]

DCOI[0]

DCOQ[0]

IP3IC[0]

IP3CC[0]

CF1[0]

GERR[5]

LVCM[2]

BAND

GERR[4]

LVCM[1]

LF1[1]

GERR[1]

CF1[3]

CF2[3]

CF2[2]

CF2[1]

CF2[0]

PHA[8]

PHA[0]

1*

PHA[7]

AMPG[2]

1*

PHA[6]

AMPG[1]

1*

PHA[4]

PHA[3]

PHA[2]

AMPIC[1]

0*

PHA[1]

AMPIC[0]

0*

AMPCC[1] AMPCC[0]

SRST

0*

SDO_MODE

0*

CHIPID[1] CHIPID[0]

0*

RFSW

*Unused, do not change default value.

5586fa

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For more information www.linear.com/LTC5586

LTC5586

appenDix

Table 9. Serial Port Register Bit Field Summary

BITS

FUNCTION

DESCRIPTION

VALID VALUES

DEFAULT

0x02

0x06

0x00

1

AMPCC[1:0]

AMPIC[1:0]

AMPG[2:0]

ATT[4:0]

BAND

IF Amplifier IM3 CC Adjust

IF Amplifier IM3 IC Adjust

IF Amplifier Gain Adjust

Step Attenuator Control

LO Band Select

Used to optimize the IF amplifier IM3.

Adjusts the amplifier gain from 8dB to 15dB.

Controls the step attenuator from 0dB to 31dB attenuation.

0x00 to 0x03

0x00 to 0x07

0x00 to 0x1F

0, 1

Selects which LO matching band is used. BAND = 1 for high band. BAND

= 0 for low band.

CF1[5:0]

LO Matching Capacitor CF1 Controls the CF1 capacitor in the LO matching network.

LO Matching Capacitor CF2 Controls the CF2 capacitor in the LO matching network.

0x00 to 0x1F

0x00 to 0x03

0x00 to 0xFF

0x00 to 0x3F

0x00 to 0xFF

0x00 to 0x03

0x00 to 0x07

0x00 to 0x03

0x00 to 0x07

0x000 to 0x1FF

0x08

0x03

0x00

0x80

0x20

0x80

0x02

0x04

0x03

0x02

0x100

CF2[5:0]

CHIPID

Chip Identification Bits

I-Channel DC Offset

Factory set to default value.

DCOI[7:0]

DCOQ[7:0]

GERR[5:0]

HD2IX[7:0]

HD2IY[7:0]

HD2QX[7:0]

HD2QY[7:0]

HD3IX[7:0]

HD3IY[7:0]

HD3QX[7:0]

HD3QY[7:0]

IM2IX[7:0]

IM2QX[7:0]

IM3IX[7:0]

IM3IY[7:0]

IM3QX[7:0]

IM3QY[7:0]

IP3CC[1:0]

IP3IC[2:0]

LF1[1:0]

Controls the I-channel DC offset over a range from –200mV to 200mV.

Controls the Q-channel DC offset over a range from –200mV to 200mV.

Controls the IQ gain error over a range from –0.5dB to 0.5dB.

Controls the I-channel HD2 X-vector adjustment.

Controls the I-channel HD2 Y-vector adjustment.

Controls the Q-channel HD2 X-vector adjustment.

Controls the Q-channel HD2 Y-vector adjustment.

Controls the I-channel HD3 X-vector adjustment.

Controls the I-channel HD3 Y-vector adjustment.

Controls the Q-channel HD3 X-vector adjustment.

Controls the Q-channel HD3 Y-vector adjustment.

Controls the I-channel IM2 X-vector adjustment.

Controls the Q-channel IM2 X-vector adjustment.

Controls the I-channel IM3 X-vector adjustment.

Controls the I-channel IM3 Y-vector adjustment.

Controls the Q-channel IM3 X-vector adjustment.

Controls the Q-channel IM3 Y-vector adjustment.

Used to optimize the RF input IP3.

Q-Channel DC Offset

IQ Gain Error Adjust

HD2 I-Channel X-Vector

HD2 I-Channel Y-Vector

HD2 Q-Channel X-Vector

HD2 Q-Channel Y-Vector

HD3 I-Channel X-Vector

HD3 I-Channel Y-Vector

HD3 Q-Channel X-Vector

HD3 Q-Channel Y-Vector

IM2 I-Channel X-Vector

IM2 Q-Channel X-Vector

IM3 I-Channel X-Vector

IM3 I-Channel Y-Vector

IM3 Q-Channel X-Vector

IM3 Q-Channel Y-Vector

RF Input IP3 CC Adjust

RF Input IP3 IC Adjust

LO Matching Inductor LF1

LO Bias Adjust

Used to optimize the RF input IP3.

Controls the LF1 inductor in the LO matching network.

Used to optimize mixer IP3.

LVCM[2:0]

PHA[8:0]

IQ Phase Error Adjust

Controls the IQ phase error over a range from –2.5 Degrees to 2.5

Degrees.

RFSW

RF Switch Input Select

SDO Readback Mode

Soft Reset

Controls the RF switch state with a logical AND of the RFSW pin.

Enables the SDO readback mode if SDO_MODE = 1.

0, 1

1

0

SDO_MODE

SRST

Writing 1 to this bit resets all registers to their default values.

5586fa

31

For more information www.linear.com/LTC5586

LTC5586

package DescripTion

Please refer to http://www.linear.com/product/LTC5586#packaging for the most recent package drawings.

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05

3.50 REF

(4 SIDES)

3.45 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ±0.05

5.00 ±0.10

(4 SIDES)

31 32

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ±0.10

3.50 REF

(4-SIDES)

3.45 ±0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 ±0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

5586fa

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For more information www.linear.com/LTC5586

LTC5586

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

08/17 Various corrections.

5, 7, 14, 21, 23, 32

5586fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

33

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC5586

LTC5586

Typical applicaTion

Simplified Schematic of a 0.3GHz to 6.0GHz Receiver, (Only I-Channel Is Shown)

L1, 68nH

C9

10pF

C10

22pF

L2, 68nH

C11 C12

10pF 22pF

ANTI-ALIAS

FILTER

MIP MIM

AIM AIP

LTC5586

L5, 120nH

L7, 120nH

C20

RF INPUT

0.3 - 6.0GHz

C17

R3

R7

C23

LTC2158-14

39pF

12pF 68Ω

200Ω

22pF

+

C1

DA12_13

A

IFIP

IN

1000pF

RFA

DDR

LVDS

-

R2

25Ω

R9

25Ω

ADC

A

IN

C2

0.3pF

R4

68Ω

L6, 120nH

R8

200Ω

IFIM

DA0_1

C18

12pF

C24

22pF

VCM

L8, 120nH

LOM

LOP

VCM

C21

39pF

C6

1000pF

C8

1000pF

R1

49.9Ω

C47

0.01µF

C45

0.01µF

LO INPUT

0.3 - 6.0GHz

R32, 10Ω

5586 TA02

relaTeD parTs

PART NUMBER DESCRIPTION

Infrastructure

COMMENTS

LTC5569

300MHz to 4GHz Dual Active Downconverting

Mixer

2dB Gain, 26.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/180mA Supply

LTC6409

LTC5549

10GHz GBW Differential Amplifier

DC-Coupled, 48dBm OIP3 at 140MHz, 1.1nV/√Hz Input Noise Density

2GHz to 14GHz Mixer with Integrated LO Doubler Ultra-Wideband Bidirectional Up-, or Down-Conversion Mixer, +22.8dBm IIP3 at

12GHz, 0dBm LO Drive, 500MHz to 6GHz IF Bandwidth

LTC5548

2GHz to 14GHz Mixer with IF Frequency Extending Ultra-Wideband Bidirectional Up-, or Down-Conversion Mixer, +18.7dBm IIP3 at

to DC

12GHz, 0dBm LO Drive with On-Chip Frequency Doubler, DC to 6GHz IF Bandwidth

LTC5588-1

200MHz to 6GHz Quadrature Modulator

+31dBm OIP3, –160dBm/Hz Output Noise Floor, Excellent ACPR Performance

RF PLL/Synthesizer with VCO

LTC6946-3

Low Noise, Low Spurious Integer-N PLL with

Integrated VCO

640MHz to 5.79GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop

Phase Noise

LTC6948

Ultralow Noise Fractional-N Synthesizer with

Integrated VCO

370MHz to 6.39GHz PLL, No Delta-Sigma Modulator Spurs, 18-Bit Fractional

Denominator, –226dBc/Hz Normalized In-Band Phase Noise Floor

ADCs

LTC2145-14

LTC2185

LTC2158-14

14-Bit, 125Msps 1.8V Dual ADC

16-Bit, 125Msps 1.8V Dual ADC

73.1dB SNR, 90dB SFDR, 95mW/Ch Power Consumption

76.8dB SNR, 90dB SFDR, 185mW/Channel Power Consumption

14-Bit, 310Msps 1.8V Dual ADC, 1.25GHz Full-

Power Bandwidth

68.8dB SNR, 88dB SFDR, 362mW/Ch Power Consumption, 1.32V Input Range

P-P

5586fa

LT 0817 REV A • PRINTED IN USA

www.linear.com/LTC5586

34

 LINEAR TECHNOLOGY CORPORATION 2017

For more information www.linear.com/LTC5586

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