ESMT
M16U4G16256A
Precharge Power-Down Current
CKE: Low; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address inputs: stable at 0; data I/O: VDDQ; DM_n: stable at 1;
bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0
IDD2P
IPP2P
IDD2Q
Precharge Power-Down IPP Current
Same condition with IDD2P
Precharge Quiet Standby Current
CKE: H; External clock: On; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address Inputs: stable at 0; data I/O: VDDQ; DM_n: stable at
1;bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0
Active Standby Current
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address Inputs: partially toggling according to Measurement-Loop
Pattern table; data I/O: VDDQ; DM_n: stable at 1; bank activity: all banks open; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0; pattern details: see Measurement-Loop Pattern table
IDD3N
Active Standby Current (AL=CL-1)
Same condition with IDD3N
IDD3NA
IPP3N
Active Standby IPP Current
AL = CL-1, Other conditions: see IDD3N
Active Power-Down Current
CKE: L; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address inputs: stable at 0; data I/O: VDDQ; DM_n:stable at 1;
bank activity: all banks open; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0
IDD3P
IPP3P
Active Power-Down IPP Current
Same condition with IDD3P
Operating Burst Read Current
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: H between RD;
Command, address, Bank group address, Bank address Inputs: partially toggling according to Measurement-Loop
Pattern table; data I/O: seamless read data burst with different data between one burst and the next one according
to Measurement-Loop Pattern table; DM_n: stable at 1;Bank activity: all Banks open, RD commands cycling
through banks: 0,0,1,1,2,2,... (see Measurement-Loop Pattern table); output buffer and RTT: enabled in MR*2;
ODT signal: stable at 0; pattern details: see Measurement-Loop Pattern table
IDD4R
Operating Burst Read Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4R
IDD4RA
IDD4RB
IPP4R
Operating Burst Read Current with Read DBI
Read DBI enabled*3, Other conditions: see IDD4R
Operating Burst Read IPP Current
Same condition with IDD4R
IDDQ4R Operating Burst Read IDDQ Current
(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB Operating Burst Read IDDQ Current with Read DBI
(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: H between WR;
command, address, bank group address, bank address inputs: partially toggling according to Measurement-Loop
IDD4W
Pattern table; data I/O: seamless write data burst with different data between one burst and the next one according
to Measurement-Loop Pattern table;DM_n: stable at 1; bank activity: all banks open, WR commands cycling
through banks: 0,0,1,1,2,2,.. (see Measurement-Loop Pattern table); output buffer and RTT: enabled in MR*2;
ODT signal: stable at H; pattern details: see Measurement-Loop Pattern table
Operating Burst Write Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4W
IDD4WA
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 13/53