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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • M25P128-VMF6TP
  • 数量-
  • 厂家-
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  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • M25P128-VMF6TP图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TP 现货库存
  • 数量6851 
  • 厂家MICRON 
  • 封装SOP16 
  • 批号24+ 
  • 全新原装现货,可开增值税发票,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • M25P128-VMF6TPB图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TPB 现货库存
  • 数量5540 
  • 厂家Micron 
  • 封装SOP16 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084
  • M25P128-VMF6TPB图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • M25P128-VMF6TPB 现货库存
  • 数量8000 
  • 厂家micron 
  • 封装SO-16 
  • 批号25+ 
  • 只做原装正品现货销售
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82723761 QQ:867789136QQ:1245773710
  • M25P128-VMF6TPB图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TPB 现货库存
  • 数量3600 
  • 厂家MICRON 
  • 封装SOP 
  • 批号25+ 
  • 全新原装,欢迎查询
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • M25P128-VMF6TPB图
  • 集好芯城

     该会员已使用本站13年以上
  • M25P128-VMF6TPB 现货库存
  • 数量20013 
  • 厂家ST(意法) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • M25P128-VMF6TPB图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • M25P128-VMF6TPB 现货库存
  • 数量14500 
  • 厂家MICRON/美光 
  • 封装SOP-16 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
  • M25P128-VMF6TPB图
  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TPB 现货库存
  • 数量8308 
  • 厂家MICRON/镁光 
  • 封装SOP16 
  • 批号22+ 
  • 市场最低价!原厂原装假一罚十
  • QQ:2885659458QQ:2885659458 复制
    QQ:2885657384QQ:2885657384 复制
  • 0755-83952260 QQ:2885659458QQ:2885657384
  • M25P128-VMF6TPB图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • M25P128-VMF6TPB 现货库存
  • 数量7960 
  • 厂家Micron 
  • 封装SOP16 
  • 批号24+ 
  • 假一罚万!专业内存、储存、闪存
  • QQ:3007947169QQ:3007947169 复制
    QQ:3007947210QQ:3007947210 复制
  • 755-83950895 QQ:3007947169QQ:3007947210
  • M25P128-VMF6TPB图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • M25P128-VMF6TPB 现货库存
  • 数量7960 
  • 厂家Micron 
  • 封装SOP16 
  • 批号24+ 
  • 假一罚万!专业内存、储存、闪存
  • QQ:3003818780QQ:3003818780 复制
    QQ:3003819484QQ:3003819484 复制
  • 0755-83950895 QQ:3003818780QQ:3003819484
  • M25P128-VMF6TPB图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • M25P128-VMF6TPB 现货库存
  • 数量186 
  • 厂家Numonyx Memory Solutions 
  • 封装 
  • 批号21+ 
  • 原装特价可提供13点
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • M25P128-VMF6TPB图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • M25P128-VMF6TPB 现货库存
  • 数量7510 
  • 厂家MICRON 
  • 封装SOP16 
  • 批号22+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • M25P128-VMF6TP图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • M25P128-VMF6TP 现货库存
  • 数量26800 
  • 厂家ST 
  • 封装SOP-16 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • M25P128-VMF6TP图
  • 深圳市恒嘉威智能科技有限公司

     该会员已使用本站7年以上
  • M25P128-VMF6TP 现货库存
  • 数量14324 
  • 厂家MICRON/美光 
  • 封装SOP16 
  • 批号21+ 
  • 原装恒嘉威价格最实在
  • QQ:1036846627QQ:1036846627 复制
    QQ:2274045202QQ:2274045202 复制
  • -0755-23942980 QQ:1036846627QQ:2274045202
  • M25P128-VMF6TP图
  • 深圳市楷兴电子科技有限公司

     该会员已使用本站7年以上
  • M25P128-VMF6TP 现货库存
  • 数量36860 
  • 厂家ST 
  • 封装SOP16 
  • 批号21+ 
  • 全新进口原装现货,代理渠道假一赔十
  • QQ:2881475151QQ:2881475151 复制
  • 0755-83016042 QQ:2881475151
  • M25P128-VMF6TP图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • M25P128-VMF6TP 现货库存
  • 数量6980 
  • 厂家MICRON 
  • 封装SOP-16 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • M25P128-VMF6TPB图
  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • M25P128-VMF6TPB 现货库存
  • 数量1433 
  • 厂家SOP16 
  • 封装2019+ 
  • 批号24+ 
  • 全新原装,特价,假一罚十
  • QQ:354696650QQ:354696650 复制
    QQ:2850471056QQ:2850471056 复制
  • 0755-89587732 QQ:354696650QQ:2850471056
  • M25P128-VMF6TP图
  • 深圳市力拓辉电子有限公司

     该会员已使用本站13年以上
  • M25P128-VMF6TP 现货库存
  • 数量90000 
  • 厂家ST 
  • 封装SOP16 
  • 批号1445+ 
  • 全新原装特价热卖中
  • QQ:2881140004QQ:2881140004 复制
    QQ:2881140005QQ:2881140005 复制
  • 755-82787180 QQ:2881140004QQ:2881140005
  • M25P128-VMF6TPB【优势库存】图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TPB【优势库存】 优势库存
  • 数量16000 
  • 厂家Micron Technology Inc 
  • 封装16-SO W 
  • 批号24+ 
  • 详情 www.szolxd.com/chanpin/187330.html
  • QQ:1950791264QQ:1950791264 复制
    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • M25P128-VMF6TP图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • M25P128-VMF6TP
  • 数量5300 
  • 厂家ST(意法) 
  • 封装 
  • 批号21+ 
  • 全新原装正品,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • M25P128-VMF6TP图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • M25P128-VMF6TP
  • 数量13880 
  • 厂家MICRON/镁光 
  • 封装SOP16 
  • 批号21+ 
  • 公司只售原装 支持实单
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • M25P128-VMF6TP图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • M25P128-VMF6TP
  • 数量65000 
  • 厂家ST 
  • 封装SOP16 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • M25P128-VMF6TPB图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • M25P128-VMF6TPB
  • 数量20452 
  • 厂家NUMONYX 
  • 封装SOP 
  • 批号24+ 
  • 原装原厂 现货现卖
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • M25P128-VMF6TP图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • M25P128-VMF6TP
  • 数量90000 
  • 厂家MICRON 
  • 封装SOP-16 
  • 批号2018+ 
  • 专营MICRON进口原装正品假一赔十可開17增值稅票
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • M25P128-VMF6TPB图
  • 深圳市隆亿诚科技有限公司

     该会员已使用本站3年以上
  • M25P128-VMF6TPB
  • 数量3253 
  • 厂家MRON/镁光 
  • 封装SOP16 
  • 批号22+ 
  • 支持检测.现货价优!
  • QQ:778039761QQ:778039761 复制
  • -0755-82710221 QQ:778039761
  • M25P128-VMF6TPB图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TPB
  • 数量6000 
  • 厂家NUMONYX 
  • 封装SOP-16 
  • 批号25+ 
  • 全新原装公司现货销售
  • QQ:1245773710QQ:1245773710 复制
    QQ:867789136QQ:867789136 复制
  • 0755-82772189 QQ:1245773710QQ:867789136
  • M25P128-VMF6TPB图
  • 深圳市中利达电子科技有限公司

     该会员已使用本站11年以上
  • M25P128-VMF6TPB
  • 数量10000 
  • 厂家MICRON/美光 
  • 封装SOP16 
  • 批号24+ 
  • 原装进口现货 假一罚十
  • QQ:1902134819QQ:1902134819 复制
    QQ:2881689472QQ:2881689472 复制
  • 0755-13686833545 QQ:1902134819QQ:2881689472
  • M25P128-VMF6TP图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TP
  • 数量3800 
  • 厂家Micron 
  • 封装16-SOIC 
  • 批号24+ 
  • 授权分销 现货热卖
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084
  • M25P128-VMF6TPB图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TPB
  • 数量5321 
  • 厂家MICRON 
  • 封装SOP16 
  • 批号24+ 
  • 全新原装现货,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • M25P128-VMF6TP图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • M25P128-VMF6TP
  • 数量3000 
  • 厂家ST 
  • 封装SOP16 
  • 批号25+ 
  • 全新原装正品现货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • M25P128-VMF6TP图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • M25P128-VMF6TP
  • 数量4500 
  • 厂家STM 
  • 封装SOP16 
  • 批号25+ 
  • 全新原装现货特价销售!
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82723761 QQ:867789136QQ:1245773710
  • M25P128-VMF6TPB图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • M25P128-VMF6TPB
  • 数量14500 
  • 厂家MICRON/美光 
  • 封装SOP-16 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • M25P128-VMF6TP图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TP
  • 数量3500 
  • 厂家ST 
  • 封装SOP16 
  • 批号21+ 
  • 原装正品,公司现货
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • M25P128-VMF6TP图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • M25P128-VMF6TP
  • 数量3500 
  • 厂家ST 
  • 封装SOP16 
  • 批号21+ 
  • 原装正品,公司现货
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 96-010-62104931 QQ:2880824479QQ:1344056792
  • M25P128-VMF6TP图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • M25P128-VMF6TP
  • 数量10 
  • 厂家ST/意法 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • M25P128-VMF6TP图
  • 集好芯城

     该会员已使用本站13年以上
  • M25P128-VMF6TP
  • 数量15414 
  • 厂家ST 
  • 封装SOP16 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • M25P128-VMF6TP图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • M25P128-VMF6TP
  • 数量11531 
  • 厂家恆憶(NMX/NUMONYX)半導體股份有 
  • 封装SOP16 
  • 批号23+ 
  • 全新原装正品现货特价
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • M25P128-VMF6TP TR图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • M25P128-VMF6TP TR
  • 数量3715 
  • 厂家Micron 
  • 封装16-SOIC(0.295,7.50mm 宽) 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • M25P128-VMF6TPB图
  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • M25P128-VMF6TPB
  • 数量128000 
  • 厂家MICRON 
  • 封装SOP16 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 0755-82807802 QQ:528164397QQ:1318502189
  • M25P128-VMF6TPB图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • M25P128-VMF6TPB
  • 数量12842 
  • 厂家MICRON 
  • 封装SOP16 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • M25P128-VMF6TP图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • M25P128-VMF6TP
  • 数量35000 
  • 厂家ST 
  • 封装SOP16 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
  • QQ:1091796029QQ:1091796029 复制
    QQ:916896414QQ:916896414 复制
  • 0755-82772151 QQ:1091796029QQ:916896414
  • M25P128-VMF6TP图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • M25P128-VMF6TP
  • 数量13740 
  • 厂家ST 
  • 封装SOP16 
  • 批号23+ 
  • 全新原装正品现货特价
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • M25P128-VMF6TPB图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • M25P128-VMF6TPB
  • 数量28500 
  • 厂家MICRON/美光 
  • 封装SOP16 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495

产品型号M25P128-VMF6TP的概述

M25P128-VMF6TP 芯片概述 M25P128-VMF6TP是一款由意法半导体(STMicroelectronics)生产的串行NOR闪存芯片,广泛应用于嵌入式系统、消费电子、工业设备等领域。该芯片具有高性能、低功耗和可靠的数据存储能力,适用于需要快速、随机存取存储的应用场景。 M25P128的“128”表示其存储容量为128Mb(即16MB),而“VMF6TP”则表明其特定封装类型和工作温度范围。该芯片支持多种接口命令,便于与多种微处理器、微控制器及其他数字电路进行接口连接。 芯片详细参数 M25P128-VMF6TP的详细参数包括但不限于以下几个方面: 1. 存储容量:128Mb (16MB) 2. 接口类型:SPI (Serial Peripheral Interface) 3. 工作电压:2.7V至3.6V 4. 读速度:高达85MHz 5. 编程时间:最大持续时间为0...

产品型号M25P128-VMF6TP的Datasheet PDF文件预览

M25P128  
128 Mbit (Multilevel), low-voltage, Serial Flash memory  
with 50-MHz SPI bus interface  
Feature summary  
128 Mbit of Flash memory  
2.7 to 3.6 V single supply voltage  
SPI bus compatible Serial interface  
50 MHz clock rate (maximum)  
VDFPN8 (ME)  
8x6mm (MLP8)  
V = 9 V for fast Program/Erase mode  
PP  
(optional)  
Page Program (up to 256 Bytes):  
– in 2.5 ms (typical)  
– in 1.2 ms (typical with V = 9 V)  
PP  
Sector Erase (2 Mbit)  
Bulk Erase (128 Mbit)  
Electronic signature  
SO16 (MF)  
300 mils width  
– JEDEC standard two-byte signature  
(2018h)  
More than 10000 Erase/Program cycles per  
sector  
More than 20-year data retention  
Packages  
– ECOPACK® (RoHS compliant)  
December 2007  
Rev 3  
1/45  
www.numonyx.com  
1
Contents  
M25P128  
Contents  
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . . 9  
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
4.8  
Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12  
Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
6.1  
6.2  
6.3  
6.4  
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
6.4.1  
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
2/45  
M25P128  
Contents  
6.4.2  
6.4.3  
6.4.4  
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
6.5  
6.6  
6.7  
6.8  
6.9  
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27  
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
7
8
9
10  
11  
12  
13  
3/45  
List of tables  
M25P128  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm,  
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 42  
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Table 16.  
Table 17.  
Table 18.  
4/45  
M25P128  
List of figures  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21  
Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23  
Figure 12. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26  
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out sequence . . . 27  
Figure 15. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Figure 16. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Figure 17. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Figure 21. Write Protect setup and hold timing during WRSR when SRWD =1 . . . . . . . . . . . . . . . . . 39  
Figure 22. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Figure 23. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 24.  
V
timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
PPH  
Figure 25. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, package outline. 41  
Figure 26. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 42  
5/45  
Summary description  
M25P128  
1
Summary description  
The M25P128 is a 128 Mbit (16 Mbit × 8), multilevel Serial Flash memory, with advanced  
write protection mechanisms, accessed by a high speed SPI-compatible bus.  
The memory can be programmed 1 to 256 bytes at a time, using the Page Program  
instruction.  
The memory is organized as 64 sectors, each containing 1024 pages. Each page is 256  
bytes wide. Thus, the whole memory can be viewed as consisting of 65536 pages, or  
16777216 bytes.  
An enhanced Fast Program/Erase mode is available to speed up operations in factory  
environment. The device enters this mode whenever the V  
voltage is applied to the Write  
PPH  
Protect/Enhanced Program Supply Voltage pin (W/V ).  
PP  
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,  
using the Sector Erase instruction.  
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®  
packages. ECOPACK® packages are Lead-free and RoHS compliant.  
Figure 1.  
Logic diagram  
V
CC  
D
C
S
Q
M25P128  
W/V  
PP  
HOLD  
V
SS  
AI11313b  
Table 1.  
Signal names  
Serial Clock  
Serial Data Input  
C
D
Q
Serial Data Output  
Chip Select  
S
W/VPP  
HOLD  
VCC  
VSS  
Write Protect/Enhanced Program supply voltage  
Hold  
Supply Voltage  
Ground  
6/45  
M25P128  
Summary description  
Figure 2.  
VDFPN connections  
M25P128  
S
1
2
3
4
8
7
6
5
V
CC  
HOLD  
Q
W/V  
C
D
PP  
V
SS  
AI11314b  
1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS  
,
and must not be allowed to be connected to any other voltage or signal line on the PCB.  
2. See Package mechanical section for package dimensions, and how to identify pin-1.  
Figure 3.  
SO connections  
M25P128  
HOLD  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
C
V
D
CC  
DU  
DU  
DU  
DU  
DU  
DU  
DU  
DU  
S
V
SS  
W/V  
Q
PP  
AI11315b  
1. DU = Don’t Use  
2. See Package mechanical section for package dimensions, and how to identify pin-1.  
7/45  
Signal description  
M25P128  
2
Signal description  
2.1  
Serial data output (Q)  
This output signal is used to transfer data serially out of the device. Data is shifted out on the  
falling edge of Serial Clock (C).  
2.2  
2.3  
2.4  
Serial data input (D)  
This input signal is used to transfer data serially into the device. It receives instructions,  
addresses, and the data to be programmed. Values are latched on the rising edge of Serial  
Clock (C).  
Serial clock (C)  
This input signal provides the timing of the serial interface. Instructions, addresses, or data  
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on  
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).  
Chip Select (S)  
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high  
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,  
the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the  
device, placing it in the Active Power mode.  
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any  
instruction.  
2.5  
Hold (HOLD)  
The Hold (HOLD) signal is used to pause any serial communications with the device without  
deselecting the device.  
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data  
Input (D) and Serial Clock (C) are Don’t Care.  
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.  
8/45  
M25P128  
Signal description  
2.6  
Write Protect/Enhanced Program supply voltage (W/VPP)  
W/V is both a control input and a power supply pin. The two functions are selected by the  
PP  
voltage range applied to the pin.  
If the W/V input is kept in a low voltage range (0V to V ) the pin is seen as a control  
PP  
CC  
input. This input signal is used to freeze the size of the area of memory that is protected  
against program or erase instructions (as specified by the values in the BP2, BP1 and BP0  
bits of the Status Register).  
If V is in the range of V  
it acts as an additional power supply pin. In this case V must  
PP  
PP  
PPH  
be stable until the Program/Erase algorithm is completed.  
2.7  
2.8  
VCC supply voltage  
V
is the supply voltage.  
CC  
VSS ground  
V
is the reference for the V supply voltage.  
CC  
SS  
9/45  
SPI modes  
M25P128  
3
SPI modes  
These devices can be driven by a microcontroller with its SPI peripheral running in either of  
the two following modes:  
CPOL=0, CPHA=0  
CPOL=1, CPHA=1  
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and  
output data is available from the falling edge of Serial Clock (C).  
The difference between the two modes, as shown in Figure 5, is the clock polarity when the  
bus master is in Stand-by mode and not transferring data:  
C remains at 0 for (CPOL=0, CPHA=0)  
C remains at 1 for (CPOL=1, CPHA=1)  
Figure 4.  
Bus master and memory devices on the SPI bus  
V
V
SS  
CC  
(2)  
R
SDO  
SPI Interface with  
(CPOL, CPHA) =  
(0, 0) or (1, 1)  
SDI  
SCK  
V
V
V
CC  
C
Q
D
C
Q
D
C Q D  
CC  
CC  
V
V
V
SS  
SS  
SS  
SPI bus master  
(2)  
(2)  
(2)  
SPI memory  
device  
SPI memory  
device  
SPI memory  
device  
R
R
R
CS3 CS2 CS1  
S
W/V  
HOLD  
S
W/V  
HOLD  
S
W/V  
HOLD  
PP  
PP  
PP  
AI12836  
1. The Write Protect (W/VPP) and Hold (HOLD) signals should be driven, High or Low as appropriate.  
2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-  
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time  
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all  
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become  
High at the same time, and so, that the tSHCH requirement is met).  
10/45  
M25P128  
Figure 5.  
SPI modes  
SPI modes supported  
CPOL CPHA  
C
C
0
1
0
1
D
MSB  
Q
MSB  
AI01438B  
11/45  
Operating features  
M25P128  
4
Operating features  
4.1  
Page programming  
To program one data byte, two instructions are required: Write Enable (WREN), which is one  
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is  
followed by the internal Program cycle (of duration t ).  
PP  
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be  
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive  
addresses on the same page of memory.  
For optimized timings, it is recommended to use the Page Program (PP) instruction to  
program all consecutive targeted Bytes in a single sequence versus using several Page  
Program (PP) sequences with each containing only a few Bytes (see Section 6.8: Page  
Program (PP) and Table 14: AC characteristics).  
4.2  
Sector Erase and Bulk Erase  
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be  
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be  
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the  
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of  
duration t or t ).  
SE  
BE  
The Erase instruction must be preceded by a Write Enable (WREN) instruction.  
4.3  
4.4  
Polling during a write, program or erase cycle  
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase  
(SE or BE) can be achieved by not waiting for the worst case delay (t , t , t , or t ). The  
W
PP SE  
BE  
Write In Progress (WIP) bit is provided in the Status Register so that the application program  
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or  
Erase cycle is complete.  
Fast Program/Erase mode  
The Fast Program/Erase mode is used to speed up programming/erasing. The device  
enters the Fast Program/Erase mode during the Page Program, Sector Erase or Bulk Erase  
instruction whenever a voltage equal to V  
is applied to the W/V pin.  
PPH  
PP  
The use of the Fast Program/Erase mode requires specific operating conditions in addition  
to the normal ones (V must be within the normal operating range):  
CC  
the voltage applied to the W/V pin must be equal to V  
(see Table 10)  
PP  
PPH  
ambient temperature, T must be 25°C 10°C,  
A
the cumulated time during which W/V is at V  
should be less than 80 hours  
PPH  
PP  
12/45  
M25P128  
Operating features  
4.5  
Active power and standby power modes  
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.  
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power  
mode until all internal cycles have completed (Program, Erase, Write Status Register). The  
device then goes in to the Standby Power mode. The device consumption drops to I  
.
CC1  
4.6  
4.7  
Status Register  
The Status Register contains a number of status and control bits that can be read or set (as  
appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a  
detailed description of the Status Register bits.  
Protection modes  
The environments where non-volatile memory devices are used can be very noisy. No SPI  
device can operate correctly in the presence of excessive noise. To help combat this, the  
M25P128 features the following data protection mechanisms:  
Power On Reset and an internal timer (t  
) can provide protection against inadvertent  
PUW  
changes while the power supply is outside the operating specification.  
Program, Erase and Write Status Register instructions are checked that they consist of  
a number of clock pulses that is a multiple of eight, before they are accepted for  
execution.  
All instructions that modify data must be preceded by a Write Enable (WREN)  
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state  
by the following events:  
Power-up  
Write Disable (WRDI) instruction completion  
Write Status Register (WRSR) instruction completion  
Page Program (PP) instruction completion  
Sector Erase (SE) instruction completion  
Bulk Erase (BE) instruction completion  
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as  
read-only. This is the Software Protected Mode (SPM).  
The Write Protect (W/V ) signal allows the Block Protect (BP2, BP1, BP0) bits and  
PP  
Status Register Write Disable (SRWD) bit to be protected. This is the Hardware  
Protected Mode (HPM).  
13/45  
Operating features  
Table 2.  
M25P128  
Protected area sizes  
Status Register content  
BP2 Bit BP1 Bit BP0 Bit  
Memory content  
Protected area  
Unprotected area  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none  
All Sectors (Sectors 0 to 63)(1)  
Sectors 0 to 62  
Upper 64th (1 Sector, 2Mb)  
Upper 32nd (2 Sectors, 4Mb)  
Upper 16nd (4 Sectors, 8Mb)  
Upper 8nd (8 Sectors, 16Mb)  
Sectors 0 to 61  
Sectors 0 to 59  
Sectors 0 to 55  
Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47)  
Upper Half (32 Sectors, 64Mb)  
All sectors (64 Sectors, 128Mb)  
Lower Half (Sectors 0 to 31)  
none  
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.  
4.8  
Hold condition  
The Hold (HOLD) signal is used to pause any serial communications with the device without  
resetting the clocking sequence. However, taking this signal Low does not terminate any  
Write Status Register, Program or Erase cycle that is currently in progress.  
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.  
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this  
coincides with Serial Clock (C) being Low (as shown in Figure 6).  
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this  
coincides with Serial Clock (C) being Low.  
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition  
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide  
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes  
Low. (This is shown in Figure 6).  
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data  
Input (D) and Serial Clock (C) are Don’t Care.  
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration  
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged  
from the moment of entering the Hold condition.  
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of  
resetting the internal logic of the device. To restart communication with the device, it is  
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents  
the device from going back to the Hold condition.  
14/45  
M25P128  
Operating features  
Figure 6.  
Hold condition activation  
C
HOLD  
Hold  
Hold  
Condition  
Condition  
(standard use)  
(non-standard use)  
AI02029D  
15/45  
Memory organization  
M25P128  
5
Memory organization  
The memory is organized as:  
16777216 bytes (8 bits each)  
64 sectors (2 Mbits, 262144 bytes each)  
65536 pages (256 bytes each).  
Each page can be individually programmed (bits are programmed from 1 to 0). The device is  
Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.  
Figure 7.  
Block diagram  
HOLD  
High Voltage  
W/V  
Control Logic  
Generator  
PP  
S
C
D
Q
I/O Shift Register  
Status  
Register  
Address Register  
and Counter  
256 Byte  
Data Buffer  
FFFFFFh  
Size of the  
read-only  
memory area  
00000h  
000FFh  
256 Bytes (Page Size)  
X Decoder  
AI11316b  
16/45  
M25P128  
Memory organization  
Table 3.  
Memory organization  
Sector  
Address Range  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
FC0000h  
F80000h  
F40000h  
F00000h  
EC0000h  
E80000h  
E40000h  
E00000h  
DC0000h  
D80000h  
D40000h  
D00000h  
CC0000h  
C80000h  
C40000h  
C00000h  
BC0000h  
B80000h  
B40000h  
B00000h  
AC0000h  
A80000h  
A40000h  
A00000h  
9C0000h  
980000h  
940000h  
900000h  
8C0000h  
880000h  
840000h  
800000h  
7C0000h  
780000h  
740000h  
FFFFFFh  
FBFFFFh  
F7FFFFh  
F3FFFFh  
EFFFFFh  
EBFFFFh  
E7FFFFh  
E3FFFFh  
DFFFFFh  
DBFFFFh  
D7FFFFh  
D3FFFFh  
CFFFFFh  
CBFFFFh  
C7FFFFh  
C3FFFFh  
BFFFFFh  
BBFFFFh  
B7FFFFh  
B3FFFFh  
AFFFFFh  
ABFFFFh  
A7FFFFh  
A3FFFFh  
9FFFFFh  
9BFFFFh  
97FFFFh  
93FFFFh  
8FFFFFh  
8BFFFFh  
87FFFFh  
83FFFFh  
7FFFFFh  
7BFFFFh  
77FFFFh  
17/45  
Memory organization  
Table 3.  
M25P128  
Memory organization (continued)  
Sector  
Address Range  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
700000h  
6C0000h  
680000h  
640000h  
600000h  
5C0000h  
580000h  
540000h  
500000h  
4C0000h  
480000h  
440000h  
400000h  
3C0000h  
380000h  
340000h  
300000h  
2C0000h  
280000h  
240000h  
200000h  
1C0000h  
180000h  
140000h  
100000h  
0C0000h  
080000h  
040000h  
000000h  
73FFFFh  
6FFFFFh  
6BFFFFh  
67FFFFh  
63FFFFh  
5FFFFFh  
5BFFFFh  
57FFFFh  
53FFFFh  
4FFFFFh  
4BFFFFh  
47FFFFh  
43FFFFh  
3FFFFFh  
3BFFFFh  
37FFFFh  
33FFFFh  
2FFFFFh  
2BFFFFh  
27FFFFh  
23FFFFh  
1FFFFFh  
1BFFFFh  
17FFFFh  
13FFFFh  
0FFFFFh  
0BFFFFh  
07FFFFh  
03FFFFh  
8
7
6
5
4
3
2
1
0
18/45  
M25P128  
Instructions  
6
Instructions  
All instructions, addresses and data are shifted in and out of the device, most significant bit  
first.  
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select  
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most  
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of  
Serial Clock (C).  
The instruction set is listed in Table 4.  
Every instruction sequence starts with a one-byte instruction code. Depending on the  
instruction, this might be followed by address bytes, or by data bytes, or by both or none.  
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),  
Read Status Register (RDSR) or Read Identification (RDID) instruction, the shifted-in  
instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High  
after any bit of the data-out sequence is being shifted out.  
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status  
Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be  
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not  
executed. That is, Chip Select (S) must driven High when the number of clock pulses after  
Chip Select (S) being driven Low is an exact multiple of eight.  
All attempts to access the memory array during a Write Status Register cycle, Program  
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program  
cycle or Erase cycle continues unaffected.  
Table 4.  
Instruction set  
Description  
One-byte Instruction Address Dummy  
Data  
Instruction  
Code  
Bytes  
Bytes  
Bytes  
WREN  
WRDI  
RDID  
Write Enable  
0000 0110  
06h  
04h  
9Fh  
05h  
01h  
03h  
0
0
0
0
0
3
0
0
0
0
0
0
0
Write Disable  
0000 0100  
1001 1111  
0000 0101  
0000 0001  
0000 0011  
0
Read Identification  
Read Status Register  
Write Status Register  
Read Data Bytes  
1 to 3  
1 to  
1
RDSR  
WRSR  
READ  
1 to ∞  
Read Data Bytes at Higher  
Speed  
FAST_READ  
0000 1011  
0Bh  
3
1
1 to ∞  
PP  
SE  
BE  
Page Program  
Sector Erase  
Bulk Erase  
0000 0010  
1101 1000  
1100 0111  
02h  
D8h  
C7h  
3
3
0
0
0
0
1 to 256  
0
0
19/45  
Instructions  
M25P128  
6.1  
Write Enable (WREN)  
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.  
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector  
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.  
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the  
instruction code, and then driving Chip Select (S) High.  
Figure 8.  
Write Enable (WREN) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI02281E  
6.2  
Write Disable (WRDI)  
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.  
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the  
instruction code, and then driving Chip Select (S) High.  
The Write Enable Latch (WEL) bit is reset under the following conditions:  
Power-up  
Write Disable (WRDI) instruction completion  
Write Status Register (WRSR) instruction completion  
Page Program (PP) instruction completion  
Sector Erase (SE) instruction completion  
Bulk Erase (BE) instruction completion  
Figure 9.  
Write Disable (WRDI) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction  
High Impedance  
AI03750D  
20/45  
M25P128  
Instructions  
6.3  
Read Identification (RDID)  
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be  
read, followed by two bytes of device identification. The manufacturer identification is  
assigned by JEDEC, and has the value 20h for Numonyx. The device identification is  
assigned by the device manufacturer, and indicates the memory type in the first byte (20h),  
and the memory capacity of the device in the second byte (18h).  
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is  
not decoded, and has no effect on the cycle that is in progress.  
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code  
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in  
the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during  
the falling edge of Serial Clock (C).  
The instruction sequence is shown in Figure 10.  
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at  
any time during data output.  
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in  
the Standby Power mode, the device waits to be selected, so that it can receive, decode and  
execute instructions.  
Table 5.  
Read Identification (RDID) data-out sequence  
Device Identification  
Manufacturer Identification  
Memory Type  
Memory Capacity  
20h  
20h  
18h  
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence  
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18  
28 29 30 31  
C
D
Instruction  
Manufacturer Identification  
Device Identification  
High Impedance  
Q
15 14 13  
MSB  
3
2
1
0
MSB  
AI06809b  
21/45  
Instructions  
M25P128  
6.4  
Read Status Register (RDSR)  
The Read Status Register (RDSR) instruction allows the Status Register to be read. The  
Status Register may be read at any time, even while a Program, Erase or Write Status  
Register cycle is in progress. When one of these cycles is in progress, it is recommended to  
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is  
also possible to read the Status Register continuously, as shown in Figure 11.  
Table 6.  
Status Register format  
b7  
b0  
SRWD  
0
0
BP2  
BP1  
BP0  
WEL  
WIP  
Status Register Write Protect  
Block Protect Bits  
Write Enable Latch Bit  
Write In Progress Bit  
The status and control bits of the Status Register are as follows:  
6.4.1  
6.4.2  
6.4.3  
WIP bit  
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status  
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to  
0 no such cycle is in progress.  
WEL bit  
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.  
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable  
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.  
BP2, BP1, BP0 bits  
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to  
be software protected against Program and Erase instructions. These bits are written with  
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,  
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes  
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect  
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not  
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,  
BP1, BP0) bits are 0.  
6.4.4  
SRWD bit  
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write  
Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and Write Protect  
PP  
(W/V ) signal allow the device to be put in the Hardware Protected mode (when the Status  
PP  
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V ) is driven Low). In  
PP  
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become  
22/45  
M25P128  
Instructions  
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for  
execution.  
Figure 11. Read Status Register (RDSR) instruction sequence and data-out  
sequence  
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15  
C
D
Instruction  
Status Register Out  
Status Register Out  
High Impedance  
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB  
MSB  
AI02031E  
23/45  
Instructions  
M25P128  
6.5  
Write Status Register (WRSR)  
The Write Status Register (WRSR) instruction allows new values to be written to the Status  
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously  
have been executed. After the Write Enable (WREN) instruction has been decoded and  
executed, the device sets the Write Enable Latch (WEL).  
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,  
followed by the instruction code and the data byte on Serial Data Input (D).  
The instruction sequence is shown in Figure 12.  
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the  
Status Register. b6 and b5 are always read as 0.  
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.  
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select  
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t ) is  
W
initiated. While the Write Status Register cycle is in progress, the Status Register may still  
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)  
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.  
When the cycle is completed, the Write Enable Latch (WEL) is reset.  
The Write Status Register (WRSR) instruction allows the user to change the values of the  
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as  
read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows  
the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the  
Write Protect (W/V ) signal. The Status Register Write Disable (SRWD) bit and Write  
PP  
Protect (W/V ) signal allow the device to be put in the Hardware Protected Mode (HPM).  
PP  
The Write Status Register (WRSR) instruction is not executed once the Hardware Protected  
Mode (HPM) is entered.  
Table 7.  
Protection modes  
Memory Content  
W/VPP SRWD  
Write Protection of the  
Status Register  
Mode  
Signal  
Bit  
Protected Area(1) Unprotected Area(1)  
1
0
0
0
Status Register is Writable  
(if the WREN instruction  
has set the WEL bit)  
Protected against Ready to accept  
Software  
Protected  
(SPM)  
Page Program,  
Sector Erase and  
Bulk Erase  
Page Program and  
Sector Erase  
instructions  
The values in the SRWD,  
BP2, BP1 and BP0 bits  
can be changed  
1
1
Status Register is  
Hardware write protected  
Protected against Ready to accept  
Hardware  
Protected  
(HPM)  
Page Program,  
Sector Erase and  
Bulk Erase  
Page Program and  
Sector Erase  
instructions  
0
1
The values in the SRWD,  
BP2, BP1 and BP0 bits  
cannot be changed  
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in  
Table 2: Protected area sizes.  
The protection features of the device are summarized in Table 7  
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial  
delivery state), it is possible to write to the Status Register provided that the Write Enable  
24/45  
M25P128  
Instructions  
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless  
of the whether Write Protect (W/V ) is driven High or Low.  
PP  
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two  
cases need to be considered, depending on the state of Write Protect (W/V ):  
PP  
If Write Protect (W/V ) is driven High, it is possible to write to the Status Register  
PP  
provided that the Write Enable Latch (WEL) bit has previously been set by a Write  
Enable (WREN) instruction.  
If Write Protect (W/V ) is driven Low, it is not possible to write to the Status Register  
PP  
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable  
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not  
accepted for execution). As a consequence, all the data bytes in the memory area that  
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status  
Register, are also hardware protected against data modification.  
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be  
entered:  
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect  
(W/V ) Low  
PP  
or by driving Write Protect (W/V ) Low after setting the Status Register Write Disable  
PP  
(SRWD) bit.  
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write  
Protect (W/V ) High.  
PP  
If Write Protect (W/V ) is permanently tied High, the Hardware Protected Mode (HPM) can  
PP  
never be activated, and only the Software Protected Mode (SPM), using the Block Protect  
(BP2, BP1, BP0) bits of the Status Register, can be used.  
Figure 12. Write Status Register (WRSR) instruction sequence  
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
C
Instruction  
Status  
Register In  
7
6
5
4
3
2
0
1
D
Q
High Impedance  
MSB  
AI02282D  
25/45  
Instructions  
M25P128  
6.6  
Read Data Bytes (READ)  
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read  
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being  
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that  
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum  
frequency f , during the falling edge of Serial Clock (C).  
R
The instruction sequence is shown in Figure 13.  
The first byte addressed can be at any location. The address is automatically incremented  
to the next higher address after each byte of data is shifted out. The whole memory can,  
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest  
address is reached, the address counter rolls over to 000000h, allowing the read sequence  
to be continued indefinitely.  
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip  
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)  
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having  
any effects on the cycle that is in progress.  
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39  
C
Instruction  
24-Bit Address  
23 22 21  
MSB  
3
2
1
0
D
Q
Data Out 1  
Data Out 2  
High Impedance  
2
7
6
5
4
3
1
7
0
MSB  
AI03748D  
26/45  
M25P128  
Instructions  
6.7  
Read Data Bytes at Higher Speed (FAST_READ)  
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read  
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-  
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).  
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each  
bit being shifted out, at a maximum frequency f , during the falling edge of Serial Clock (C).  
C
The instruction sequence is shown in Figure 14.  
The first byte addressed can be at any location. The address is automatically incremented  
to the next higher address after each byte of data is shifted out. The whole memory can,  
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)  
instruction. When the highest address is reached, the address counter rolls over to  
000000h, allowing the read sequence to be continued indefinitely.  
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving  
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any  
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or  
Write cycle is in progress, is rejected without having any effects on the cycle that is in  
progress.  
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out  
sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31  
C
Instruction  
24 BIT ADDRESS  
23 22 21  
3
2
1
0
D
Q
High Impedance  
S
C
47  
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46  
Dummy Byte  
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2  
DATA OUT 1  
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB  
MSB  
MSB  
AI04006  
27/45  
Instructions  
M25P128  
6.8  
Page Program (PP)  
The Page Program (PP) instruction allows bytes to be programmed in the memory  
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction  
must previously have been executed. After the Write Enable (WREN) instruction has been  
decoded, the device sets the Write Enable Latch (WEL).  
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by  
the instruction code, three address bytes and at least one data byte on Serial Data Input (D).  
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes  
beyond the end of the current page are programmed from the start address of the same  
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)  
must be driven Low for the entire duration of the sequence. The instruction sequence is  
shown in Figure 15.  
If more than 256 bytes are sent to the device, previously latched data are discarded and the  
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less  
than 256 Data bytes are sent to device, they are correctly programmed at the requested  
addresses without having any effects on the other bytes of the same page.  
For optimized timings, it is recommended to use the Page Program (PP) instruction to  
program all consecutive targeted Bytes in a single sequence versus using several Page  
Program (PP) sequences with each containing only a few Bytes (see Table 14: AC  
characteristics).  
Chip Select (S) must be driven High after the eighth bit of the last data byte has been  
latched in, otherwise the Page Program (PP) instruction is not executed.  
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose  
duration is t ) is initiated. While the Page Program cycle is in progress, the Status Register  
PP  
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress  
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At  
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is  
reset.  
A Page Program (PP) instruction applied to a page which is protected by the Block Protect  
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.  
28/45  
M25P128  
Instructions  
Figure 15. Page Program (PP) instruction sequence  
S
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39  
C
D
Instruction  
24-Bit Address  
Data Byte 1  
23 22 21  
MSB  
3
2
1
0
7
6
5
4
3
2
0
1
MSB  
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55  
Data Byte 2  
Data Byte 3  
Data Byte 256  
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB  
MSB  
MSB  
AI04082B  
29/45  
Instructions  
M25P128  
6.9  
Sector Erase (SE)  
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it  
can be accepted, a Write Enable (WREN) instruction must previously have been executed.  
After the Write Enable (WREN) instruction has been decoded, the device sets the Write  
Enable Latch (WEL).  
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the  
instruction code, and three address bytes on Serial Data Input (D). Any address inside the  
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)  
must be driven Low for the entire duration of the sequence.  
The instruction sequence is shown in Figure 16.  
Chip Select (S) must be driven High after the eighth bit of the last address byte has been  
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip  
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is t ) is  
SE  
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to  
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1  
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified  
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.  
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect  
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.  
Figure 16. Sector Erase (SE) instruction sequence  
S
0
1
2
3
4
5
6
7
8
9
29 30 31  
C
D
Instruction  
24 Bit Address  
23 22  
MSB  
2
0
1
AI03751D  
30/45  
M25P128  
Instructions  
6.10  
Bulk Erase (BE)  
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write  
Enable (WREN) instruction must previously have been executed. After the Write Enable  
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).  
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the  
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire  
duration of the sequence.  
The instruction sequence is shown in Figure 17.  
Chip Select (S) must be driven High after the eighth bit of the instruction code has been  
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)  
is driven High, the self-timed Bulk Erase cycle (whose duration is t ) is initiated. While the  
BE  
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the  
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk  
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is  
completed, the Write Enable Latch (WEL) bit is reset.  
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are  
0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.  
Figure 17. Bulk Erase (BE) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Instruction  
AI03752D  
31/45  
Power-up and power-down  
M25P128  
7
Power-up and power-down  
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must  
follow the voltage applied on V ) until V reaches the correct value:  
CC  
CC  
V
V
(min) at Power-up, and then for a further delay of t  
at Power-down  
CC  
SS  
VSL  
Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper  
Power-up and Power-down.  
To avoid data corruption and inadvertent write operations during Power-up, a Power On  
Reset (POR) circuit is included. The logic inside the device is held reset while V is less  
CC  
than the Power On Reset (POR) threshold voltage, V – all operations are disabled, and  
WI  
the device does not respond to any instruction.  
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase  
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of  
t
has elapsed after the moment that V rises above the V threshold. However, the  
PUW  
CC WI  
correct operation of the device is not guaranteed if, by this time, V is still below V (min).  
CC  
CC  
No Write Status Register, Program or Erase instructions should be sent until the later of:  
t
t
after V passed the V threshold  
CC WI  
PUW  
VSL  
after V passed the V (min) level  
CC  
CC  
These values are specified in Table 8.  
If the delay, t  
, has elapsed, after V has risen above V (min), the device can be  
VSL  
CC  
CC  
selected for READ instructions even if the t  
delay is not yet fully elapsed.  
PUW  
At Power-up, the device is in the following state:  
The device is in the Standby Power mode  
The Write Enable Latch (WEL) bit is reset.  
Normal precautions must be taken for supply rail decoupling, to stabilize the V supply.  
CC  
Each device in a system should have the V rail decoupled by a suitable capacitor close to  
CC  
the package pins. (Generally, this capacitor is of the order of 0.1µF).  
At Power-down, when V drops from the operating voltage, to below the Power On Reset  
CC  
(POR) threshold voltage, V , all operations are disabled and the device does not respond  
WI  
to any instruction. (The designer needs to be aware that if a Power-down occurs while a  
Write, Program or Erase cycle is in progress, some data corruption can result.)  
Power up sequencing for Fast program/erase mode: V should attain V  
before V  
PPH  
CC  
CCMIN  
is applied.  
32/45  
M25P128  
Initial delivery state  
Figure 18. Power-up timing  
V
CC  
V
(max)  
CC  
Program, Erase and Write Commands are Rejected by the Device  
Chip Selection Not Allowed  
V
(min)  
CC  
tVSL  
Read Access allowed  
Device fully  
accessible  
Reset State  
of the  
Device  
V
WI  
tPUW  
time  
AI04009C  
Table 8.  
Symbol  
Power-Up Timing and V Threshold  
WI  
Parameter  
Min.  
Max.  
Unit  
(1)  
tVSL  
VCC(min) to S Low  
60  
1
µs  
ms  
V
(1)  
tPUW  
Time delay to Write instruction  
Write Inhibit Voltage  
10  
VWI  
1.5  
2.5  
1. These parameters are characterized only.  
8
Initial delivery state  
The device is delivered with the memory array erased: all bits are set to 1 (each byte  
contains FFh). The Status Register contains 00h (all Status Register bits are 0).  
33/45  
Maximum rating  
M25P128  
9
Maximum rating  
Stressing the device outside the ratings listed in Table 9 may cause permanent damage to  
the device. These are stress ratings only, and operation of the device at these, or any other  
conditions outside those indicated in the Operating sections of this specification, is not  
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect  
device reliability. Refer also to the Numonyx SURE Program and other relevant quality  
documents.  
Table 9.  
Symbol  
Absolute maximum ratings  
Parameter  
Min.  
Max.  
Unit  
TSTG  
VIO  
Storage Temperature  
–65  
–0.5  
150  
VCC + 0.6  
4.0  
°C  
V
Input and output voltage (with respect to Ground)  
Supply voltage  
VCC  
VPP  
–0.2  
V
Fast Program/Erase voltage  
–0.2  
10.0  
V
VESD  
Electrostatic Discharge Voltage (Human Body Model) (1)  
–2000  
2000  
V
1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)  
34/45  
M25P128  
DC and AC parameters  
10  
DC and AC parameters  
This section summarizes the operating and measurement conditions, and the DC and AC  
characteristics of the device. The parameters in the DC and AC Characteristic tables that  
follow are derived from tests performed under the Measurement Conditions summarized in  
the relevant tables. Designers should check that the operating conditions in their circuit  
match the measurement conditions when relying on the quoted parameters.  
Table 10. Operating conditions  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
VCC  
Supply Voltage  
2.7  
3.6  
V
Supply Voltage on W/VPP pin for Fast  
Program/Erase mode  
VPPH  
TA  
8.5  
–40  
15  
9.5  
85  
35  
V
Ambient Operating Temperature  
°C  
°C  
Ambient Operating Temperature for Fast  
Program/Erase mode  
TAVPP  
25  
30  
Table 11. AC measurement conditions  
Symbol  
Parameter  
Load Capacitance  
Min.  
Max.  
Unit  
CL  
pF  
ns  
V
Input Rise and Fall Times  
5
Input Pulse Voltages  
0.2VCC to 0.8VCC  
0.3VCC to 0.7VCC  
Input Timing Reference Voltages  
Output Timing Reference Voltages  
V
V
CC / 2  
V
1. Output Hi-Z is defined as the point where data out is no longer driven.  
Figure 19. AC measurement I/O waveform  
Input Levels  
Input and Output  
Timing Reference Levels  
0.8V  
CC  
0.7V  
CC  
0.5V  
CC  
0.3V  
CC  
0.2V  
CC  
AI07455  
Table 12. Capacitance  
Symbol  
Parameter  
Test Condition  
Min.  
Max.  
Unit  
COUT  
CIN  
Output Capacitance (Q)  
VOUT = 0V  
VIN = 0V  
8
6
pF  
pF  
Input Capacitance (other pins)  
1. Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.  
35/45  
DC and AC parameters  
M25P128  
Table 13. DC characteristics  
Test Condition  
Symbol  
Parameter  
Min.  
Max.  
Unit  
(in addition to those in Table 10)  
ILI  
ILO  
Input Leakage Current  
Output Leakage Current  
Standby Current  
2
2
µA  
µA  
µA  
ICC1  
S = VCC, VIN = VSS or VCC  
100  
C = 0.1VCC / 0.9.VCC at 50MHz,  
Q = open  
8
mA  
ICC3  
Operating Current (READ)  
C = 0.1VCC / 0.9.VCC at 20MHz,  
Q = open  
4
mA  
mA  
mA  
ICC4  
ICC5  
Operating Current (PP)  
S = VCC  
S = VCC  
20  
20  
Operating Current  
(WRSR)  
ICC6  
ICC7  
Operating Current (SE)  
Operating Current (BE)  
S = VCC  
S = VCC  
20  
20  
mA  
mA  
Operating current for Fast  
Program/Erase mode  
(1)  
ICCPP  
S = VCC, VPP = VPPH  
S = VCC, VPP = VPPH  
20  
mA  
mA  
VPP Operating current in  
Fast Program/Erase mode  
(1)  
IPP  
20  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
– 0.5  
0.3VCC  
V
V
V
V
0.7VCC VCC+0.2  
0.4  
VOL  
VOH  
IOL = 1.6mA  
IOH = –100μA  
VCC–0.2  
1. Characterized only.  
36/45  
M25P128  
DC and AC parameters  
Table 14. AC characteristics  
Test conditions specified in Table 10 and Table 11  
Symbol  
Alt.  
Parameter  
Min. Typ.  
Max.  
Unit  
Clock Frequency for the following instructions:  
FAST_READ, PP, SE, BE, WREN, WRDI,  
RDID, RDSR, WRSR  
fC  
fR  
fC  
D.C.  
50  
20  
MHz  
Clock Frequency for READ instructions  
D.C.  
9
MHz  
ns  
(1)  
tCH  
tCLH Clock High Time  
tCLL Clock Low Time  
(1)  
tCL  
9
ns  
(2)  
tCLCH  
Clock Rise Time(3) (peak to peak)  
0.1  
0.1  
5
V/ns  
V/ns  
ns  
(2)  
tCHCL  
Clock Fall Time(3) (peak to peak)  
tCSS S Active Setup Time (relative to C)  
S Not Active Hold Time (relative to C)  
tDSU Data In Setup Time  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
5
ns  
2
ns  
tDH  
Data In Hold Time  
5
ns  
S Active Hold Time (relative to C)  
S Not Active Setup Time (relative to C)  
5
ns  
5
ns  
tCSH S Deselect Time  
100  
ns  
(2)  
tSHQZ  
tDIS Output Disable Time  
8
8
ns  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
tV  
tHO Output Hold Time  
HOLD Setup Time (relative to C)  
Clock Low to Output Valid  
ns  
0
5
5
5
5
ns  
ns  
HOLD Hold Time (relative to C)  
HOLD Setup Time (relative to C)  
HOLD Hold Time (relative to C)  
HOLD to Output Low-Z  
ns  
ns  
ns  
(2)  
tHHQX  
tLZ  
8
8
ns  
(2)  
tHLQZ  
tHZ  
HOLD to Output High-Z  
ns  
(4)  
tWHSL  
Write Protect Setup Time  
Write Protect Hold Time  
20  
ns  
(4)  
tSHWL  
100  
ns  
Enhanced Program Supply Voltage High to  
Chip Select Low  
(2)(5)  
tVPPHSL  
tW  
200  
ns  
Write Status Register Cycle Time  
Page Program Cycle Time (256 Bytes)  
Page Program Cycle Time (n Bytes)  
5
15  
7
ms  
2.5  
2.5  
(6)  
tPP  
ms  
s
Page Program Cycle Time (VPP = VPPH) (256  
Bytes)  
1.2(2)  
Sector Erase Cycle Time  
2
tSE  
6
Sector Erase Cycle Time (VPP = VPPH  
)
1.6(2)  
37/45  
DC and AC parameters  
M25P128  
Table 14. AC characteristics (continued)  
Test conditions specified in Table 10 and Table 11  
Symbol  
Alt.  
Parameter  
Min. Typ.  
Max.  
250  
Unit  
Bulk Erase Cycle Time  
105  
tBE  
s
Bulk Erase Cycle Time (VPP = VPPH  
)
56(2)  
1. tCH and tCL must be greater than or equal to 1/fC (max).  
2. Value is guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for WRSR instruction when SRWD is set to 1.  
5. VPPH should be kept at a valid level until the program or erase operation has completed and its result  
(success or failure) is known.  
6. Due to the Multi Level Cell technology, when using the Page Program (PP) instruction to program  
consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus  
several sequences of only a few Bytes. If only a single byte is programmed, the estimated programming  
time is close to the time needed to program a full page of 256 Bytes. Therefore, it is highly recommended  
to use the Page Program (PP) instruction with a sequence of 256 consecutive Bytes. (1 n 256)  
Figure 20. Serial input timing  
tSHSL  
S
tCHSL  
tSLCH  
tCHSH  
tSHCH  
C
tDVCH  
tCHCL  
tCHDX  
tCLCH  
MSB IN  
LSB IN  
D
Q
High Impedance  
AI01447C  
38/45  
M25P128  
DC and AC parameters  
Figure 21. Write Protect setup and hold timing during WRSR when SRWD =1  
W/VPP  
tWHSL  
tSHWL  
S
C
D
High Impedance  
Q
AI07439b  
Figure 22. Hold timing  
S
tHLCH  
tCHHL  
tHLQZ  
tHHCH  
C
tCHHH  
tHHQX  
Q
D
HOLD  
AI02032  
39/45  
DC and AC parameters  
M25P128  
Figure 23. Output timing  
S
tCH  
C
tCLQV  
tCLQV  
tCL  
tSHQZ  
tCLQX  
tCLQX  
LSB OUT  
Q
D
tQLQH  
tQHQL  
ADDR.LSB IN  
AI01449e  
Figure 24. V  
timing  
PPH  
End of PP, SE or BE  
(identified by WPI polling)  
S
C
D
PP, SE, BE  
VPPH  
W/VPP  
ai12092  
tVPPHSL  
40/45  
M25P128  
Package mechanical  
11  
Package mechanical  
Figure 25. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm,  
package outline  
D
E
E2  
e
b
D2  
A
L
L1  
ddd  
A1  
VDFPN-02  
1. Drawing is not to scale.  
2. The circle in the top view of the package indicates the position of pin 1.  
Table 15. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm,  
package mechanical data  
millimeters  
Min.  
inches  
Min.  
Symbol  
Typ.  
Max.  
Typ.  
Max.  
A
A1  
b
0.85  
1.00  
0.05  
0.48  
0.0335  
0.0394  
0.0020  
0.0189  
0.00  
0.35  
0.0000  
0.0138  
0.40  
8.00  
6.40  
0.0157  
0.3150  
0.2520  
D
(1)  
D2  
ddd  
E
0.05  
0.0020  
6.00  
4.80  
1.27  
0.2362  
0.1890  
0.0500  
E2  
e
K
0.20  
0.45  
0.0079  
0.0177  
L
0.50  
0.60  
0.15  
0.0197  
0.0236  
0.0059  
L1  
N
8
8
1. D2 Max should not exceed (D – K – 2 × L).  
41/45  
Package mechanical  
Figure 26. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width  
M25P128  
D
h x 45˚  
C
16  
9
E
H
1
8
θ
A2  
A
A1  
L
ddd  
B
e
SO-H  
1. Drawing is not to scale.  
Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width  
millimeters  
Min  
inches  
Min  
Symbol  
Typ  
Max  
Typ  
Max  
A
A1  
B
2.35  
0.10  
0.33  
0.23  
10.10  
7.40  
2.65  
0.30  
0.51  
0.32  
10.50  
7.60  
0.093  
0.004  
0.013  
0.009  
0.398  
0.291  
0.104  
0.012  
0.020  
0.013  
0.413  
0.299  
C
D
E
e
1.27  
0.050  
H
10.00  
0.25  
0.40  
0°  
10.65  
0.75  
1.27  
8°  
0.394  
0.010  
0.016  
0°  
0.419  
0.030  
0.050  
8°  
h
L
θ
ddd  
0.10  
0.004  
42/45  
M25P128  
Part numbering  
12  
Part numbering  
Table 17. Ordering information scheme  
Example:  
M25P128  
V MF 6  
T
P
Device Type  
M25P = Serial Flash Memory for Code Storage  
Device Function  
128 = 128 Mit (16 Mb × 8)  
Operating Voltage  
V = VCC = 2.7 to 3.6 V  
Package  
MF = SO16 (300 mil width)  
ME = VDFPN8 8x6mm (MLP8)  
Device Grade  
6 = Industrial temperature range, –40 to 85 °C.  
Device tested with standard test flow  
Option  
blank = Standard Packing  
T = Tape and Reel Packing  
Plating Technology  
P or G = ECOPACK® (RoHs compliant)  
For a list of available options (speed, package, etc.) or for further information on any aspect  
of this device, please contact your nearest Numonyx Sales Office.  
The category of second-Level Interconnect is marked on the package and on the inner box  
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to  
soldering conditions are also marked on the inner box label.  
43/45  
Revision history  
M25P128  
13  
Revision history  
Table 18. Document revision history  
Date  
Revision  
Changes  
02-May-2005  
0.1  
First issue.  
Table 2: Protected area sizes updated.  
09-Jun-2005  
0.2  
Memory capacity modified in Section 6.3: Read Identification (RDID).  
Updated tPP values in Table 14: AC characteristics and tVSL value in  
Table 8: Power-Up Timing and VWI Threshold. Modified information  
in Section 4.1: Page programming and Section 6.8: Page Program  
(PP).  
28-Aug-2005  
0.3  
Document status promoted from Target specification to Preliminary  
data.  
Packages are ECOPACK® compliant. Blank option removed under  
Plating Technology in Table 17. Read Electronic Signature (RES)  
instruction removed. ICC1 parameter updated in Table 13: DC  
characteristics.  
20-Jan-2006  
1
Document status promoted from Preliminary Data to full Datasheet.  
Write Protect pin (W) changed to Write Protect/Enhanced Program  
supply voltage (W/VPP). Section 4.4: Fast Program/Erase mode and  
Figure 24: VPPH timing added. Power-up specified for Fast  
Program/Erase mode in Power-up and power-down section.  
17-Oct-2006  
10-Dec-2007  
2
3
Figure 4: Bus master and memory devices on the SPI bus modified  
and Note 2 added.  
Note 1 added below Table 15: VDFPN8 (MLP8), 8-lead Very thin  
Dual Flat Package No lead, 8 × 6mm, package mechanical data.  
VIO max modified in Table 9: Absolute maximum ratings.  
Applied Numonyx branding.  
44/45  
M25P128  
Please Read Carefully:  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR  
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT  
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY  
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF  
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,  
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.  
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility  
applications.  
Numonyx may make changes to specifications and product descriptions at any time, without notice.  
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the  
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,  
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.  
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves  
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.  
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by  
visiting Numonyx's website at http://www.numonyx.com.  
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.  
*Other names and brands may be claimed as the property of others.  
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.  
45/45  
配单直通车
M25P128-VMF6TP产品参数
型号:M25P128-VMF6TP
是否Rohs认证: 符合
生命周期:Transferred
零件包装代码:SOIC
包装说明:0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-16
针数:16
Reach Compliance Code:unknown
ECCN代码:3A991.B.1.A
HTS代码:8542.32.00.51
风险等级:5.59
其他特性:MORE THAN 10000 ERASE/PROGRAM CYCLES MORE THAN 20-YEAR DATA RETENTION
最大时钟频率 (fCLK):50 MHz
数据保留时间-最小值:20
耐久性:10000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G16
JESD-609代码:e3/e4
长度:10.3 mm
内存密度:134217728 bit
内存集成电路类型:FLASH
内存宽度:8
功能数量:1
端子数量:16
字数:16777216 words
字数代码:16000000
工作模式:SYNCHRONOUS
最高工作温度:85 °C
最低工作温度:-40 °C
组织:16MX8
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP16,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/3.3 V
编程电压:2.7 V
认证状态:Not Qualified
座面最大高度:2.65 mm
串行总线类型:SPI
最大待机电流:0.0001 A
子类别:Flash Memories
最大压摆率:0.02 mA
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
类型:NOR TYPE
宽度:7.5 mm
写保护:HARDWARE/SOFTWARE
Base Number Matches:1
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