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产品型号M82C55A的Datasheet PDF文件预览

E2O0020-27-X3  
This version: Jan. 1998  
Previous version: Aug. 1996  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
CMOS PROGRAMMABLE PERIPHERAL INTERFACE  
GENERAL DESCRIPTION  
The MSM82C55A-2 is a programmable universal I/O interface device which operates as high  
speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best  
fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU.  
This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are  
TTL interface compatible.  
FEATURES  
• High speed and low power consumption due to 3m silicon gate CMOS technology  
• 3 V to 6 V single power supply  
• Full static operation  
• Programmable 24-bit I/O ports  
• Bidirectional bus operation (Port A)  
• Bit set/reset function (Port C)  
• TTL compatible  
• Compatible with 8255A-5  
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS)  
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS)  
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K)  
1/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
CIRCUIT CONFIGURATION  
8
VCC  
8
8
Group A  
Port A  
(8)  
GND  
PA0 - PA7  
8
Group A  
Control  
4
4
4
4
Group A  
Port C  
PC4 - PC7  
(High Order  
4 Bits)  
8
8
Data  
Bus  
Buffer  
D0 - D7  
Group B  
Port C  
(Low Order  
4 Bits)  
PC0 - PC3  
8
RD  
Group B  
Control  
Read/  
Write  
WR  
8
8
Group B  
Port B  
(8)  
Control  
Logic  
RESET  
PB0 - PB7  
CS  
A0  
A1  
2/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
PIN CONFIGURATION (TOP VIEW)  
40 pin Plastic DIP  
1
2
40  
39  
38  
37  
36  
35  
34  
33  
32  
PA3  
PA2  
PA1  
PA0  
PA4  
PA5  
PA6  
PA7  
WR  
RESET  
D0  
3
4
5
RD  
CS  
GND  
A1  
6
7
8
D1  
D2  
9
A0  
31 D3  
10  
11  
12  
13  
14  
15  
16  
PC7  
PC6  
PC5  
PC4  
PC0  
PC1  
PC2  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
D4  
D5  
D6  
D7  
VCC  
PB7  
PB6  
PB5  
PB4  
PB3  
44 pin Plastic QFP  
PC3 17  
PB0 18  
PB1 19  
PB2 20  
CS  
GND  
A1  
1
2
3
4
5
6
7
8
9
33 RESET  
32 D0  
31 D1  
A0  
30  
29  
28  
27  
26  
25  
24  
D2.  
D3  
D4  
D5  
D6  
D7  
VCC  
PC7  
PC6  
PC5  
PC4  
PC0  
PC1 10  
PC2 11  
23 PB7  
44 pin Plastic QFJ  
CS  
GND  
A1  
7
8
9
39 RESET  
38 D0  
37 D1  
A0 10  
PC7 11  
NC 12  
PC6 13  
PC5 14  
PC4 15  
PC0 16  
PC1 17  
36  
35  
34  
33  
32  
31  
30  
D2.  
D3  
NC  
D4  
D5  
D6  
D7  
29 VCC  
3/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
ABSOLUTE MAXIMUM RATINGS  
Rating  
Parameter  
Symbol Conditions  
Unit  
MSM82C55A-2RS MSM82C55A-2GS MSM82C55A-2vJS  
Supply Voltage  
Input Voltage  
VCC  
VIN  
Ta = 25°C  
with respect  
to GND  
V
V
–0.5 to +7  
–0.5 to VCC +0.5  
–0.5 to VCC +0.5  
–55 to +150  
Output Voltage  
VOUT  
TSTG  
V
Storage Temperature  
Power Dissipation  
°C  
W
1.0  
0.7  
1.0  
PD  
Ta = 25°C  
OPERATING RANGE  
Parameter  
Supply Voltage  
Symbol  
VCC  
Unit  
V
Range  
3 to 6  
Operating Temperature  
Top  
–40 to 85  
°C  
RECOMMENDED OPERATING RANGE  
Parameter  
Supply Voltage  
Symbol  
VCC  
Unit  
Min.  
4.5  
Typ.  
5
Max.  
5.5  
V
Operating Temperature  
"L" Input Voltage  
Top  
–40  
–0.3  
2.2  
+25  
+85  
°C  
V
VIL  
+0.8  
VIH  
V
CC + 0.3  
V
"H" Input Voltage  
DC CHARACTERISTICS  
MSM82C55A-2  
Parameter  
"L" Output Voltage  
"H" Output Voltage  
Symbol  
VOL  
Conditions  
Unit  
Min.  
Typ.  
Max.  
I
OL = 2.5 mA  
OH = –40 mA  
OH = –2.5 mA  
4.2  
3.7  
–1  
0.4  
1
V
V
I
VOH  
I
V
ILI  
0 £ VIN £ VCC  
mA  
mA  
Input Leak Current  
Output Leak Current  
VCC = 4.5 V to 5.5 V  
Ta = –40°C to +85°C  
(CL = 0 pF)  
ILO  
0 £ VOUT £ VCC  
–10  
10  
CS VCC –0.2 V  
VIH VCC –0.2 V  
VIL £ 0.2 V  
Supply Current  
(Standby)  
0.1  
10  
8
mA  
ICCS  
I/O Wire Cycle  
82C55A-2  
Average Supply  
Current (Active)  
ICC  
mA  
...8 MHzCPU Timing  
4/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
AC CHARACTERISTICS  
(VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C)  
MSM82C55A-2  
Remarks  
Unit  
Parameter  
Symbol  
Min.  
20  
Max.  
Setup Time of Address to the Falling Edge of RD  
Hold Time of Address to the Rising Edge of RD  
RD Pulse Width  
ns  
ns  
ns  
tAR  
tRA  
tRR  
0
100  
Delay Time from the Falling Edge of RD to the Output of  
Defined Data  
10  
120  
75  
ns  
ns  
ns  
tRD  
tDF  
tRV  
Delay Time from the Rising Edge of RD to the Floating of  
Data Bus  
Time from the Rising Edge of RD or WR to the Next Falling  
Edge of RD or WR  
200  
Setup Time of Address before the Falling Edge of WR  
Hold Time of Address after the Rising Edge of WR  
WR Pulse Width  
Setup Time of Bus Data before the Rising Edge of WR  
Hold Time of Bus Data after the Rising Edge of WR  
0
ns  
ns  
ns  
ns  
ns  
tAW  
tWA  
tWW  
tDW  
tWD  
20  
150  
50  
30  
Delay Time from the rising Edge of WR to the Output of  
Defined Data  
200  
ns  
tWB  
Setup Time of Port Data before the Falling Edge of RD  
Hold Time of Port Data after the Rising Edge of RD  
ACK Pulse Width  
STB Pulse Width  
Setup Time of Port Data before the rising Edge of STB  
Hold Time of Port Bus Data after the rising Edge of STB  
20  
10  
ns  
ns  
ns  
ns  
ns  
ns  
tIR  
tHR  
tAK  
tST  
tPS  
tPH  
100  
100  
20  
Load  
150 pF  
50  
Delay Time from the Falling Edge of ACK to the Output of  
Defined Data  
20  
150  
250  
150  
150  
150  
150  
200  
150  
150  
250  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAD  
Delay Time from the Rising Edge of ACK to the Floating of  
Port (Port A in Mode 2)  
tKD  
Delay Time from the Rising Edge of WR to the Falling Edge of  
OBF  
Delay Time from the Falling Edge of ACK to the Rising Edge of  
OBF  
Delay Time from the Falling Edge of STB to the Rising Edge of  
IBF  
tWOB  
tAOB  
tSIB  
tRIB  
tRIT  
tSIT  
tAIT  
tWIT  
Delay Time from the Rising Edge of RD to the Falling Edge of  
IBF  
Delay Time from the the Falling Edge of RD to the Falling Edge  
of INTR  
Delay Time from the Rising Edge of STB to the Rising Edge of  
INTR  
Delay Time from the Rising Edge of ACK to the Rising Edge of  
INTR  
Delay Time from the Falling Edge of WR to the Falling Edge of  
INTR  
Note: Timing measured at V = 0.8 V and V = 2.2 V for both inputs and outputs.  
L
H
5/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
TIMING DIAGRAM  
Basic Input Operation (Mode 0)  
tRR  
RD  
tIR  
tHR  
Port Input  
tAR  
tRA  
CS, A1, A0  
D7 - D0  
tRD  
tDF  
Basic Output Operation (Mode 0)  
tWW  
WR  
tDW  
tWD  
D7 - D0  
tAW  
tWA  
CS, A1, A0  
Port Output  
tWB  
Strobe Input Operation (Mode 1)  
tST  
STB  
tSIB  
IBF  
INTR  
tSIT  
tRIB  
tRIT  
RD  
tPH  
Port Input  
tPS  
6/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
Strobe Output Operation (Mode 1)  
WR  
OBF  
tAOB  
tWOB  
INTR  
tWIT  
ACK  
tAIT  
tAK  
Port Output  
tWB  
Bidirectional Bus Operation (Mode 2)  
WR  
tAOB  
OBF  
tWOB  
INTR  
tAK  
ACK  
tST  
STB  
tSIB  
IBF  
tAD  
tKD  
tPS  
Port A  
tPH  
tRIB  
RD  
7/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
OUTPUT CHARACTERISTICS (REFERENCE VALUE)  
1
Output "H" Voltage (V ) vs. Output Current (I  
)
OH  
OH  
5
Ta = –40 to + 85°C  
VCC = 5.0 V  
4
3
2
1
0
0
–1  
–2  
–3  
–4  
–5  
Output Current IOH (mA)  
2
Output "L" Voltage (V ) vs. Output Current (I  
)
OL  
OL  
5
4
3
2
VCC = 5.0 V  
Ta = –40 to +85°C  
1
0
0
1
2
3
4
5
Output Current IOL (mA)  
Note: The direction of flowing into the device is taken as positive for the output current.  
8/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
PIN DESCRIPTION  
Pin No.  
Item  
Input/Output  
Function  
These are three-state 8-bit bidirectional buses used to write and  
read data upon receipt of the WR and RD signals from CPU and also  
used when control words and bit set/reset data are transferred from  
CPU to MSM82C55A-2.  
Bidirectional  
Data Bus  
Input and  
Output  
D7 - D0  
This signal is used to reset the control register and all internal  
registers when it is in high level. At this time, ports are all made into  
the input mode (high impedance status).  
all port latches are cleared to 0.  
and all ports groups are set to mode 0.  
RESET  
Input  
Input  
Reset Input  
When the CS is in low level, data transmission is enabled with CPU.  
When it is in high level, the data bus is made into the high impedance  
status where no write nor read operation is performed. Internal  
registers hold their previous status, however.  
Chip Select  
Input  
CS  
When RD is in low level, data is transferred from MSM82C55A-2 to  
CPU.  
RD  
Read Input  
Write Input  
Input  
Input  
When WR is in low level, data or control words are transferred from  
CPU to MSM82C55A-2.  
WR  
By combination of A0 and A1, either one is selected from among  
port A, port B, port C, and control register. These pins are usually  
connected to low order 2 bits of the address bus.  
Port Select Input  
(Address)  
A0, A1  
Input  
These are universal 8-bit I/O ports. The direction of inputs/ outputs  
can be determined by writing a control word. Especially, port A can  
be used as a bidirectional port when it is set to mode 2.  
Input and  
Output  
PA7 - PA0  
PB7 - PB0  
Port A  
Port B  
These are universal 8-bit I/O ports. The direction of inputs/outputs  
ports can be determined by writing a control word.  
Input and  
Output  
These are universal 8-bit I/O ports. The direction of inputs/outputs  
can be determined by writing a control word as 2 ports with 4 bits  
each. When port A or port B is used in mode 1 or mode 2 (port A  
only), they become control pins. Especially, when port C is used as  
an output port, each bit can set/reset independently.  
Input and  
Output  
PC7 - PC0  
Port C  
VCC  
+5V power supply.  
GND  
GND  
9/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
BASIC FUNCTIONAL DESCRIPTION  
Group A and Group B  
When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each.  
Group A: Port A (8 bits) and high order 4 bits of port C (PC ~PC )  
7
4
Group B: Port B (8 bits) and low order 4 bits of port C (PC ~PC )  
3
0
Mode 0, 1, 2  
There are 3 types of modes to be set by grouping as follows:  
Mode 0: Basic input operation/output operation (Available for both groups A and B)  
Mode 1: Strobe input operation/output operation (Available for both groups A and B)  
Mode 2: Bidirectional bus operation (Available for group A only)  
Whenusedinmode1ormode2, however, portChasbitstobedefinedasportsforcontrolsignal  
for operation ports (port A for group A and port B for group B) of their respective groups.  
Port A, B, C  
The internal structure of 3 ports is as follows:  
Port A: One 8-bit data output latch/buffer and one 8-bit data input latch  
Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer  
PortC: One8-bitdataoutputlatch/bufferandone8-bitdatainputbuffer(nolatchforinput)  
Single bit set/reset function for port C  
When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to  
turn to low level) any one of 8 bits individually without affecting other bits.  
10/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
OPERATIONAL DESCRIPTION  
Control Logic  
Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table  
below:  
RD  
0
Operaiton  
A1  
0
Operation  
A0  
0
CS  
0
WR  
1
Port A Æ Data Bus  
Input  
0
0
1
0
1
Port B Æ Data Bus  
Port C Æ Data Bus  
Data Bus Æ Port A  
0
1
0
0
1
1
0
0
0
0
Output  
1
0
1
0
0
Data Bus Æ Port B  
Data Bus Æ Port C  
1
1
0
0
0
1
Control  
Others  
1
1
0
0
Data Bus Æ Control Register  
Illegal Condition  
0
1
1
0
1
¥
¥
¥
1
¥
Data bus is in the high impedance status.  
Setting of Control Word  
The control register is composed of 7-bit latch circuit and 1-bit flag as shown below.  
Group A Control Bits  
D6 D5 D4  
Group B Control Bits  
D2 D1 D0  
D7  
D3  
Definition of input/  
output of low order  
4 bits of port C.  
0 = Output  
1 = Input  
Definition of input/  
output of 8 bits of  
port B.  
Mode definition of  
group B.  
0 = Output  
1 = Input  
0 = Mode 0  
1 = Mode 1  
Definition of input/  
output of high order  
4 bits of port C.  
0 = Output  
1 = Input  
Definition of input/  
output of 8 bits of  
port A.  
0 = Output  
1 = Input  
Mode definition of group A.  
D6 D5  
Mode  
Mode 0  
Mode 1  
Mode 2  
Control word Identification flag  
0
0
1
0
1
¥
Be sure to set 1 for the control word  
to define a mode and input/output.  
When set to 0, it becomes  
the control word for bit set/  
reset.  
11/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
Precaution for Mode Selection  
The output registers for ports A and C are cleared to f each time data is written in the command  
register and the mode is changed, but the port B state is undefined.  
Bit Set/Reset Function  
When port C is defined as output port, it is possible to set (set output to 1) or reset (set output  
to 0) any one of 8 bits without affecting other bits as shown below.  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Definition of set/reset  
for a desired bit.  
0 = Reset  
1 = Set  
Definition of bit wanted  
to be set or reset.  
Port C D3 D2 D1  
PC0  
PC1  
PC2  
PC3  
PC4  
PC5  
PC6  
PC7  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Dont's Care  
Control word Identification flag  
Be sure to set to 0 for bit set/reset  
When set to 1, it becomes the control  
word to define a mode and input/output.  
Interrupt Control Function  
When the MSM82C55A-2 is used in mode 1 or mode 2, the interrupt signal for the CPU is  
provided. The interrupt request signal is output from port C. When the internal flip-flop INTE  
is set beforehand at this time, the desired interrupt request signal is output. When it is reset  
beforehand, however, the interrupt request signal is not output. The set/reset of the internal  
flip-flop is made by the bit set/reset operation for port C virtually.  
Bit set Æ INTE is set Æ Interrupt allowed  
Bit reset Æ INTE is reset Æ Interrupt inhibited  
Operational Description by Mode  
1. Mode 0 (Basic input/output operation)  
Mode 0 makes the MSM82C55A-2 operate as a basic input port or output port. No control  
signals such as interrupt request, etc. are required in this mode. All 24 bits can be used as  
two-8-bit ports and two 4-bit ports. Sixteen combinations are then possible for inputs/  
outputs. The inputs are not latched, but the outputs are.  
12/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
Control Word  
D7 D6 D5 D4 D3 D2 D1 D0  
Group A  
Group B  
Type  
High Order 4 Bits  
of Port C  
Low Order 4 Bits  
Port B  
Port A  
of Port C  
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Input  
Output  
Output  
Output  
Output  
Input  
Output  
Output  
Input  
Output  
Input  
3
Output  
Input  
4
Input  
5
Output  
Output  
Input  
Output  
Input  
6
Input  
7
Input  
Ouput  
Input  
8
Input  
Input  
9
Output  
Output  
Output  
Output  
Input  
Output  
Output  
Input  
Output  
Input  
10  
11  
12  
13  
14  
15  
16  
Input  
Input  
Output  
Input  
Input  
Input  
Input  
Output  
Output  
Input  
Output  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
Input  
Input  
Notes: When used in mode 0 for both groups A and B  
2. Mode 1 (Strobe input/output operation)  
In mode 1, the strobe, interrupt and other control signals are used when input/output  
operations are made from a specified port. This mode is available for both groups A and  
B. In group A at this time, port A is used as the data line and port C as the control signal.  
Following is a description of the input operation in mode 1.  
STB (Strobe input)  
When this signal is low level, the data output from terminal to port is fetched into the  
internal latch of the port. This can be made independent from the CPU, and the data is not  
output to the data bus until the RD signal arrives from the CPU.  
IBF (Input buffer full flag output)  
This is the response signal for the STB. This signal when turned to high level indicates that  
data is fetched into the input latch. This signal turns to high level at the falling edge of STB  
and to low level at the rising edge of RD.  
INTR (Interrupt request output)  
This is the interrupt request signal for the CPU of the data fetched into the input latch. It  
is indicated by high level only when the internal INTE flip-flop is set. This signal turns to  
high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge  
of the RD when the INTE is set.  
INTE of group A is set when the bit for PC is set, while INTE of group B is set when the  
A
4
B
bit for PC is set.  
2
Following is a description of the output operation of mode 1.  
13/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
OBF (Output buffer full flag output)  
This signal when turned to low level indicates that data is written to the specified port upon  
receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of  
the WR and high level at the falling edge of the ACK.  
ACK (Acknowledge input)  
This signal when turned to low level indicates that the terminal has received data.  
INTR (Interrupt request output)  
This is the signal used to interrupt the CPU when a terminal receives data from the CPU via  
the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the  
internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK  
(OBF = 1 at this time) and low level at the falling edge of WR when the INTE is set.  
B
INTE of group A is set when the bit for PC is set, while INTE of group B is set when the  
A
6
B
bit for PC is set.  
2
Mode 1 Input  
(Group A)  
(Group B)  
8
8
PA7  
PA0  
PC4  
PB7  
PB0  
PC2  
INTEA  
INTEB  
STBA  
STBB  
PC5  
PC1  
IBFA  
IBFB  
RD  
RD  
PC3  
PC0  
INTRA  
INTRB  
Note: Although belonging to group B, PC3 operates as the control signal of  
group A functionally.  
Mode 1 Output  
(Group A)  
(Group B)  
8
8
PA7  
PA0  
PC7  
PB7  
PB0  
PC1  
INTEA  
INTEB  
OBFA  
ACKA  
OBFB  
ACKB  
PC6  
PC2  
WR  
WR  
PC3  
PC0  
INTRA  
INTRB  
14/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
Port C Function Allocation in Mode 1  
Combination of  
Group A: Input  
Input/Output  
Group A: Input  
Group B: Input Group B: Output  
Group A: Output  
Group B: Input  
Group A: Output  
Group B: Output  
Port C  
INTRB  
IBFB  
STBB  
INTRA  
STBA  
IBFA  
I/O  
INTRB  
OBFB  
ACKB  
INTRA  
STBA  
IBFA  
PC0  
PC1  
PC2  
PC3  
PC4  
PC5  
PC6  
PC7  
INTRB  
IBFB  
INTR  
B
OBFB  
ACKB  
INTRA  
I/O  
STBB  
INTRA  
I/O  
I/O  
I/O  
I/O  
ACKA  
OBFA  
ACKA  
OBFA  
I/O  
I/O  
Note: I/O is a bit not used as the control signal, but it is available as a port of mode 0.  
Examples of the relation between the control words and pins when used in mode 1 are  
shown below:  
(a) When group A is mode 1 output and group B is mode 1 input.  
D7  
1
D6  
0
D5  
1
D4  
0
D3  
D2  
1
D1  
1
D0  
Control Word  
1/0  
¥
As all of PC0 - PC3 bits  
become a control pin  
in this case, this bit is  
"Don't Care".  
Selection of I/O  
of PC4 and PC5  
when not defined  
as a control pin.  
1 = Input  
0 = Output  
8
PA7 - PA0  
PC7  
OBFA  
ACKA  
INTRA  
I/O  
WR  
PC6  
PC3  
PC4, PC5  
2
8
Group A: Mode 1 Output  
Group B: Mode 1 Input  
PB7 - PB0  
PC2  
STBB  
IBFB  
INTRB  
PC1  
PC0  
RD  
15/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
(b) When group A is mode 1 input and group B is mode 1 output.  
D7  
1
D6  
0
D5  
1
D4  
1
D3  
D2  
1
D1  
0
D0  
1/0  
¥
Selection of I/O of PC6 and PC7  
when not defined as a control pin.  
1 = Input  
0 = Output  
8
PA7 - PA0  
PC4  
PC5  
PC3  
PC6, PC7  
STBA  
RD  
IBFA  
INTRA  
I/O  
2
8
Group A: Mode 1 Input  
Group B: Mode 1 Output  
PB7 - PB0  
PC1  
OBFB  
ACKB  
INTRB  
PC2  
PC0  
WR  
3. Mode 2 (Strobe bidirectional bus I/O operation)  
In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This  
operation is akin to a combination between input and output operations. Port C waits for  
the control signal in this case, too. Mode 2 is available only for group A, however.  
Next, a description is made on mode 2.  
OBF (Output buffer full flag output)  
This signal when turned to low level indicates that data has been written to the internal  
output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the  
high impedance status and the data is not yet output to the outside. This signal turns to low  
level at the rising edge of the WR and high level at the falling edge of the ACK.  
ACK (Acknowledge input)  
When a low level signal is input to this pin, the high impedance status of port A is cleared,  
the buffer is enabled, and the data written to the internal output latch is output to port A.  
When the input returns to high level, port A is made into the high impedance status.  
STB (Strobe input)  
When this signal turns to low level, the data output to the port from the pin is fetched into  
theinternalinputlatch. ThedataisoutputtothedatabusuponreceiptoftheRDsignalfrom  
the CPU, but it remains in the high impedance status until then.  
IBF (Input buffer full flag output)  
This signal when turned to high level indicates that data from the pin has been fetched into  
the input latch. This signal turns to high level at the falling edge of the STB and low level  
at the rising edge of the RD.  
16/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
INTR (Interrupt request output)  
This signal is used to interrupt the CPU and its operation in the same as in mode 1. There  
are two INTE flip-flops internally available for input and output to select either interrupt  
of input or output operation. The INTE1 is used to control the interrupt request for output  
operation and it can be reset by the bit set for PC6. INTE2 is used to control the interrupt  
request for the input operation and it can be set by the bit set for PC4.  
Mode 2 I/O Operation  
PC3  
PA7  
INTRA  
8
PA0  
PC7  
OBFA  
ACKA  
INTE1  
INTE2  
PC  
6
WR  
RD  
PC4  
PC5  
STBA  
IBFA  
Port C Function Allocation in Mode 2  
Port C  
Function  
PC0  
PC1  
PC2  
PC3  
PC4  
PC5  
PC6  
PC7  
Confirmed to the Group B Mode  
INTRA  
STBA  
IBFA  
ACKA  
OBFA  
Following is an example of the relation between the control word and the pin when used in  
mode 2.  
When input in mode 2 for group A and in mode 1 for group B.  
17/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
D7  
1
D6  
1
D5  
D4  
D3  
D2  
1
D1  
1
D0  
¥
¥
¥
¥
As all of 8 bits of port C become  
control pins in this case, D3 and  
D0 bits are treated as "Don't Care".  
No I/O specification is required for mode 2,  
since it is a bidirectional operation.  
This bit is therefore treated as "Don't Care".  
When group A is set to mode 2, this bit is treated  
as "Don't Care".  
PC3  
PA7 - PA0  
PC7  
INTRA  
8
8
OBFA  
ACKA  
STBA  
IBFA  
PC6  
PC4  
PC5  
Group A: Mode 2  
Group B: Mode 1 Input  
RD  
PB7 - PB0  
PC2  
STBB  
IBFB  
WR  
PC1  
PC0  
INTRB  
18/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
4. When Group A is Different in Mode from Group B  
Group A and group B can be used by setting them in different modes each other at the same  
time. When either group is set to mode 1 or mode 2, it is possible to set the one not defined  
as a control pin in port C to both input and output as port which operates in mode 0 at the  
3rd and 0th bits of the control word.  
(Mode combinations that define no control bit at port C)  
Port C  
Group A Group B  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC7  
PC0  
Mode 1  
input  
1
STBA  
INTRA  
I/O  
Mode 0  
Mode 0  
I/O  
I/O  
IBFA  
I/O  
I/O  
Mode 0  
Output  
I/O  
I/O  
INTRA  
I/O  
I/O  
2
3
4
5
6
7
OBFA  
I/O  
ACKA  
I/O  
I/O  
I/O  
I/O  
I/O  
Mode 1  
Input  
STBB  
ACKB  
STBB  
ACKB  
STBB  
Mode 0  
Mode 0  
IBFB  
OBFB  
IBFB  
OBFB  
IBFB  
INTRB  
INTRB  
INTRB  
INTRB  
INTRB  
Mode 1  
Output  
I/O  
I/O  
I/O  
I/O  
I/O  
Mode 1  
Input  
Mode 1  
Input  
STBA  
STBA  
I/O  
INTRA  
INTRA  
INTRA  
I/O  
I/O  
IBFA  
IBFA  
I/O  
Mode 1  
Input  
Mode 1  
Output  
I/O  
I/O  
Mode 1  
Input  
Mode 1  
Output  
OBFA  
ACKA  
Mode 1  
Output  
Mode 1  
Output  
I/O  
INTRA  
INTRA  
ACKB  
8
9
OBFA  
OBFA  
ACKA  
ACKA  
I/O  
OBFB  
INTRB  
I/O  
Mode 2  
Mode 0  
STBA  
I/O  
IBFA  
I/O  
Controlled at the 3rd bit (D3) of  
the Control Word  
Controlled at the 0th bit (D0) of  
the Control Word  
When the I/O bit is set to input in this case, it is possible to access data by the normal port  
C read operation.  
When set to output, PC -PC bits can be accessed by the bit set/reset function only.  
7
4
Meanwhile, 3 bits from PC to PC can be accessed by normal write operation.  
2
0
The bit set/reset function can be used for all of PC -PC bits. Note that the status of port C  
3
0
varies according to the combination of modes like this.  
19/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
5. Port C Status Read  
When port C is used for the control signal, that is, in either mode 1 or mode 2, each control  
signal and bus status signal can be read out by reading the content of port C.  
The status read out is as follows:  
Status Read on the Data Bus  
Group A Group B  
D6  
D5  
D4  
D3  
D2  
D1  
D7  
D0  
Mode 1  
Input  
1
INTEA  
INTRA  
I/O  
Mode 0  
Mode 0  
I/O  
I/O  
IBFA  
I/O  
I/O  
Mode 1  
Output  
I/O  
I/O  
INTRA  
I/O  
I/O  
2
3
4
5
6
7
OBFA  
I/O  
INTEA  
I/O  
I/O  
I/O  
I/O  
I/O  
Mode 1  
Input  
INTEB  
INTEB  
INTEB  
INTEB  
INTEB  
Mode 0  
Mode 0  
IBFB  
OBFB  
IBFB  
OBFB  
IBFB  
INTRB  
INTRB  
INTRB  
INTRB  
INTRB  
Mode 1  
Output  
I/O  
I/O  
I/O  
I/O  
I/O  
Mode 1  
Input  
Mode 1  
Input  
INTEA  
INTEA  
I/O  
INTRA  
INTRA  
INTRA  
I/O  
I/O  
IBFA  
IBFA  
I/O  
Mode 1  
Input  
Mode 1  
Output  
I/O  
I/O  
Mode 1  
Input  
Mode 1  
Output  
OBFA  
INTEA  
Mode 1  
Output  
Mode 1  
Output  
I/O  
INTRA  
INTRA  
INTRA  
INTEB  
I/O  
8
9
OBFA  
OBFA  
OBFA  
INTEA  
INTE1  
INTE1  
I/O  
OBFB  
I/O  
INTRB  
I/O  
Mode 2  
Mode 0  
INTE2  
INTE2  
IBFA  
IBFA  
Mode 1  
Input  
INTEB  
Mode 2  
IBFB  
INTRB  
10  
11  
Mode 1  
Output  
INTE2  
INTRA  
INTEB  
OBFA  
INTE1  
IBFA  
OBFB  
INTRB  
Mode 2  
6. Reset of MSM82C55A-2  
Be sure to keep the RESET signal at power ON in the high level at least for 50 ms.  
Subsequently, it becomes the input mode at a high level pulse above 500 ns.  
Note: Comparison of MSM82C55A-5 and MSM82C55A-2  
MSM82C55A-5  
After a write command is executed to the command register, the internal latch is cleared in  
PORTA PORTC. For instance, 00H is output at the beginning of a write command when  
the output port is assigned. However, if PORTB is not cleared at this time, PORTB is  
unstable. In other words, PORTB only outputs ineffective data (unstable value according  
to the device) during the period from after a write command is executed till the first data  
is written to PORTB.  
MSM82C55A-2  
After a write command is executed to the command register, the internal latch is cleared in  
All Ports (PORTA, PORTB, PORTC). 00H is output at the beginning of a write command  
when the output port is assigned.  
20/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES  
The conventional low speed devices are replaced by high-speed devices as shown below.  
When you want to replace your low speed devices with high-speed devices, read the replacement  
notice given on the next pages.  
High-speed device (New)  
M80C85AH  
Remarks  
Low-speed device (Old)  
M80C85A/M80C85A-2  
M80C86A/M80C86A-2  
M80C88A/M80C88A-2  
M82C84A/M82C84A-5  
M81C55  
8bit MPU  
M80C86A-10  
16bit MPU  
M80C88A-10  
8bit MPU  
M82C84A-2  
Clock generator  
RAM.I/O, timer  
DMA controller  
M81C55-5  
M82C37B-5  
M82C37A/M82C37A-5  
M82C51A-2  
USART  
M82C51A  
M82C53-2  
Timer  
PPI  
M82C53-5  
M82C55A-2  
M82C55A-5  
21/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
Differences between MSM82C55A-5 and MSM82C55A-2  
1) Manufacturing Process  
These devices use a 3 m Si-Gate CMOS process technology.  
The MSM82C55A-2 is about 7% smaller in chip size than the MSM82C55A-5 as the MSM82C55A-  
2 changed its output characteristics.  
2) Function  
Item  
MSM82C55A-5  
MSM82C55A-2  
All ports are cleared.  
Internal latch during writing into  
the command register  
Only ports A and C are cleared.  
Port B is not cleared.  
The above function has been improved to remove bugs and other logics are not different between  
the two devices.  
3) Electrical Characteristics  
3-1) DC Characteristics  
Parameter  
''L'' Output Voltage  
Symbol  
MSM82C55A-5  
MSM82C55A-2  
0.45 V  
(IOL = +2.5 mA)  
0.40 V  
(IOL = +2.5 mA)  
V
OL  
2.4 V  
(IOH = -400 mA)  
3.7 V  
(IOH = -2.5 mA)  
''H'' Output Voltage  
V
OH  
5 mA maximum  
(I/O Cycle = 1 ms)  
8 mA maximum  
(I/O Cycle = 375 ns)  
Average Operating Current  
I
CC  
As shown above, the DC characteristics of the MSM82C55A-2 satisfies the DC characteristics of the  
MSM82C55A-5.  
3-2) AC Characteristics  
Parameter  
MSM82C55A-5  
MSM82C55A-2  
Symbol  
tRA  
Address Hold Time for RD Rising  
20 ns minimum  
0 ns minimum  
tRR  
tRD  
RD Pulse Width  
300 ns minimum  
200 ns maximum  
100 ns minimum  
120 ns maximum  
Difined Data Output Delay Time  
From RD Falling  
100 ns maximum  
850 ns minimum  
75 ns maximum  
200 ns minimum  
tRF  
tRV  
Data Floating Delay Time From RD Rising  
RD/WR Recovery Time  
22/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
Parameter  
Symbol  
MSM82C55A-5  
MSM82C55A-2  
Address Hold Time for WR Rising  
t
WA  
30 ns minimum  
20 ns minimum  
t
WW  
WR Pulse Width  
300 ns minimum  
1000 ns minimum  
150 ns minimum  
50 ns minimum  
Data Setup Time for WR Rising  
t
DW  
WD  
Data Hold Time for WR Rising  
t
40 ns minimum  
30 ns minimum  
Defined Data Output Time  
From WR Rising  
t
WB  
350 ns maximum  
20 ns minimum  
200 ns maximum  
10 ns minimum  
t
HR  
AK  
Port Data Hold Time for RD Rising  
t
ACK Pulse Width  
STB Pulse Width  
300 ns minimum  
300 ns minimum  
100 ns minimum  
100 ns minimum  
t
ST  
t
PH  
Port Data Hold Time for STB Falling  
ACK Falling to Defined Data Output  
WR Falling to OBF Falling Delay Time  
ACK Falling to OBF Rising Delay Time  
STB Falling to IBF Rising Delay Time  
RD Rising to IBF Falling Delay Time  
RD Falling to INTR Falling Delay Time  
STB Rising to INTR Rising Delay Time  
ACK Rising to INTR Rising Delay Time  
WR Falling to INTR Falling Delay Time  
180 ns minimum  
300 ns maximum  
650 ns maximum  
350 ns maximum  
300 ns maximum  
300 ns maximum  
400 ns maximum  
300 ns maximum  
350 ns maximum  
850 ns minimum  
50 ns minimum  
150 ns maximum  
150 ns maximum  
150 ns maximum  
150 ns maximum  
150 ns maximum  
200 ns maximum  
150 ns maximum  
150 ns maximum  
250 ns maximum  
t
AD  
t
WOB  
t
AOB  
t
SIB  
RIB  
t
t
RIT  
t
t
SIT  
AIT  
t
WIT  
As shown above, the MSM82C55A-2 satisfies the characteristics of the MSM82C55A-5.  
23/26  
¡ Semiconductor  
PACKAGE DIMENSIONS  
DIP40-P-600-2.54  
MSM82C55A-2RS/GS/VJS  
(Unit : mm)  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
6.10 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
24/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
(Unit : mm)  
QFJ44-P-S650-1.27  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
Cu alloy  
Solder plating  
5 mm or more  
2.00 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
25/26  
¡ Semiconductor  
MSM82C55A-2RS/GS/VJS  
(Unit : mm)  
QFP44-P-910-0.80-2K  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
0.41 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
26/26  
配单直通车
M83-0110001产品参数
型号:M83-0110001
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8536.90.40.00
风险等级:5.69
Is Samacsys:N
制造商序列号:M83
Base Number Matches:1
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