M93C46-WMN6P全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

M93C86, M93C76, M93C66

M93C56, M93C46

16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit (8-bit or 16-bit wide)

MICROWIRE® serial access EEPROM

Features

●

Industry standard MICROWIRE bus

Single supply voltage:

●

–

4.5 V to 5.5 V for M93Cx6

2.5 V to 5.5 V for M93Cx6-W

1.8 V to 5.5 V for M93Cx6-R

●

Dual organization: by word (x16) or byte (x8)

PDIP8 (BN)

Programming instructions that work on: byte,

word or entire memory

●

Self-timed programming cycle with auto-

erase: 5 ms

●

READY/BUSY signal during programming

2 MHz clock rate

Sequential read operation

Enhanced ESD/latch-up behavior

More than 1 million write cycles

More than 40 year data retention

Packages

SO8 (MN)

150 mil width

–

ECOPACK® (RoHS compliant)

TSSOP8 (DW)

169 mil width

Table 1.

Reference

Product list

Part

Reference

number

M93C86

M93C56

UFDFPN8 (MB)

2 x 3 mm (MLP)

M93C86 M93C86-W

M93C86-R

M93C56 M93C56-W

M93C56-R

M93C66

M93C46

M93C66 M93C66-W

M93C66-R

M93C46 M93C46-W

M93C46-R

M93C76

M93C76 M93C76-W

M93C76-R

January 2008

Rev 8

1/37

www.st.com

1

Contents

M93C86, M93C76, M93C66, M93C56, M93C46

Contents

1

2

3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

Supply voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1.1

3.1.2

3.1.3

3.1.4

Operating supply voltage V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4

5

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1

5.2

5.3

5.4

5.5

5.6

Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6

READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7

8

9

10

11

12

2/37

M93C86, M93C76, M93C66, M93C56, M93C46

Contents

13

14

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3/37

List of tables

M93C86, M93C76, M93C66, M93C56, M93C46

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Instruction set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Operating conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operating conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AC measurement conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AC measurement conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . 22

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC characteristics (M93Cx6, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC characteristics (M93Cx6, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AC characteristics (M93Cx6, device grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 30

UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . 31

TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Available M93C46-x products (package, voltage range, temperature grade). . . . . . . . . . . 34

Available M93C56-x products (package, voltage range, temperature grade). . . . . . . . . . . 34

Available M93C66-x products (package, voltage range, temperature grade). . . . . . . . . . . 34

Available M93C76-x products (package, voltage range, temperature grade). . . . . . . . . . . 34

Available M93C86-x products (package, voltage range, temperature grade). . . . . . . . . . . 34

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

4/37

M93C86, M93C76, M93C66, M93C56, M93C46

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DIP, SO, TSSOP and MLP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 30

Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline 31

Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32

5/37

Description

M93C86, M93C76, M93C66, M93C56, M93C46

1

Description

The M93C86, M93C76, M93C66, M93C56 and M93C46 are electrically erasable

programmable memory (EEPROM) devices. They are accessed through a Serial Data input

(D) and Serial Data output (Q) using the MICROWIRE bus protocol.

Figure 1.

Logic diagram

V

CC

D

Q

C

S

M93Cx6

ORG

V

SS

AI01928

Table 2.

Signal names

Signal name

Function

Direction

S

Chip Select

Input

Output

Input

D

Serial Data input

Q

Serial Data output

Serial Clock

C

ORG

V_CC

V_SS

Organisation Select

Supply voltage

Ground

The memory array organization may be divided into either bytes (x8) or words (x16) which

may be selected by a signal applied on Organization Select (ORG). The bit, byte and word

sizes of the memories are as shown in Table 3.

6/37

M93C86, M93C76, M93C66, M93C56, M93C46

Description

Table 3.

Device

Memory size versus organization

Number of bits

Number of 8-bit bytes

Number of 16-bit words

M93C86

M93C76

M93C66

M93C56

M93C46

16384

8192

4096

2048

1024

2048

1024

512

1024

512

256

128

64

256

128

The M93Cx6 is accessed by a set of instructions, as summarized in Table 4., and in more

detail in Table 5. to Table 7.).

Table 4.

Instruction set for the M93Cx6

Description

Instruction

Data

Byte or Word

READ

WRITE

WEN

Read Data from Memory

Write Data to Memory

Write Enable

Byte or Word

WDS

Write Disable

ERASE

ERAL

Erase Byte or Word

Erase All Memory

Byte or Word

Write All Memory

with same Data

WRAL

A Read Data from Memory (READ) instruction loads the address of the first byte or word to

be read in an internal address register. The data at this address is then clocked out serially.

The address register is automatically incremented after the data is output and, if Chip Select

Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In

this way, the memory can be read as a data stream from eight to 16384 bits long (in the

case of the M93C86), or continuously (the address counter automatically rolls over to 00h

when the highest address is reached).

Programming is internally self-timed (the external clock signal on Serial Clock (C) may be

stopped or left running after the start of a Write cycle) and does not require an Erase cycle

prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the

byte or word locations of the M93Cx6. After the start of the programming cycle, a

Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is

driven High.

An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when

the supply is too low.

7/37

Description

M93C86, M93C76, M93C66, M93C56, M93C46

DIP, SO, TSSOP and MLP connections (top view)

M93Cx6

Figure 2.

S

C

D

Q

1

8

V

CC

DU

2

3

4

7

6

5

ORG

V

SS

AI01929B

1. See Package mechanical data section for package dimensions, and how to identify pin-1.

2. DU = Don’t Use.

The DU (do not use) pin does not contribute to the normal operation of the device. It is

reserved for use by STMicroelectronics during test sequences. The pin may be left

unconnected or may be connected to V or V

.

CC

SS

8/37

M93C86, M93C76, M93C66, M93C56, M93C46

Connecting to the serial bus

2

Connecting to the serial bus

Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.

Only one device is selected at a time, so only one device drives the Serial Data output (Q)

line at a time, the other devices are high impedance.

The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the

bus master leaves the S line in the high impedance state.

In applications where the bus master may be in a state where all inputs/outputs are high

impedance at the same time (for example, if the bus master is reset during the transmission

of an instruction), the clock line (C) must be connected to an external pull-down resistor so

that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is

pulled low): this ensures that C does not become high at the same time as S goes low, and

so, that the t

requirement is met. The typical value of R is 100 kΩ.

SLCH

Figure 3.

Bus master and memory devices on the serial bus

V_SS

V_CC

R

SDO

SDI

SCK

Bus master

V_CC

C

Q

D

C

Q

D

C Q D

V_SS

M93xxx

memory device

M93xxx

memory device

M93xxx

memory device

R

CS3 CS2 CS1

S

ORG

AI14377b

9/37

Operating features

M93C86, M93C76, M93C66, M93C56, M93C46

3

Operating features

3.1

Supply voltage (V_CC)

3.1.1

Operating supply voltage V

CC

Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage

CC

within the specified [V (min), V (max)] range must be applied. In order to secure a stable

CC

DC supply voltage, it is recommended to decouple the V line with a suitable capacitor

CC

(usually of the order of 10 nF to 100 nF) close to the V /V package pins.

CC SS

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (t ).

W

3.1.2

3.1.3

Power-up conditions

When the power supply is turned on, V rises from V to V . During this time, the Chip

Select (S) line is not allowed to float and should be driven to V , it is therefore

recommended to connect the S line to V via a suitable pull-down resistor.

CC

SS

CC

SS

The V rise time must not vary faster than 1 V/µs.

CC

Power-up and device reset

In order to prevent inadvertent Write operations during power-up, a power on reset (POR)

circuit is included. At power-up (continuous rise of V ), the device does not respond to any

CC

instruction until V has reached the power on reset threshold voltage (this threshold is

CC

lower than the minimum V operating voltage defined in Table 9, Table 10 and Table 11).

CC

When V passes the POR threshold, the device is reset and is in the following state:

CC

●

Standby Power mode

●

deselected (assuming that there is a pull-down resistor on the S line)

3.1.4

Power-down

At power-down (continuous decrease in V ), as soon as V drops from the normal

CC

operating voltage to below the power on reset threshold voltage, the device stops

responding to any instruction sent to it.

During power-down, the device must be deselected and in the Standby Power mode (that is,

there should be no internal Write cycle in progress).

10/37

M93C86, M93C76, M93C66, M93C56, M93C46

Memory organization

4

Memory organization

The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization

Select (ORG) is left unconnected (or connected to V ) the x16 organization is selected;

CC

when Organization Select (ORG) is connected to Ground (V ) the x8 organization is

SS

selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set

either to V or V for minimum power consumption. Any voltage between V and V

SS

CC

SS

CC

applied to Organization Select (ORG) may increase the Standby current.

11/37

Instructions

M93C86, M93C76, M93C66, M93C56, M93C46

5

Instructions

The instruction set of the M93Cx6 devices contains seven instructions, as summarized in

Table 5. to Table 7.. Each instruction consists of the following parts, as shown in Figure 4.:

●

Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock

(C) being held low.

●

A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of

Serial Clock (C).

Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock

(C). (Some instructions also use the first two bits of the address to define the op-code).

The address bits of the byte or word that is to be accessed. For the M93C46, the

address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization

(see Table 5.). For the M93C56 and M93C66, the address is made up of 8 bits for the

x16 organization or 9 bits for the x8 organization (see Table 6.). For the M93C76 and

M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8

organization (see Table 7.).

The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as

slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 20. to

Table 23..

Table 5.

Instruction set for the M93C46

x8 origination (ORG = 0)

x16 origination (ORG = 1)

Start Op-

Required

clock

Required

Address

Instruction

Description

Address

bit

code

Data

clock

(1)

cycles

Read Data from

Memory

READ

WRITE

WEN

1

10

01

00

11

00

A6-A0

Q7-Q0

D7-D0

A5-A0

Q15-Q0

D15-D0

Write Data to

Memory

18

10

18

25

9

11X

XXXX

Write Enable

Write Disable

11 XXXX

00 XXXX

A5-A0

00X

XXXX

WDS

9

Erase Byte or

Word

ERASE

ERAL

WRAL

A6-A0

9

10X

XXXX

Erase All Memory

10 XXXX

9

Write All Memory

with same Data

01X

XXXX

D7-D0

01 XXXX D15-D0

25

1. X = Don't Care bit.

12/37

M93C86, M93C76, M93C66, M93C56, M93C46

Instructions

Table 6.

Instruction set for the M93C56 and M93C66

x8 origination (ORG = 0)

x16 origination (ORG = 1)

Start Op-

bit code

Instruction

Description

Address

Required Address

Required

Data

(1) (2)

(1) (3)

clock cycles

Read Data from

Memory

READ

WRITE

WEN

1

10

01

00

11

00

A8-A0

Q7-Q0

D7-D0

A7-A0 Q15-Q0

A7-A0 D15-D0

Write Data to

Memory

20

12

20

27

11

27

1 1XXX

XXXX

11XX

XXXX

Write Enable

Write Disable

0 0XXX

XXXX

00XX

XXXX

WDS

Erase Byte or

Word

ERASE

ERAL

WRAL

A8-A0

A7-A0

Erase All

Memory

1 0XXX

XXXX

10XX

XXXX

Write All Memory

with same Data

0 1XXX

XXXX

01XX

D7-D0

D15-D0

XXXX

1. X = Don't Care bit.

2. Address bit A8 is not decoded by the M93C56.

3. Address bit A7 is not decoded by the M93C56.

Table 7.

Instruction set for the M93C76 and M93C86

x8 Origination (ORG = 0)

x16 Origination (ORG = 1)

Start Op-

bit code

Required

clock

Required

Address

Instruction

Description

Address^(1),

Data

clock

(2)

(1) (3)

cycles

Read Data from

Memory

READ

WRITE

WEN

1

10

01

00

A10-A0

Q7-Q0

D7-D0

A9-A0 Q15-Q0

A9-A0 D15-D0

Write Data to

Memory

22

14

29

13

11X XXXX

XXXX

11XXXX

XXXX

Write Enable

00X XXXX

XXXX

00XXXX

XXXX

WDS

Write Disable

1

00

11

00

14

13

ERASE

ERAL

Erase Byte or Word

Erase All Memory

A10-A0

A9-A0

10X XXXX

XXXX

10XXXX

XXXX

Write All Memory

with same Data

01X XXXX

XXXX

01XXXX

D15-D0

XXXX

WRAL

1

00

D7-D0

22

29

1. X = Don't Care bit.

2. Address bit A10 is not decoded by the M93C76.

3. Address bit A9 is not decoded by the M93C76.

13/37

Instructions

M93C86, M93C76, M93C66, M93C56, M93C46

5.1

Read Data from Memory

The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).

When the instruction is received, the op-code and address are decoded, and the data from

the memory is transferred to an output shift register. A dummy 0 bit is output first, followed

by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are

triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the

internal address register and clocks out the next byte (or word) as long as the Chip Select

Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)

and a continuous stream of data can be read.

5.2

Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of erase or write

instructions, and the Write Disable (WDS) instruction disables it. When power is first

applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After

an Write Enable (WEN) instruction has been executed, erasing and writing remains enabled

until an Write Disable (WDS) instruction is executed, or until V falls below the power-on

CC

reset threshold voltage. To protect the memory contents from accidental corruption, it is

advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read

Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write

Disable (WDS) instructions.

14/37

M93C86, M93C76, M93C66, M93C56, M93C46

Instructions

Figure 4.

READ, WRITE, WEN, WDS sequences

Read

S

D

Q

1 1 0 An

A0

Qn

Q0

ADDR

DATA OUT

OP

CODE

Write

S

D

Q

CHECK

STATUS

1 0 1 An

A0 Dn

D0

ADDR

DATA IN

BUSY

READY

OP

CODE

Write

Enable

S

D

Write

Disable

S

1 0 0 1 1 Xn X0

D

1 0 0 0 0 Xn X0

OP

CODE

AI00878d

1. For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Table 7..

5.3

Erase Byte or Word

The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or

word) to 1. Once the address has been correctly decoded, the falling edge of the Chip

Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be

detected by monitoring the READY/BUSY line, as described in the READY/BUSY status

section.

15/37

Instructions

M93C86, M93C76, M93C66, M93C56, M93C46

5.4

Write

For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and

address bits. These form the byte or word that is to be written. As with the other bits, Serial

Data Input (D) is sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the Chip Select Input (S) must be taken low before

the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after

this specific time frame, the self-timed programming cycle will not be started, and the

addressed location will not be programmed. The completion of the cycle can be detected by

monitoring the READY/BUSY line, as described later in this document.

Once the Write cycle has been started, it is internally self-timed (the external clock signal on

Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is

automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase

instruction before a Write Data to Memory (WRITE) instruction.

Figure 5.

ERASE, ERAL sequences

ERASE

S

D

Q

CHECK

STATUS

1 1 1 An

A0

ADDR

BUSY

READY

OP

CODE

ERASE

ALL

S

D

Q

CHECK

STATUS

1 0 0 1 0 Xn X0

ADDR

OP

BUSY

READY

CODE

AI00879B

1. For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..

5.5

Erase All

The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set

to 1). The format of the instruction requires that a dummy address be provided. The Erase

cycle is conducted in the same way as the Erase instruction (ERASE). The completion of

the cycle can be detected by monitoring the READY/BUSY line, as described in the

READY/BUSY status section.

16/37

M93C86, M93C76, M93C66, M93C56, M93C46

Instructions

5.6

Write All

As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with

same Data (WRAL) instruction requires that a dummy address be provided. As with the

Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same

Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.

This value is written to all the addresses of the memory device. The completion of the cycle

can be detected by monitoring the READY/BUSY line, as described next.

Figure 6.

WRAL sequence

WRITE

ALL

S

CHECK

STATUS

D

Q

1 0 0 0 1 Xn X0 Dn

D0

ADDR

DATA IN

BUSY

READY

OP

CODE

AI00880C

1. For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..

17/37

READY/BUSY status

M93C86, M93C76, M93C66, M93C56, M93C46

6

READY/BUSY status

While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL

instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.

(Please note, though, that there is an initial delay, of t

, before this status information

SLSH

becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write

cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)

indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)

remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is

decoded.

7

8

Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

Common I/O operation

Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a

current limiting resistor, to form a common, single-wire data bus. Some precautions must be

taken when operating the memory in this way, mostly to prevent a short circuit current from

flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output

(Q). Please see the application note AN394 for details.

18/37

M93C86, M93C76, M93C66, M93C56, M93C46

Clock pulse counter

9

Clock pulse counter

In a noisy environment, the number of pulses received on Serial Clock (C) may be greater

than the number delivered by the master (the microcontroller). This can lead to a

misalignment of the instruction of one or more bits (as shown in Figure 7.) and may lead to

the writing of erroneous data at an erroneous address.

To combat this problem, the M93Cx6 has an on-chip counter that counts the clock pulses

from the start bit until the falling edge of the Chip Select Input (S). If the number of clock

pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL

instruction is aborted, and the contents of the memory are not modified.

The number of clock cycles expected for each instruction, and for each member of the

M93Cx6 family, are summarized in Table 5. to Table 7.. For example, a Write Data to

Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the

x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is:

1 Start bit

+ 2 Op-code bits

+ 9 Address bits

+ 8 Data bits

Figure 7.

Write sequence with one clock glitch

S

C

D

An

An-1

Glitch

An-2

START

"0"

"1"

D0

ADDRESS AND DATA

ARE SHIFTED BY ONE BIT

WRITE

AI01395

19/37

Maximum rating

M93C86, M93C76, M93C66, M93C56, M93C46

10

Maximum rating

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 8.

Symbol

Absolute maximum ratings

Parameter

Min.

Max.

Unit

T_A

Ambient operating temperature

Storage temperature

–40

–65

130

150

°C

T_STG

PDIP

260⁽¹⁾

T_LEADlead temperature during soldering

other packages

See note ⁽²⁾

°C

V

V_OUT

V_IN

Output range (Q = V_OHor Hi-Z)

Input range

–0.50

–4000

V_CC+0.5

V_CC+1

6.5

V

V_CC

V_ESD

Supply voltage

V

Electrostatic discharge voltage (human body model)⁽³⁾

4000

V

1. T_LEADmax must not be applied for more than 10 s.

2. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK^®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω).

20/37

M93C86, M93C76, M93C66, M93C56, M93C46

DC and AC parameters

11

DC and AC parameters

This section summarizes the operating and measurement conditions, and the dc and ac

characteristics of the device. The parameters in the dc and ac characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

Table 9.

Symbol

Operating conditions (M93Cx6)

Parameter

Min.

Max.

Unit

V_CC

T_A

Supply voltage

4.5

–40

5.5

85

V

Ambient operating temperature (device grade 6)

Ambient operating temperature (device grade 3)

°C

125

Table 10. Operating conditions (M93Cx6-W)

Symbol

Parameter

Min.

Max.

Unit

V_CC

Supply voltage

2.5

–40

5.5

85

V

Ambient operating temperature (device grade 6)

Ambient operating temperature (device grade 3)

°C

T_A

125

Table 11. Operating conditions (M93Cx6-R)

Symbol

Parameter

Min.

Max.

Unit

V_CC

T_A

Supply voltage

Ambient operating temperature (device grade 6)

1.8

5.5

85

V

–40

°C

(1)

Table 12. AC measurement conditions (M93Cx6)

Symbol

Parameter

Min.

Max.

Unit

C_L

Load capacitance

100

pF

ns

V

Input rise and fall times

50

Input pulse voltages

0.4 V to 2.4 V

1.0 V and 2.0 V

0.8 V and 2.0 V

Input timing reference voltages

Output timing reference voltages

V

1. Output Hi-Z is defined as the point where data out is no longer driven.

21/37

DC and AC parameters

M93C86, M93C76, M93C66, M93C56, M93C46

(1)

Table 13. AC measurement conditions (M93Cx6-W and M93Cx6-R)

Symbol

Parameter

Min.

Max.

Unit

C_L

Load capacitance

100

pF

ns

V

Input rise and fall times

50

Input pulse voltages

0.2V_CCto 0.8V_CC

0.3V_CCto 0.7V_CC

Input timing reference voltages

Output timing reference voltages

V

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 8.

AC testing input output waveforms

M93CXX

2.4V

2V

2.0V

0.8V

1V

0.4V

INPUT

OUTPUT

M93CXX-W & M93CXX-R

0.8V

0.2V

CC

0.7V

CC

0.3V

CC

AI02553

(1)

Table 14. Capacitance

Symbol

C_OUT

C_IN

Parameter

Test condition

Min

Max

Unit

pF

Output capacitance

Input capacitance

V_OUT= 0V

V_IN= 0V

5

1. Sampled only, not 100% tested, at T_A= 25 °C and a frequency of 1 MHz.

Table 15. DC characteristics (M93Cx6, device grade 6)

Symbol

Parameter

Test condition

Min.

Max.

Unit

I_LI

Input leakage current

Output leakage current

0V ≤V_IN≤V_CC

2.5

µA

I_LO

0V ≤V_OUT≤V_CC, Q in Hi-Z

V

_CC= 5 V, S = V_IH, f = 2 MHz,

I_CC

Supply current

2

mA

µA

Q = open

V

_CC= 5 V, S = V_SS, C = V_SS

,

I_CC1

Supply current (Standby)

ORG = V_SSor V_CC

,

15

pin7 = V_CC, V_SSor Hi-Z

(1)

V_IL

Input low voltage

Input high voltage

Output low voltage

Output high voltage

V_CC= 5 V 10%

–0.45

2

0.8

V

(1)

V_IH

V_CC= 5 V 10%

V_CC+ 1

0.4

(1)

V_OL

V_CC= 5 V, I_OL= 2.1 mA

V_CC= 5 V, I_OH= –400 µA

(1)

V_OH

0.8V_CC

1. The input and output levels are compatible with TTL logic levels.

22/37

M93C86, M93C76, M93C66, M93C56, M93C46

DC and AC parameters

Table 16. DC characteristics (M93Cx6, device grade 3)

Symbol

Parameter

Test condition

Min.

Max.

Unit

I_LI

Input leakage current

Output leakage current

0V ≤V_IN≤V_CC

2.5

µA

I_LO

0V ≤V_OUT≤V_CC, Q in Hi-Z

V_CC= 5 V, S = V_IH, f = 2 MHz,

Q = open

I_CC

Supply current

2

mA

µA

V_CC= 5 V, S = V_SS, C = V_SS

,

I_CC1

Supply current (Standby)

ORG = V_SSor V_CC

,

15

pin7 = V_CC, V_SSor Hi-Z

V_IL

V_IH

Input low voltage

Input high voltage

Output low voltage

Output high voltage

V_CC= 5 V 10%

–0.45

2

0.8

V_CC+ 1

0.4

V

V_CC= 5 V 10%

V_OL

V_OH

V_CC= 5 V, I_OL= 2.1 mA

V_CC= 5 V, I_OH= –400 µA

0.8 V_CC

Table 17. DC characteristics (M93Cx6-W, device grade 6)

Symbol

Parameter

Test condition

Min.

Max.

Unit

I_LI

Input leakage current

Output leakage current

0V ≤V_IN≤V_CC

2.5

µA

I_LO

0V ≤V_OUT≤V_CC, Q in Hi-Z

V_CC= 5 V, S = V_IH, f = 2 MHz,

Q = open

2

1

mA

Supply current (CMOS

inputs)

I_CC

V_CC= 2.5 V, S = V_IH, f = 2 MHz,

Q = open

V

_CC= 2.5 V, S = V_SS, C = V_SS

ORG = V_SSor V_CC

pin7 = V_CC, V_SSor Hi-Z

,

I_CC1

Supply current (Standby)

,

5

µA

V_IL

Input low voltage (D, C, S)

Input high voltage (D, C, S)

–0.45 0.2 V_CC

0.7 V_CCV_CC+ 1

0.4

V

V_IH

V

_CC= 5 V, I_OL= 2.1 mA

_CC= 2.5 V, I_OL= 100 µA

_CC= 5 V, I_OH= –400 µA

V_CC= 2.5 V, I_OH= –100 µA

V_OL

Output low voltage (Q)

Output high voltage (Q)

V

0.2

V

0.8 V_CC

V_OH

V_CC–0.2

23/37

DC and AC parameters

M93C86, M93C76, M93C66, M93C56, M93C46

Table 18. DC characteristics (M93Cx6-W, device grade 3)

Symbol

Parameter

Test condition

Min.⁽¹⁾Max. ⁽¹⁾Unit

I_LI

Input leakage current

Output leakage current

0V ≤V_IN≤V_CC

2.5

µA

I_LO

0V ≤V_OUT≤V_CC, Q in Hi-Z

V_CC= 5 V, S = V_IH, f = 2 MHz,

Q = open

2

1

mA

Supply current (CMOS

inputs)

I_CC

V_CC= 2.5 V, S = V_IH, f = 2 MHz,

Q = open

V_CC= 2.5 V, S = V_SS, C = V_SS

ORG = V_SSor V_CC

pin7 = V_CC, V_SSor Hi-Z

,

I_CC1

Supply current (Standby)

,

5

µA

Input low voltage (D, C,

S)

V_IL

V_IH

–0.45

0.2 V_CC

V

Input high voltage (D, C,

S)

0.7 V_CCV_CC+ 1

V

_CC= 5 V, I_OL= 2.1 mA

_CC= 2.5 V, I_OL= 100 µA

_CC= 5 V, I_OH= –400 µA

V_CC= 2.5 V, I_OH= –100 µA

0.4

0.2

V

V_OL

Output low voltage (Q)

Output high voltage (Q)

V

0.8 V_CC

V_OH

V_CC–0.2

1. New product: identified by Process Identification letter W or G or S.

Table 19. DC characteristics (M93Cx6-R)

Symbol

Parameter

Test condition

Min.⁽¹⁾Max. ⁽¹⁾Unit

I_LI

Input leakage current

Output leakage current

0V ≤V_IN≤V_CC

2.5

µA

I_LO

0V ≤V_OUT≤V_CC, Q in Hi-Z

V_CC= 5 V, S = V_IH, f = 2 MHz,

Q = open

2

1

mA

Supply current (CMOS

inputs)

I_CC

V_CC= 1.8 V, S = V_IH, f = 1 MHz,

Q = open

V

_CC= 1.8 V, S = V_SS, C = V_SS

,

I_CC1

Supply current (Standby)

ORG = V_SSor V_CC

,

2

µA

pin7 = V_CC, V_SSor Hi-Z

Input low voltage (D, C,

S)

V_IL

V_IH

–0.45 0.2 V_CC

0.8 V_CCV_CC+ 1

V

Input high voltage (D, C,

S)

V_OL

V_OH

Output low voltage (Q)

Output high voltage (Q)

V_CC= 1.8 V, I_OL= 100 µA

V_CC= 1.8 V, I_OH= –100 µA

0.2

V

V_CC–0.2

1. This product is under development. For more information, please contact your nearest ST sales office.

24/37

M93C86, M93C76, M93C66, M93C56, M93C46

DC and AC parameters

Table 20. AC characteristics (M93Cx6, device grade 6 or 3)

Test conditions specified in Table 12. and Table 9.

Symbol

Alt.

Parameter

Min.

Max.

Unit

f_C

f_SK

Clock frequency

D.C.

50

2

MHz

ns

t_SLCH

Chip Select low to Clock high

Chip Select setup time

M93C46, M93C56, M93C66

50

ns

t_SHCH

t_CSS

Chip Select setup time

M93C76, M93C86

(1)

t_SLSH

t_CS

t_SKH

t_SKL

t_DIS

t_DIH

t_SKS

t_CSH

t_SV

Chip Select low to Chip Select high

Clock high time

200

50

ns

ms

(2)

t_CHCL

(2)

t_CLCH

Clock low time

t_DVCH

t_CHDX

t_CLSH

t_CLSL

t_SHQV

t_SLQZ

t_CHQL

t_CHQV

t_W

Data in setup time

Data in hold time

50

Clock setup time (relative to S)

Chip Select hold time

50

0

Chip Select to READY/BUSY status

Chip Select low to output Hi-Z

Delay to output low

200

100

200

5

t_DF

t_PD0

t_PD1

t_WP

Delay to output valid

Erase or Write cycle time

1. Chip Select Input (S) must be brought low for a minimum of t_SLSHbetween consecutive instruction cycles.

2. t_CHCL+ t_CLCH≥ 1 / f_C.

Table 21. AC characteristics (M93Cx6-W, device grade 6)

Test conditions specified in Table 13. and Table 10.

Symbol

Alt.

Parameter

Clock frequency

Min.

Max.

Unit

f_C

f_SK

D.C.

50

2

MHz

ns

t_SLCH

t_SHCH

Chip Select low to Clock high

Chip Select setup time

Chip Select low to Chip Select high

Clock high time

t_CSS

t_CS

50

(1)

t_SLSH

200

50

(2)

t_CHCL

t_SKH

t_SKL

t_DIS

t_DIH

t_SKS

t_CSH

t_SV

(2)

t_CLCH

Clock low time

t_DVCH

t_CHDX

t_CLSH

t_CLSL

t_SHQV

Data in setup time

Data in hold time

50

Clock setup time (relative to S)

Chip Select hold time

50

0

Chip Select to READY/BUSY status

200

25/37

DC and AC parameters

M93C86, M93C76, M93C66, M93C56, M93C46

Table 21. AC characteristics (M93Cx6-W, device grade 6)

Test conditions specified in Table 13. and Table 10.

Symbol

Alt.

Parameter

Min.

Max.

Unit

t_SLQZ

t_CHQL

t_CHQV

t_W

t_DF

t_PD0

t_PD1

t_WP

Chip Select low to output Hi-Z

Delay to output low

100

200

5

ns

ms

Delay to output valid

Erase or Write cycle time

1. Chip Select Input (S) must be brought low for a minimum of t_SLSHbetween consecutive instruction cycles.

2. t_CHCL+ t_CLCH≥ 1 / f_C.

Table 22. AC characteristics (M93Cx6-W, device grade 3)

Test conditions specified in Table 13. and Table 10.

Symbol

Alt.

Parameter

Clock frequency

Min.

Max.

Unit

f_C

f_SK

D.C.

50

2

MHz

ns

ms

t_SLCH

t_SHCH

Chip Select low to Clock high

Chip Select set-up time

Chip Select low to Chip Select high

Clock high time

t_CSS

t_CS

50

(1)

t_SLSH

200

50

(2)

t_CHCL

t_SKH

t_SKL

t_DIS

t_DIH

t_SKS

t_CSH

t_SV

(2)

t_CLCH

Clock low time

t_DVCH

t_CHDX

t_CLSH

t_CLSL

t_SHQV

t_SLQZ

t_CHQL

t_CHQV

t_W

Data in set-up time

Data in hold time

50

Clock set-up time (relative to S)

Chip Select hold time

50

0

Chip Select to READY/BUSY status

Chip Select low to output Hi-Z

Delay to output low

200

100

200

5

t_DF

t_PD0

t_PD1

t_WP

Delay to output valid

Erase or Write cycle time

1. Chip Select Input (S) must be brought low for a minimum of t_SLSHbetween consecutive instruction cycles.

2. t_CHCL+ t_CLCH≥ 1 / f_C.

26/37

M93C86, M93C76, M93C66, M93C56, M93C46

Table 23. AC characteristics (M93Cx6-R)

DC and AC parameters

Test conditions specified in Table 13. and Table 11.

Symbol

Alt.

Parameter

Min.⁽¹⁾

Max.⁽¹⁾

Unit

f_C

f_SK

Clock frequency

D.C.

250

50

1

MHz

ns

ms

t_SLCH

t_SHCH

Chip Select low to Clock high

Chip Select setup time

Chip Select low to Chip Select high

Clock high time

t_CSS

t_CS

(2)

t_SLSH

250

100

0

(3)

t_CHCL

t_SKH

t_SKL

t_DIS

t_DIH

t_SKS

t_CSH

t_SV

(3)

t_CLCH

Clock low time

t_DVCH

t_CHDX

t_CLSH

t_CLSL

t_SHQV

t_SLQZ

t_CHQL

t_CHQV

t_W

Data in setup time

Data in hold time

Clock setup time (relative to S)

Chip Select hold time

Chip Select to READY/BUSY status

Chip Select low to output Hi-Z

Delay to output low

400

200

400

10

t_DF

t_PD0

t_PD1

t_WP

Delay to output valid

Erase or Write cycle time

1. This product is under development. For more information, please contact your nearest ST sales office.

2. Chip Select Input (S) must be brought low for a minimum of t_SLSHbetween consecutive instruction cycles.

3. t_CHCL+ t_CLCH≥ 1 / f_C.

Figure 9.

Synchronous timing (start and op-code input)

tCLSH

tCHCL

C

S

D

tSHCH

tCLCH

tDVCH

START

tCHDX

OP CODE

START

OP CODE INPUT

AI01428

27/37

DC and AC parameters

M93C86, M93C76, M93C66, M93C56, M93C46

Figure 10. Synchronous timing (Read or Write)

C

tCLSL

S

tDVCH

tCHDX

tCHQV

tSLSH

A0

D

Q

An

tSLQZ

tCHQL

Hi-Z

Q15/Q7

Q0

ADDRESS INPUT

DATA OUTPUT

AI00820C

Figure 11. Synchronous timing (Read or Write)

tSLCH

C

S

tCLSL

tDVCH

tCHDX

A0/D0

tSLSH

D

Q

An

tSHQV

BUSY

tSLQZ

READY

Hi-Z

tW

ADDRESS/DATA INPUT

WRITE CYCLE

AI01429

28/37

M93C86, M93C76, M93C66, M93C56, M93C46

Package mechanical data

12

Package mechanical data

In order to meet environmental requirements, ST offers the M93C86, M93C76, M93C66,

®

M93C56 and M93C46 in ECOPACK packages. These packages have a lead-free second

level interconnect. The category of second level interconnect is marked on the package and

on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings

related to soldering conditions are also marked on the inner box label. ECOPACK is an ST

trademark. ECOPACK specifications are available at www.st.com.

Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package

outline

E

b2

A2

A1

A

L

c

b

e

eA

eB

D

8

1

E1

PDIP-B

1. Drawing is not to scale.

Table 24. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package

mechanical data

millimeters

Min.

inches⁽¹⁾

Symbol

Typ.

Max.

Typ.

Min.

Max.

A

A1

A2

b

5.33

0.2098

0.38

2.92

0.36

1.14

0.2

9.02

7.62

6.1

-

0.015

0.115

0.0142

0.0449

0.0079

0.3551

0.3

3.3

4.95

0.56

1.78

0.36

10.16

8.26

7.11

-

0.1299

0.0181

0.0598

0.0098

0.365

0.3098

0.25

0.1949

0.022

0.0701

0.0142

0.4

0.46

1.52

0.25

9.27

7.87

6.35

2.54

7.62

b2

c

D

E

0.3252

0.2799

-

E1

e

0.2402

-

0.1

eA

eB

L

-

0.3

-

10.92

3.81

0.4299

0.15

3.3

2.92

0.1299

0.115

1. Values in inches are converted from mm and rounded to 4 decimal digits.

29/37

Package mechanical data

M93C86, M93C76, M93C66, M93C56, M93C46

Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package

outline

h x 45˚

A2

A

c

ccc

b

e

0.25 mm

D

GAUGE PLANE

k

8

1

E1

E

L

A1

L1

SO-A

1. Drawing is not to scale.

Table 25. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package

data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

A1

A2

b

1.75

0.25

0.0689

0.0098

0.1

0.0039

0.0492

0.011

1.25

0.28

0.17

0.48

0.23

0.1

5

0.0189

0.0091

0.0039

0.1969

0.2441

0.1575

-

c

0.0067

ccc

D

4.9

6

4.8

5.8

3.8

-

0.1929

0.2362

0.1535

0.05

0.189

0.2283

0.1496

-

E

6.2

4

E1

e

3.9

1.27

-

h

0.25

0°

0.5

8°

0.0098

0°

0.0197

8°

k

L

0.4

1.27

0.0157

0.05

L1

1.04

0.0409

1. Values in inches are converted from mm and rounded to 4 decimal digits.

30/37

M93C86, M93C76, M93C66, M93C56, M93C46

Package mechanical data

Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, outline

e

b

D

L1

L3

E

E2

L

A

D2

ddd

A1

UFDFPN-01

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V_SS. It must not be

allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering

process.

3. The circle in the top view of the package indicates the position of pin 1.

Table 26. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

A1

b

0.55

0.02

0.25

2

0.45

0

0.6

0.05

0.3

2.1

1.7

3.1

0.3

-

0.0217

0.0008

0.0098

0.0787

0.063

0.0177

0

0.0236

0.002

0.0118

0.0827

0.0669

0.122

0.0118

-

0.2

1.9

1.5

2.9

0.1

-

0.0079

0.0748

0.0591

0.1142

0.0039

-

D

D2

E

1.6

3

0.1181

0.0079

0.0197

0.0177

E2

e

0.2

0.5

0.45

L

0.4

0.5

0.15

0.0157

0.0197

0.0059

L1

L3

ddd⁽²⁾

0.3

0.0118

0.08

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

measuring.

31/37

Package mechanical data

M93C86, M93C76, M93C66, M93C56, M93C46

Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline

D

8

5

c

E1

E

1

4

α

A1

L

A

A2

L1

CP

b

e

TSSOP8AM

1. Drawing is not to scale.

Table 27. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

millimeters

Min.

inches⁽¹⁾

Symbol

Typ.

Max.

Typ.

Min.

Max.

A

1.2

0.15

1.05

0.3

0.2

0.1

3.1

-

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.122

A1

0.05

0.8

0.002

0.0315

0.0075

0.0035

A2

1

0.0394

b

0.19

0.09

c

CP

D

3

0.65

6.4

4.4

0.6

1

2.9

-

0.1181

0.0256

0.252

0.1142

-

e

-

E

6.2

4.3

0.45

6.6

4.5

0.75

0.2441

0.1693

0.0177

0.2598

0.1772

0.0295

E1

0.1732

0.0236

0.0394

L

L1

α

0°

8

8°

0°

8

8°

N (pin number)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

32/37

M93C86, M93C76, M93C66, M93C56, M93C46

Part numbering

13

Part numbering

Table 28. Ordering information scheme

Example:

M93C86

–

W MN 6

T

P /S

Device type

M93 = MICROWIRE serial access EEPROM

Device function

86 = 16 Kbit (2048 x 8)

76 = 8 Kbit (1024 x 8)

66 = 4 Kbit (512 x 8)

56 = 2 Kbit (256 x 8)

46 = 1 Kbit (128 x 8)

Operating voltage

blank = V_CC= 4.5 to 5.5 V

W = V_CC= 2.5 to 5.5 V

R = V_CC= 1.8 to 5.5 V

Package

BN = PDIP8

MN = SO8 (150 mils width)

MB = UFDFPN8 (MLP8)

DW = TSSOP8 (169 mils width)

Device grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3 = Device tested with high reliability certified flow⁽¹⁾

Automotive temperature range (–40 to 125 °C)

.

Packing

blank = standard packing

T = tape and reel packing

Plating technology

P or G = ECOPACK® (RoHS compliant)

Process⁽²⁾

/W or /S = F6SP36%

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive

environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801.

Please ask your nearest ST sales office for a copy.

2. Used only for device grade 3.

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

33/37

Part numbering

M93C86, M93C76, M93C66, M93C56, M93C46

Table 29. Available M93C46-x products (package, voltage range, temperature

grade)

M93C46

4.5 V to 5.5 V

M93C46-W

2.5 V to 5.5 V

M93C46-R

1.8 V to 5.5 V

Package

Range 6

Range 3

DIP8 (BN)

SO8 (MN)

Range 3

-

Range 6

Range 3

Range 6

Range 3

Range 6

Range 3

TSSOP (DW)

-

Table 30. Available M93C56-x products (package, voltage range, temperature

grade)

M93C56

4.5 V to 5.5 V

M93C56-W

2.5 V to 5.5 V

M93C56-R

1.8 V to 5.5 V

Package

Range 6

Range3

Range 6

Range3

SO8 (MN)

Range 6

TSSOP (DW)

-

Range 6

Table 31. Available M93C66-x products (package, voltage range, temperature

grade)

M93C66

4.5 V to 5.5 V

M93C66-W

2.5 V to 5.5 V

M93C66-R

1.8 V to 5.5 V

Package

Range 6

Range3

Range 6

Range3

SO8 (MN)

-

Range 6

Range3

TSSOP (DW)

-

UFDFPN 2 x 3 mm (MB)

-

Range 6

Table 32. Available M93C76-x products (package, voltage range, temperature

grade)

M93C76

4.5 V to 5.5 V

M93C76-W

2.5 V to 5.5 V

M93C76-R

1.8 V to 5.5 V

Package

Range 6

Range3

SO8 (MN)

Range3

-

TSSOP (DW)

Range 6

Table 33. Available M93C86-x products (package, voltage range, temperature

grade)

M93C86

4.5 V to 5.5 V

M93C86-W

2.5 V to 5.5 V

M93C86-R

1.8 V to 5.5 V

Package

DIP8 (BN)

SO8 (MN)

-

Range 6

-

Range 6

Range3

Range 6

Range3

TSSOP (DW)

-

Range 6

34/37

M93C86, M93C76, M93C66, M93C56, M93C46

Revision history

14

Revision history

Table 34. Document revision history

Date

Revision

Changes

Document reformatted, and reworded, using the new template.

Temperature range 1 removed. TSSOP8 (3x3mm) package added. New

products, identified by the process letter W, added, with fc(max)

increased to 1MHz for -R voltage range, and to 2MHz for all other

ranges (and corresponding parameters adjusted)

04-Feb-2003

2.0

Value of standby current (max) corrected in DC characteristics tables for

-W and -R ranges

26-Mar-2003

04-Apr-2003

2.1

2.2

V_OUTand V_INseparated from V_IOin the Absolute Maximum Ratings

table

Values corrected in AC characteristics tables for -W range (t_SLSH, t_DVCH

t_CLSL) for devices with Process Identification Letter W

,

23-May-2003

27-May-2003

2.3

2.4

Standby current corrected for -R range

Turned-die option re-instated in Ordering Information Scheme

Table of contents, and Pb-free options added. Temperature range 7

added. V_IL(min) improved to –0.45V.

25-Nov-2003

3.0

MLP package added. Absolute Maximum Ratings for V_IO(min) and

V_CC(min) changed. Soldering temperature information clarified for

RoHS compliant devices. Device grade information clarified. Process

identification letter “G” information added

30-Mar-2004

4.0

M93C06 removed. Device grade information further clarified. Process

identification letter “S” information added. Turned-die package option

removed. Product list summary added.

16-Aug-2004

27-Oct-2005

5.0

6.0

current product/new product distinction removed. I_CCand I_CC1values for

current product removed from tables 15, 16 and 17 and AC

characteristics for current product removed from Tables 20 and 21.

Clock rate added to Features.

“Q = open” added to I_CCTest conditions in DC Characteristics Tables 15,

16, 17, 18 and 19.

Process added to Table 28.: Ordering information scheme. POWER ON

DATA PROTECTION section removed, replaced by Operating features

and Active Power and Standby Power modes. Initial delivery state

added.

SO8N and TSSOP8 packages updated. PDIP-specific T_LEADadded to

Table 8.: Absolute maximum ratings.

35/37

Revision history

M93C86, M93C76, M93C66, M93C56, M93C46

Table 34. Document revision history (continued)

Date

Revision

Changes

Document reformatted. TSSOP8 3 × 3 mm (DS) package removed.

Erase/Write Enable (EWEN) instruction replaced by Write Enable

(WEN). Erase/Write Disable (EWDS) instruction replaced by Write

Disable (WDS).

Section 7: Initial delivery state modified, ACTIVE POWER AND

STANDBY POWER MODES section removed.

I_CC1test conditions modified in Table 15, Table 16, Table 17, Table 18

and Table 19. Note 1 added to Table 15.

31-Jul-2007

7

t_Wparameter description modified in Table 20, Table 21, Table 22 and

Table 23..

SO8 narrow and UFDFPN8 package specifications updated (see

Section 12: Package mechanical data).

Table 29, Table 30, Table 31, Table 32 and Table 33 added.

Blank option removed under Plating technology in Table 27: TSSOP8 –

8 lead thin shrink small outline, package mechanical data.

Section 2: Connecting to the serial bus added. Device grade 7 removed.

Small text changes.

M93C76-R root part number added.

Section 2: Connecting to the serial bus modified (pull-down resitor

added to Figure 3: Bus master and memory devices on the serial bus

and paragraph added).

Section 3.1.2: Power-up conditions corrected.

29-Jan-2007

8

T_LEADmodified in Table 8: Absolute maximum ratings.

V_OHmin guaranteed at a higher value in DC characteristics tables 15,

16, 17 and 18.

M93C56-R is also offered in TSSOP8 package (see Table 30).

Package mechanical inch values calculated from mm and rounded to 4

decimal digits in Section 12: Package mechanical data

TSSOP8 (DW) package specifications updated.

36/37

M93C86, M93C76, M93C66, M93C56, M93C46

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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

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All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

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37/37

型号:	M93C46-WMN6P
Brand Name：	STMicroelectronics
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, SOP-8
针数：	8
Reach Compliance Code：	compliant
HTS代码：	8542.32.00.51
风险等级：	1.17
备用内存宽度：	8
最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	40
耐久性：	1000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
内存密度：	1024 bit
内存集成电路类型：	EEPROM
内存宽度：	16
湿度敏感等级：	1
功能数量：	1
端子数量：	8
字数：	64 words
字数代码：	64
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	64X16
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260
电源：	3/5 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
串行总线类型：	MICROWIRE
最大待机电流：	0.00001 A
子类别：	EEPROMs
最大压摆率：	0.001 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm
最长写入周期时间 (tWC)：	5 ms
写保护：	SOFTWARE
Base Number Matches：	1

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