MAX20029/MAX20029B/
MAX20029C/MAX20029D
Automotive Quad/Triple Low-Voltage
Step-Down DC-DC Converters
junction temperature at high power dissipation in some
PMIC applications. Furthermore, the solder mask around
the IC area on both top and bottom layers can be removed
to radiate the heat directly into the air. The maximum
allowable power dissipation in the IC is as follows:
Inductor Selection
The PMICs are optimized for use with a 1.5µH inductor
on outputs configured for 0.5A, 1A, or 1.5A, and a 1.0µH
inductor for an output configured for 2A or 3A. For output
voltagesꢀlessꢀthanꢀ0.9V,ꢀ0.47μHꢀisꢀrecommended.
T
− T
(
)
J(MAX)
A
Input Capacitor
P
=
MAX
θ
+ θ
CA
The PMICs are designed to operate with a single 2.2µF
ceramic bypass capacitor on each PV_ input. Phase
interleaving of the four buck converters contributes to
a lower required input capacitance by canceling input
ripple currents. Place the bypass capacitors as close as
possible to their corresponding PV_ input to ensure the
best EMI and jitter performance.
JC
where T
is the maximum junction temperature
J(MAX)
(+150°C), T ꢀisꢀtheꢀambientꢀairꢀtemperature,ꢀθ (3°C/W
A
JC
for the 28-pin TQFN) is the thermal resistance from the
junctionꢀtoꢀtheꢀcase,ꢀandꢀθ is the thermal resistance from
CA
the case to the surrounding air through the PCB, copper
traces,ꢀandꢀtheꢀpackageꢀmaterials.ꢀθ
is directly related
CA
to system-level variables and can be modified to increase
the maximum power dissipation.
Output Capacitor
All outputs of the PMICs are optimized for use with ceramic
capacitors.
The TQFN package has an exposed thermal pad on its
underside. This pad provides a low thermal-resistance path
for heat transfer into the PCB. This low thermally resistive
path carries a majority of the heat away from the IC. The
PCB is effectively a heatsink for the IC. The exposed pad
should be connected to a large ground plane for proper
thermal and electrical performance. The minimum size
of the ground plane is dependent upon many system
variables. To create an efficient path, the exposed pad
should be soldered to a thermal landing, which is connected
to the ground plane by thermal vias. The thermal landing
should be at least as large as the exposed pad and can be
made larger depending on the amount of free space from
the exposed pad to the other pin landings. A sample layout
is available on the evaluation kit to speed designs.
For
V
V
> 0.2:
OUT/ IN
20
C
C
=
µF
OUT_MIN
V
OUT
33
=
µF
OUT_NOM
V
OUT
For
V
V
ꢀꢀ≤ꢀ0.2:
OUT/ IN
40
C
C
=
µF
OUT_MIN
V
OUT
60
=
µF
OUT_NOM
PCB Layout Guidelines
V
OUT
Careful PCB layout is critical to achieve low switching
lossesꢀandꢀclean,ꢀstableꢀoperation.ꢀUseꢀaꢀmultilayerꢀboardꢀ
whenever possible for better noise immunity and power
dissipation. Follow these guidelines for good PCB layout:
Additional output capacitance can be used if better volt-
age ripple or load-transient response is required (see
Figure 2). To guarantee stability, it is recommended that
the phase margin be measured under the worst-case
deration of the output capacitor(s). Due to the soft-start
sequence, the PMICs are unable to drive arbitrarily large
output capacitors.
1)ꢀ UseꢀaꢀlargeꢀcontiguousꢀcopperꢀplaneꢀunderꢀtheꢀPMICꢀ
packages. Ensure that all heat-dissipating components
have adequate cooling.
2) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. The high current path comprising
of input capacitor, inductor, and the output capacitor
should be as short as possible.
Thermal Considerations
How much power the package can dissipate strongly
depends on the mounting method of the IC to the PCB
andꢀ theꢀ copperꢀ areaꢀ forꢀ cooling.ꢀ Usingꢀ theꢀ JEDECꢀ testꢀ
standard, the maximum power dissipation allowed is
2285mW in the TQFN package. More power dissipation
can be handled by the package if great attention is given
during PCB layout. For example, using the top and bottom
copper as a heatsink and connecting the thermal vias to
one of the middle layers (GND) transfers the heat from the
package into the board more efficiently, resulting in lower
3) Keep the power traces and load connections short. This
practiceꢀisꢀessentialꢀforꢀhighꢀefficiency.ꢀUseꢀthickꢀcopperꢀ
PCBs (2oz vs. 1oz) to enhance full-load efficiency.
4)ꢀ Useꢀ aꢀ singleꢀ groundꢀ planeꢀ toꢀ reduceꢀ theꢀ chanceꢀ ofꢀ
ground potential differences. With a single ground
plane, enough isolation between analog return signals
and high-power signals must be maintained.
Maxim Integrated
│ 13
www.maximintegrated.com