S in g le /Du a l/Qu a d , Lo w -P o w e r, S in g le -S u p p ly,
Ra il-t o -Ra il I/O Op Am p s w it h S h u t d o w n
_______________De t a ile d De s c rip t io n
Ra il-t o -Ra il In p u t S t a g e
The MAX4330–MAX4334 have rail-to-rail input and out-
MAX4330
MAX4331
MAX4332
MAX4333
MAX4334
p ut s ta g e s tha t a re s p e c ific a lly d e s ig ne d for low-
voltage, single-supply operation. The input stage con-
sists of se p a ra te NPN a nd PNP d iffe re ntia l sta ge s,
which operate together to provide a common-mode
range extending to 0.25V beyond both supply rails. The
R3
crossover region, which occurs halfway between V
CC
and V , is extended to minimize degradation in CMRR
EE
caused by mismatched input pairs. The input offset volt-
age is typically 250µV. Low offset voltage, high band-
wid th, ra il-to-ra il c ommon-mod e inp ut ra ng e , a nd
rail-to-rail outputs make this family of op amps an excel-
lent choice for precision, low-voltage data-acquisition
systems.
R3 = R1 R2
R1
R2
Since the input stage consists of NPN and PNP pairs,
the input bias current changes polarity as the input volt-
age passes through the crossover region. Match the
effective impedance seen by each input to reduce the
offset error due to input bias currents flowing through
external source impedances (Figures 1a and 1b). The
c omb ina tion of hig h s ourc e imp e d a nc e with inp ut
capacitance (amplifier input capacitance plus stray
capacitance) creates a parasitic pole that produces an
underdamped signal response. Reducing input capaci-
tance or placing a small capacitor across the feedback
resistor improves response.
0–MAX34
Figure 1a. Reducing Offset Error Due to Bias Current
(Noninverting)
MAX4330
MAX4331
MAX4332
MAX4333
The MAX4330–MAX4334’s inputs are protected from
large differential input voltages by internal 1kΩ series
resistors and back-to-back triple diode stacks across
the inputs (Figure 2). For differential input voltages
(much less than 1.8V), input resistance is typically
2.3MΩ. For differential input voltages greater than 1.8V,
input resistance is around 2kΩ, and the input bias cur-
rent can be approximated by the following equation:
MAX4334
R3
R3 = R1 R2
I
= (V
- 1.8V) / 2kΩ
BIAS
DIFF
R1
R2
In the re g ion whe re the d iffe re ntia l inp ut volta g e
approaches 1.8V, input resistance decreases exponen-
tially from 2.3MΩ to 2kΩ as the diode block begins con-
ducting. Inversely, the bias current increases with the
same curve.
Figure 1b. Reducing Offset Error Due to Bias Current
(Inverting)
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