MAX690T/S/R, MAX704T/S/R,
MAX802T/S/R, MAX804−MAX806T/S/R
3.0V/3.3V Microprocessor
Supervisory Circuits
Backup-Battery Switchover
Applications Information
In the event of a brownout or power failure, it may be
necessary to preserve the contents of RAM. With a back-
up battery installed at VBATT, the devices automatically
These µP supervisory circuits are not short-circuit
protected. Shorting V to ground—excluding power-up
OUT
transients such as charging a decoupling capacitor—
switch RAM to backup power when V
falls.
destroys the device. Decouple both V and VBATT
CC
CC
pins to ground by placing 0.1µF capacitors as close as
possible to the device.
This family of µP supervisors (designed for 3.3V and 3V
systems) doesn’t always connect VBATT to V when
OUT
VBATT is greater than V . VBATT connects to V
CC
OUT
and
Using a SuperCap as a Backup Power Source
(through a 140Ω switch) when V
is below V
CC
SW
SuperCaps are capacitors with extremely high capaci-
tance values (e.g., order of 0.47F) for their size. Figure 3
shows two ways to use a SuperCap as a backup power
source. The SuperCap may be connected through a
diode to the 3V input (Figure 3a) or, if a 5V supply is also
available, the SuperCap may be charged up to the 5V
supply (Figure 3b) allowing a longer backup period. Since
VBATT is greater than V , or when V
falls below
CC
CC
1.75V (typ) regardless of the VBATT voltage. This is done
to allow the backup battery (e.g., a 3.6V lithium cell) to
have a higher voltage than V
.
CC
Switchover at V
(2.40V) ensures that battery-backup
SW
mode is entered before V
gets too close to the 2.0V
OUT
minimum required to reliably retain data in CMOS RAM.
Switchover at higher V voltages would decrease
VBATT can exceed V
while V
is a bove the reset
CC
CC
CC
threshold, there are no special precautions when using
these µP supervisors with a SuperCap.
backup-battery life. When V
recovers, switchover is
CC
deferred until V
rises above the reset threshold (V
)
CC
RST
Operation without a Backup Power Source
to ensure a stable supply. V
is connected to V
OUT
CC
through a 3Ω PMOS power switch.
These µP supervisors were designed for battery-backed
applications. If a backup battery is not used, connect both
Manual Reset
VBATT and V
to V , or use a different µP supervisor
OUT
CC
A logic low on MR asserts reset. Reset remains asserted
while MR is low, and for t (200ms) after MR returns
such as the MAX706T/S/R or MAX708T/S/R.
WP
Replacing the Backup Battery
high. This input has an internal 70µA pullup current, so it
can be left open if it is not used. MR can be driven with
TTL or CMOS logic levels, or with open-drain/collector
outputs. Connect a normally open momentary switch from
MR to GND to create a manual-reset function; external
debounce circuitry is not required.
The backup power source can be removed while V
CC
remains valid, if VBATT is decoupled with a 0.1µF
capacitor to ground, without danger of triggering RESET/
RESET. As long as V
stays above V , battery-back-
up mode cannot be entered.
CC
SW
Adding Hysteresis to the Power-Fail
Comparator
The power-fail comparator has a typical input hysteresis
of 10mV. This is sufficient for most applications where a
power-supply line is being monitored through an external
voltage divider (see the Monitoring an Additional Power
Supply section).
Table 1. Input and Output Status in
Battery-Backup Mode
PIN NAME
STATUS
Connected to VBATT through an internal
140Ω switch
V
OUT
V
Disconnected from V
OUT
CC
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 4a. Select the
The power-fail comparator is disabled when
PFI
ratio of R1 and R2 such that PFI sees 1.237V (V
)
V
< V
PFT
CC
SW
when V falls to its trip point (V
hysteresis and will typically be more than 10 times the
value of R1 or R2. The hysteresis window extends both
). R3 adds the
IN
TRIP
Logic low when V
< V
or PFI < V
PFO
CC
SW PFT
WDI
The watchdog timer is disabled
Disabled
MR
above (V ) and below (V ) the original trip point (V ).
H
L
TRIP
Low logic
RESET
RESET
VBATT
Connecting an ordinary signal diode in series with R3, as
shown in Figure 4b, causes the lower trip point (V ) to
High impedance
L
Connected to V
OUT
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