欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • MC14LC5480DW
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • MC14LC5480DWR2图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • MC14LC5480DWR2 现货库存
  • 数量26800 
  • 厂家SST 
  • 封装SOP 
  • 批号22+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • MC14LC5480DW图
  • 深圳市科时进电子有限公司

     该会员已使用本站11年以上
  • MC14LC5480DW 现货库存
  • 数量770 
  • 厂家ON/安森美 
  • 封装SOP20 
  • 批号21+ 
  • 全新进口现货▊一手货源▊热卖支持实单▊bom配单专家
  • QQ:2355850215QQ:2355850215 复制
  • 0755-83997989 QQ:2355850215
  • MC14LC5480DW图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • MC14LC5480DW 现货库存
  • 数量3557 
  • 厂家MOTOROLA 
  • 封装SOP20 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • MC14LC5480DW图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • MC14LC5480DW 现货库存
  • 数量60030 
  • 厂家ON/安森美 
  • 封装SOP 
  • 批号2023+ 
  • 专营原装正品量大可定货
  • QQ:2885134554QQ:2885134554 复制
    QQ:2885134398QQ:2885134398 复制
  • 0755-22669259 QQ:2885134554QQ:2885134398
  • MC14LC5480DWR2图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • MC14LC5480DWR2 现货库存
  • 数量10 
  • 厂家SST 
  • 封装SOP 
  • 批号 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • MC14LC5480DW图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • MC14LC5480DW 现货库存
  • 数量28859 
  • 厂家FREESCALE 
  • 封装SOP20 
  • 批号2020+ 
  • 全新原装进口现货特价热卖,长期供货
  • QQ:1220223788QQ:1220223788 复制
    QQ:1327510916QQ:1327510916 复制
  • 86-0755-28767101 QQ:1220223788QQ:1327510916
  • MC14LC5480DWR2图
  • 深圳市芯柏然科技有限公司

     该会员已使用本站7年以上
  • MC14LC5480DWR2
  • 数量26800 
  • 厂家SST 
  • 封装SOP 
  • 批号22+ 
  • 授权代理直销,原厂原装现货,假一罚十,特价销售
  • QQ:287673858QQ:287673858 复制
  • 0755-82533534 QQ:287673858
  • MC14LC5480DWR2图
  • 深圳市凯睿晟科技有限公司

     该会员已使用本站10年以上
  • MC14LC5480DWR2
  • 数量2000 
  • 厂家FREESCALE/飞思卡尔 
  • 封装SOIC20 
  • 批号24+ 
  • 百域芯优势 实单必成 可开13点增值税
  • QQ:2885648621QQ:2885648621 复制
  • 0755-23616725 QQ:2885648621
  • MC14LC5480DW图
  • 深圳市捷兴胜微电子科技有限公司

     该会员已使用本站13年以上
  • MC14LC5480DW
  • 数量1200 
  • 厂家MOT 
  • 封装SOP 
  • 批号 
  • 原装 现货 专业MOT供应商 优势库存热卖中!
  • QQ:838417624QQ:838417624 复制
    QQ:929605236QQ:929605236 复制
  • 0755-23997656(现货库存配套一站采购及BOM优化) QQ:838417624QQ:929605236
  • MC14LC5480DWR2图
  • 上海金庆电子技术有限公司

     该会员已使用本站15年以上
  • MC14LC5480DWR2
  • 数量1316 
  • 厂家MOT 
  • 封装SOP-20 
  • 批号新 
  • 全新原装 货期两周
  • QQ:1484215649QQ:1484215649 复制
    QQ:729272152QQ:729272152 复制
  • 021-51872561 QQ:1484215649QQ:729272152
  • MC14LC5480DW2图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • MC14LC5480DW2
  • 数量450 
  • 厂家MOTOROLA 
  • 封装SMD 
  • 批号16+ 
  • 特价,原装正品,绝对公司现货库存,原装特价!
  • QQ:2880824479QQ:2880824479 复制
  • 010-62104891 QQ:2880824479
  • MC14LC5480DW图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • MC14LC5480DW
  • 数量65800 
  • 厂家ON/安森美 
  • 封装SOP 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • MC14LC5480DWR2图
  • 集好芯城

     该会员已使用本站13年以上
  • MC14LC5480DWR2
  • 数量16928 
  • 厂家FREESCALE 
  • 封装SOP 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • MC14LC5480DW图
  • 齐创科技(上海北京青岛)有限公司

     该会员已使用本站14年以上
  • MC14LC5480DW
  • 数量26000 
  • 厂家MOT代理 
  • 封装SOP-28 
  • 批号24+热销 
  • 【优势库存】专业代理全新现货特价热卖
  • QQ:2394092314QQ:2394092314 复制
    QQ:792179102QQ:792179102 复制
  • 021-62153656 QQ:2394092314QQ:792179102
  • MC14LC5480DW图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • MC14LC5480DW
  • 数量1001 
  • 厂家NXP 
  • 封装SOP-20 
  • 批号24+ 
  • ★体验愉快问购元件!!就找我吧!《停产物料》
  • QQ:1415691092QQ:1415691092 复制
  • 133-5299-5145(微信同号) QQ:1415691092
  • MC14LC5480DW图
  • 北京力通科信电子有限公司

     该会员已使用本站10年以上
  • MC14LC5480DW
  • 数量
  • 厂家mot 
  • 封装vpe: 36/tube/so20 
  • 批号dc98 
  • 7-10天原装特价*热卖
  • QQ:2355365902QQ:2355365902 复制
    QQ:2355365899QQ:2355365899 复制
  • 010-82625766 QQ:2355365902QQ:2355365899
  • MC14LC5480DW图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • MC14LC5480DW
  • 数量10000 
  • 厂家MOT 
  • 封装SOP-20 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • MC14LC5480DW图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • MC14LC5480DW
  • 数量1680 
  • 厂家FREESCALE 
  • 封装SOP20 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • MC14LC5480DWR图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • MC14LC5480DWR
  • 数量6000 
  • 厂家MOT 
  • 封装SMD 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • MC14LC5480DW图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • MC14LC5480DW
  • 数量21688 
  • 厂家ON 
  • 封装SOP 
  • 批号2020+ 
  • 全新原装进口现货特价热卖,长期供货
  • QQ:1327510916QQ:1327510916 复制
    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • MC14LC5480DWR图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • MC14LC5480DWR
  • 数量5000 
  • 厂家MOT 
  • 封装SMD 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104891 QQ:857273081QQ:1594462451
  • MC14LC5480DW图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • MC14LC5480DW
  • 数量23000 
  • 厂家MOT 
  • 封装SMD 
  • 批号24+ 
  • 原装现货假一赔十,可含长期供货!
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • MC14LC5480DW图
  • 深圳市浩兴林电子有限公司

     该会员已使用本站16年以上
  • MC14LC5480DW
  • 数量5000 
  • 厂家MOT 
  • 封装SOP20 
  • 批号2017+ 
  • 优势库存现货,部分无铅
  • QQ:382716594QQ:382716594 复制
    QQ:351622092QQ:351622092 复制
  • 0755-82532799 QQ:382716594QQ:351622092
  • MC14LC5480DW图
  • 深圳市诚达吉电子有限公司

     该会员已使用本站2年以上
  • MC14LC5480DW
  • 数量6504 
  • 厂家FREESCALE 
  • 封装SOP20 
  • 批号2024+ 
  • 原装正品 一手现货 假一赔百
  • QQ:2881951980QQ:2881951980 复制
  • 15873513267 QQ:2881951980
  • MC14LC5480DW图
  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • MC14LC5480DW
  • 数量11104 
  • 厂家FREESCALE 
  • 封装SOP20 
  • 批号24+ 
  • 原装现货
  • QQ:354696650QQ:354696650 复制
    QQ:2850471056QQ:2850471056 复制
  • 0755-89587732 QQ:354696650QQ:2850471056
  • MC14LC5480DW图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • MC14LC5480DW
  • 数量6500000 
  • 厂家恩智浦 
  • 封装原厂原装 
  • 批号22+ 
  • 万三科技 秉承原装 实单可议
  • QQ:3008961396QQ:3008961396 复制
  • 0755-21008751 QQ:3008961396
  • MC14LC5480DW图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • MC14LC5480DW
  • 数量3500 
  • 厂家MOTORO 
  • 封装SOP 
  • 批号21+ 
  • 原装正品,公司现货
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • MC14LC5480DW图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • MC14LC5480DW
  • 数量10 
  • 厂家FREESCALE 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • MC14LC5480DW图
  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • MC14LC5480DW
  • 数量16680 
  • 厂家MOT 
  • 封装SOP 
  • 批号16+ 
  • 假一赔十★全新原装现货★★特价供应★工厂客户可放款
  • QQ:799387964QQ:799387964 复制
    QQ:2777237833QQ:2777237833 复制
  • 0755-82566711 QQ:799387964QQ:2777237833
  • MC14LC5480DWR2图
  • 北京顺科电子科技有限公司

     该会员已使用本站8年以上
  • MC14LC5480DWR2
  • 数量5500 
  • 厂家FREESCALE 
  • 封装SOP 
  • 批号21+ 
  • 进口品牌//国产品牌代理商18911556207
  • QQ:729566152QQ:729566152 复制
    QQ:1138731127QQ:1138731127 复制
  • 18911556207 QQ:729566152QQ:1138731127
  • MC14LC5480DW图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • MC14LC5480DW
  • 数量12800 
  • 厂家MC 
  • 封装N A 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • MC14LC5480DW图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • MC14LC5480DW
  • 数量69393 
  • 厂家MOT 
  • 封装SOP 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • MC14LC5480DW图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • MC14LC5480DW
  • 数量10150 
  • 厂家FREESCALE 
  • 封装SOP20 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507165QQ:2355507165 复制
    QQ:2355507162QQ:2355507162 复制
  • 86-0755-83210909 QQ:2355507165QQ:2355507162
  • MC14LC5480DW图
  • 北京耐芯威科技有限公司

     该会员已使用本站13年以上
  • MC14LC5480DW
  • 数量5000 
  • 厂家MOTORO 
  • 封装SOP 
  • 批号21+ 
  • 原装正品,公司现货
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 86-010-010-62104931 QQ:2880824479QQ:1344056792
  • MC14LC5480DW图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • MC14LC5480DW
  • 数量3000 
  • 厂家MOTOROLA 
  • 封装SOP20 
  • 批号25+ 
  • 全新原装公司现货销售
  • QQ:1245773710QQ:1245773710 复制
    QQ:867789136QQ:867789136 复制
  • 0755-82772189 QQ:1245773710QQ:867789136
  • MC14LC5480DW图
  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • MC14LC5480DW
  • 数量26976 
  • 厂家MOT 
  • 封装SOP20 
  • 批号2018+ 
  • ★★代理原装现货,特价热卖!★★
  • QQ:2752732883QQ:2752732883 复制
    QQ:240616963QQ:240616963 复制
  • 0755-25165869 QQ:2752732883QQ:240616963
  • MC14LC5480DW图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • MC14LC5480DW
  • 数量3265 
  • 厂家NXP 
  • 封装20-SOIC(0.295,7.50mm 宽) 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • MC14LC5480DW图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • MC14LC5480DW
  • 数量3500 
  • 厂家MOTOROLA 
  • 封装
  • 批号25+ 
  • 全新原装现货特价销售!
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82723761 QQ:867789136QQ:1245773710
  • MC14LC5480DW图
  • 首天国际(深圳)科技有限公司

     该会员已使用本站16年以上
  • MC14LC5480DW
  • 数量10000 
  • 厂家MOT 
  • 封装SMD-20 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 0755-82807802 QQ:528164397QQ:1318502189
  • MC14LC5480DW图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • MC14LC5480DW
  • 数量85600 
  • 厂家MOT 
  • 封装SOP 
  • 批号NEW 
  • ★原装★现货可售样品★长期供货★
  • QQ:1134344845QQ:1134344845 复制
    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • MC14LC5480DW图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • MC14LC5480DW
  • 数量5500 
  • 厂家MOTOROLA 
  • 封装SOP20 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
  • QQ:1437347957QQ:1437347957 复制
    QQ:1205045963QQ:1205045963 复制
  • 0755-82343089 QQ:1437347957QQ:1205045963

产品型号MC14LC5480DW的概述

芯片MC14LC5480DW的概述 MC14LC5480DW是一款多功能的高性能集成电路,广泛应用于通信、工业控制、智能设备及其他电子产品中。它可以有效地处理数字信号,提供可靠的性能和灵活的配置,以满足现代电子产品日益增长的需求。 MC14LC5480DW采用了现代CMOS工艺,具备低功耗和高集成度的特点,使其适用于便携式和电池供电的应用场景。此芯片的设计目标不仅在于实现基本的功能,还注重提高抗干扰能力和可靠性,确保在不同工作环境下都能保持稳定的性能。 芯片MC14LC5480DW的详细参数 MC14LC5480DW的主要参数包括: 1. 工作电压:3.0V - 5.5V 2. 工作频率:可达20MHz 3. 温度范围:-40°C 至 +85°C 4. 引脚数量:28引脚 5. 信号类型:支持TTL/CMOS级别信号 6. 功耗:在工作状态下功耗较低,一般在数十毫瓦。 7. 接口类型:...

产品型号MC14LC5480DW的Datasheet PDF文件预览

Order this document  
by MC14LC5480/D  
SEMICONDUCTOR TECHNICAL DATA  
Advance Information  
P SUFFIX  
PLASTIC DIP  
CASE 738  
The MC14LC5480 is a general purpose per channel PCM Codec–Filter with  
pin selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP,  
SOG, and SSOP packages. This device performs the voice digitization and  
reconstruction as well as the band limiting and smoothing required for PCM  
systems. This device is designed to operate in both synchronous and  
asynchronous applications and contains an on–chip precision reference  
voltage.  
20  
20  
1
DW SUFFIX  
SOG PACKAGE  
CASE 751D  
1
This device has an input operational amplifier whose output is the input to the  
encoder section. The encoder section immediately low–pass filters the analog  
signal with an active R–C filter to eliminate very high frequency noise from being  
modulated down to the passband by the switched capacitor filter. From the  
active R–C filter, the analog signal is converted to a differential signal. From this  
point, all analog signal processing is done differentially. This allows processing  
of an analog signal that is twice the amplitude allowed by a single–ended  
design, which reduces the significance of noise to both the inverted and  
non–inverted signal paths. Another advantage of this differential design is that  
noise injected via the power supplies is a common–mode signal that is  
cancelled when the inverted and non–inverted signals are recombined. This  
dramatically improves the power supply rejection ratio.  
SD SUFFIX  
SSOP  
CASE 940C  
20  
1
ORDERING INFORMATION  
MC14LC5480P  
Plastic DIP  
MC14LC5480DW SOG Package  
MC14LC5480SD SSOP  
After the differential converter, a differential switched capacitor filter band–  
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized  
by the differential compressing A/D converter.  
PIN ASSIGNMENT  
The decoder accepts PCM data and expands it using a differential D/A  
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X  
compensated by a differential switched capacitor filter. The signal is then filtered  
by an active R–C filter to eliminate the out–of–band energy of the switched  
capacitor filter.  
RO+  
RO–  
1
2
20  
19  
V
AG  
TI+  
PI  
3
4
18  
17  
TI–  
TG  
PO–  
The MC14LC5480 PCM Codec–Filter accepts a variety of clock formats,  
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing  
environments. This device also maintains compatibility with Motorola’s family of  
Telecommunication products, including the MC14LC5472 U–Interface Trans-  
ceiver, MC145474/75 S/T–Interface Transceiver, MC145532 ADPCM Trans-  
coder, MC145422/26 UDLT–1, MC145421/25 UDLT–2, and MC3419/MC33120  
SLIC.  
The MC14LC5480 PCM Codec–Filter utilizes CMOS due to its reliable  
low–power performance and proven capability for complex analog/digital VLSI  
functions.  
PO+  
5
6
16  
15  
Mu/A  
V
V
DD  
SS  
FSR  
DR  
7
14  
13  
12  
11  
FST  
8
DT  
BCLKR  
PDI  
9
BCLKT  
MCLK  
10  
Pin for Pin Replacement for the MC145480  
Single 5 V Power Supply  
Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW  
Fully–Differential Analog Circuit Design for Lowest Noise  
Transmit Band–Pass and Receive Low–Pass Filters On–Chip  
Active R–C Pre–Filtering and Post–Filtering  
Mu–Law and A–Law Companding by Pin Selection  
On–Chip Precision Reference Voltage (1.575 V)  
Push–Pull 300 Power Drivers with External Gain Adjust  
MC145536EVK is the Evaluation Kit that Also Includes the MC145532  
ADPCM Transcoder  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 0.1  
5/96  
Motorola, Inc. 1996  
RECEIVE  
SHIFT  
REGISTER  
DR  
RO +  
RO –  
DAC  
FREQ  
PI  
FSR  
+
PO –  
BCLKR  
Mu/A  
PDI  
SHARED  
DAC  
SEQUENCE  
AND  
– 1  
PO +  
CONTROL  
MCLK  
BCLKT  
V
DD  
1.575 V  
REF  
V
SS  
2.4 V  
REFERENCE  
1
V
AG  
FST  
TG  
TI –  
TI +  
+
ADC  
FREQ  
TRANSMIT  
SHIFT  
DT  
REGISTER  
Figure 1. MC14LC5480 PCM Codec–Filter Block Diagram  
which increment. When the chord bits increment, the step  
bits double their voltage weighting. This results in an effec-  
tive resolution of six bits (sign + chord + four step bits) across  
a 42 dB dynamic range (seven chords above 0, by 6 dB per  
chord).  
DEVICE DESCRIPTION  
A PCM Codec–Filter is used for digitizing and reconstruct-  
ing the human voice. These devices are used primarily for  
the telephone network to facilitate voice switching and trans-  
mission. Once the voice is digitized, it may be switched by  
digital switching methods or transmitted long distance (T1,  
microwave, satellites, etc.) without degradation. The name  
codec is an acronym from ‘‘COder’’ for the analog–to–digital  
converter (ADC) used to digitize voice, and ‘‘DECoder’’ for  
the digital–to–analog converter (DAC) used for reconstruct-  
ing voice. A codec is a single device that does both the ADC  
and DAC conversions.  
To digitize intelligible voice requires a signal–to–distortion  
ratio of about 30 dB over a dynamic range of about 40 dB.  
This may be accomplished with a linear 13–bit ADC and  
DAC, but will far exceed the required signal–to–distortion  
ratio at larger amplitudes than 40 dB below the peak ampli-  
tude. This excess performance is at the expense of data per  
sample. Two methods of data reduction are implemented by  
compressing the 13–bit linear scheme to companded  
pseudo–logarithmic 8–bit schemes. The two companding  
schemes are: Mu–255 Law, primarily in North America and  
Japan; and A–Law, primarily used in Europe. These com-  
panding schemes are accepted world wide. These compand-  
ing schemes follow a segmented or ‘‘piecewise–linear’’ curve  
formatted as sign bit, three chord bits, and four step bits. For  
a given chord, all sixteen of the steps have the same voltage  
weighting. As the voltage of the analog input increases, the  
four step bits increment and carry to the three chord bits  
In a sampling environment, Nyquist theory says that to  
properly sample a continuous signal, it must be sampled at a  
frequency higher than twice the signal’s highest frequency  
component. Voice contains spectral energy above 3 kHz, but  
its absence is not detrimental to intelligibility. To reduce the  
digital data rate, which is proportional to the sampling rate, a  
sample rate of 8 kHz was adopted, consistent with a band-  
width of 3 kHz. This sampling requires a low–pass filter to  
limit the high frequency energy above 3 kHz from distorting  
the in–band signal. The telephone line is also subject to  
50/60 Hz power line coupling, which must be attenuated  
from the signal by a high–pass filter before the analog–to–  
digital converter.  
The digital–to–analog conversion process reconstructs a  
staircase version of the desired in–band signal, which has  
spectral images of the in–band signal modulated about the  
sample frequency and its harmonics. These spectral images  
are called aliasing components, which need to be attenuated  
to obtain the desired signal. The low–pass filter used to at-  
tenuate these aliasing components is typically called a re-  
construction or smoothing filter.  
The MC14LC5480 PCM Codec–Filter has the codec, both  
presampling and reconstruction filters, a precision voltage  
reference on–chip, and requires no external components.  
MC14LC5480  
2
MOTOROLA  
plifier’s output (TG) into a high–impedance state, thus allow-  
ing the TG pin to serve as a high–impedance input to the  
transmit filter.  
PIN DESCRIPTIONS  
POWER SUPPLY  
V
DD  
TI–  
Positive Power Supply (Pin 6)  
Transmit Analog Input (Inverting) (Pin 18)  
This is the most positive power supply and is typically con-  
This is the inverting input of the transmit gain setting op-  
erational amplifier. Gain setting resistors are usually con-  
nected from this pin to TG and from this pin to the analog  
signal source. The common mode range of the TI+ and TI–  
nected to + 5 V. This pin should be decoupled to V  
0.1 µF ceramic capacitor.  
with a  
SS  
V
SS  
Negative Power Supply (Pin 15)  
pins is from 1.2 V to V  
DD  
Connecting the TI+ pin to V  
– 2 V. This is an FET gate input.  
will place this amplifier’s out-  
DD  
This is the most negative power supply and is typically  
connected to 0 V.  
put (TG) into a high–impedance state, thus allowing the TG  
pin to serve as a high–impedance input to the transmit filter.  
V
AG  
TG  
Analog Ground Output (Pin 20)  
Transmit Gain (Pin 17)  
This output pin provides a mid–supply analog ground reg-  
This is the output of the transmit gain setting operational  
amplifier and the input to the transmit band–pass filter. This  
op amp is capable of driving a 2 kload. Connecting the TI+  
ulated to 2.4 V. This pin should be decoupled to V  
0.01 µF to 0.1 µF ceramic capacitor. All analog signal pro-  
cessing within this device is referenced to this pin. If the au-  
with a  
SS  
pin to V  
will place this amplifier’s output (TG) into a high–  
dio signals to be processed are referenced to V , then  
special precautions must be utilized to avoid noise between  
DD  
SS  
impedance state, thus allowing the TG pin to serve as a  
high–impedance input to the transmit filter. All signals at this  
pin are referenced to the V  
V
and the V  
pin. Refer to the applications information in  
pin becomes  
SS  
AG  
pin. This pin is high impedance  
this document for more information. The V  
AG  
high impedance when this device is in the powered down  
mode.  
AG  
when the device is in the powered down mode.  
RO+  
CONTROL  
Receive Analog Output (Non–Inverting) (Pin 1)  
Mu/A  
This is the non–inverting output of the receive smoothing  
filter from the digital–to–analog converter. This output is  
capable of driving a 2 kload to 1.575 V peak referenced to  
Mu/A Law Select (Pin 16)  
This pin controls the compression for the encoder and the  
expansion for the decoder. Mu–Law companding is selected  
when this pin is connected to V  
the V  
pin. This pin is high impedance when the device is in  
AG  
the powered down mode.  
and A–Law companding is  
DD  
selected when this pin is connected to V  
.
SS  
RO–  
Receive Analog Output (Inverting) (Pin 2)  
PDI  
Power–Down Input (Pin 10)  
This is the inverting output of the receive smoothing filter  
from the digital–to–analog converter. This output is capable  
This pin puts the device into a low power dissipation mode  
when a logic 0 is applied. When this device is powered down,  
all of the clocks are gated off and all bias currents are turned  
of driving a 2 kload to 1.575 V peak referenced to the V  
AG  
pin. This pin is high impedance when the device is in the  
powered down mode.  
off, which causes RO+, RO–, PO–, PO+, TG, V , and DT to  
AG  
become high impedance. The device will operate normally  
when a logic 1 is applied to this pin. The device goes through  
a power–up sequence when this pin is taken to a logic 1  
state, which prevents the DT PCM output from going low im-  
pedance for at least two FST cycles. The filters must settle  
out before the DT PCM output or the RO+ or RO– receive  
analog outputs will represent a valid analog signal.  
PI  
Power Amplifier Input (Pin 3)  
This is the inverting input to the PO– amplifier. The non–  
inverting input to the PO– amplifier is internally tied to the  
V
pin. The PI and POpins are used with external resis-  
AG  
tors in an inverting op amp gain circuit to set the gain of the  
PO+ and PO– push–pull power amplifier outputs. Connect-  
ANALOG INTERFACE  
ing PI to V  
will power down the power driver amplifiers and  
DD  
TI+  
the PO+ and PO– outputs will be high impedance.  
Transmit Analog Input (Non–Inverting) (Pin 19)  
PO–  
This is the non–inverting input of the transmit input gain  
setting operational amplifier. This pin accommodates a differ-  
ential to single–ended circuit for the input gain setting op  
Power Amplifier Output (Inverting) (Pin 4)  
This is the inverting power amplifier output, which is used  
to provide a feedback signal to the PI pin to set the gain of  
the push–pull power amplifier outputs. This pin is capable of  
driving a 300 load to PO+. The PO+ and PO– outputs are  
differential (push–pull) and capable of driving a 300 load to  
3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage  
amp. This allows input signals that are referenced to the V  
SS  
pin with minimum noise.  
pin to be level shifted to the V  
AG  
This pin may be connected to the V  
amplifier configuration if the input signal is already refer-  
enced to the V pin. The common mode range of the TI+  
pin for an inverting  
AG  
AG  
and TI– pins is from 1.2 V, to V  
minus 2 V. This is an FET  
and signal reference of this output is the V  
pin cannot source or sink as much current as this pin, and  
pin. The V  
AG AG  
DD  
gate input. Connecting the TI+ pin to V  
will place this am-  
DD  
MOTOROLA  
MC14LC5480  
3
therefore low impedance loads must be between PO+ and  
PO–. Connecting PI to V will power down the power driver  
FSR  
Frame Sync, Receive (Pin 7)  
DD  
amplifiers and the PO+ and PO– outputs will be high imped-  
ance. This pin is also high impedance when the device is  
powered down by the PDI pin.  
When used in the Long Frame Sync or Short Frame Sync  
mode, this pin accepts an 8 kHz clock, which synchronizes  
the input of the serial PCM data at the DR pin. FSR can be  
asynchronous to FST in the Long Frame Sync or Short  
Frame Sync modes. When an ISDN mode (IDL or GCI) has  
been selected with BCLKR, this pin selects either B1 (logic 0)  
or B2 (logic 1) as the active data channel.  
PO+  
Power Amplifier Output (Non–Inverting) (Pin 5)  
This is the non–inverting power amplifier output, which is  
an inverted version of the signal at PO–. This pin is capable  
BCLKR  
Bit Clock, Receive (Pin 9)  
of driving a 300 load to PO–. Connecting PI to V  
will  
DD  
power down the power driver amplifiers and the PO+ and  
PO– outputs will be high impedance. This pin is also high im-  
pedance when the device is powered down by the PDI pin.  
See PI and PO– for more information.  
When used in the Long Frame Sync or Short Frame Sync  
mode, this pin accepts any bit clock frequency from 64 to  
4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,  
and DR become IDL Interface compatible. When this pin is  
held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-  
face compatible.  
DIGITAL INTERFACE  
DR  
MCLK  
Master Clock (Pin 11)  
Data, Receive (Pin 8)  
This pin is the PCM data input, and when in a Long Frame  
Sync or Short Frame Sync mode is controlled by FSR and  
BCLKR. When in the IDL or GCI mode, this data transfer is  
controlled by FST and BCLKT. FSR and BCLKR select the  
B channel and ISDN mode, respectively.  
This is the master clock input pin. The clock signal applied  
to this pin is used to generate the internal 256 kHz clock and  
sequencing signals for the switched–capacitor filters, ADC,  
and DAC. The internal prescaler logic compares the clock on  
this pin to the clock at FST (8 kHz) and will automatically  
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For  
MCLK frequencies of 256 and 512 kHz, MCLK must be syn-  
chronous and approximately rising edge aligned to FST. For  
optimum performance at frequencies of 1.536 MHz and  
higher, MCLK should be synchronous and approximately ris-  
ing edge aligned to the rising edge of FST. In many ap-  
plications, MCLK may be tied to the BCLKT pin.  
FUNCTIONAL DESCRIPTION  
ANALOG INTERFACE AND SIGNAL PATH  
The transmit portion of this device includes a low–noise,  
three–terminal op amp capable of driving a 2 kload. This  
op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its  
output is TG (Pin 17). This op amp is intended to be confi-  
gured in an inverting gain circuit. The analog signal may be  
applied directly to the TG pin if this transmit op amp is inde-  
pendently powered down by connecting the TI+ and TI–  
FST  
Frame Sync, Transmit (Pin 14)  
inputs to the V  
power supply. The TG pin becomes high  
DD  
impedance when the transmit op amp is powered down. The  
TG pin is internally connected to a 3–pole anti–aliasing pre–  
filter. This pre–filter incorporates a 2–pole Butterworth active  
low–pass filter, followed by a single passive pole. This pre–  
filter is followed by a single–ended to differential converter  
that is clocked at 512 kHz. All subsequent analog processing  
utilizes fully–differential circuitry. The next section is a fully–  
differential, 5–pole switched–capacitor low–pass filter with a  
3.4 kHz frequency cutoff. After this filter is a 3–pole  
switched–capacitor high–pass filter having a cutoff fre-  
quency of about 200 Hz. This high–pass stage has a trans-  
mission zero at dc that eliminates any dc coming from the  
analog input or from accumulated op amp offsets in the pre-  
ceding filter stages. The last stage of the high–pass filter is  
an autozeroed sample and hold amplifier.  
One bandgap voltage reference generator and digital–to–  
analog converter (DAC) are shared by the transmit and re-  
ceive sections. The autozeroed, switched–capacitor  
bandgap reference generates precise positive and negative  
reference voltages that are virtually independent of tempera-  
ture and power supply voltage. A binary–weighted capacitor  
array (CDAC) forms the chords of the companding structure,  
while a resistor string (RDAC) implements the linear steps  
within each chord. The encode process uses the DAC, the  
voltage reference, and a frame–by–frame autozeroed  
comparator to implement a successive–approximation con-  
This pin accepts an 8 kHz clock that synchronizes the out-  
put of the serial PCM data at the DT pin. This input is com-  
patible with various standards including IDL, Long Frame  
Sync, Short Frame Sync, and GCI formats. If both FST and  
FSR are held low for several 8 kHz frames, the device will  
power down.  
BCLKT  
Bit Clock, Transmit (Pin 12)  
This pin controls the transfer rate of transmit PCM data. In  
the IDL and GCI modes it also controls the transfer rate of  
the receive PCM data. This pin can accept any bit clock fre-  
quency from 64 to 4096 kHz for Long Frame Sync and Short  
Frame Sync timing. This pin can accept clock frequencies  
from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz  
to 6.176 MHz for GCI timing mode.  
DT  
Data, Transmit (Pin 13)  
This pin is controlled by FST and BCLKT and is high im-  
pedance except when outputting PCM data. When operating  
in the IDL or GCI mode, data is output in either the B1 or B2  
channel as selected by FSR. This pin is high impedance  
when the device is in the powered down mode.  
MC14LC5480  
4
MOTOROLA  
version algorithm. All of the analog circuitry involved in the  
data conversion (the voltage reference, RDAC, CDAC, and  
comparator) are implemented with a differential architecture.  
The receive section includes the DAC described above, a  
sample and hold amplifier, a 5–pole, 3400 Hz switched ca-  
pacitor low–pass filter with sinX/X correction, and a 2–pole  
active smoothing filter to reduce the spectral components of  
the switched capacitor filter. The output of the smoothing fil-  
ter is buffered by an amplifier, which is output at the RO+ and  
RO– pins. These outputs are capable of driving a 4 kload  
The DT output will remain in a high–impedance state for at  
least two FST pulses after power–up.  
MASTER CLOCK  
Since this codec–filter design has a single DAC architec-  
ture, the MCLK pin is used as the master clock for all analog  
signal processing including analog–to–digital conversion,  
digital–to–analog conversion, and for transmit and receive fil-  
tering functions of this device. The clock frequency applied to  
the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,  
1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-  
vice has a prescaler that automatically determines the proper  
divide ratio to use for the MCLK input, which achieves the re-  
quired 256 kHz internal sequencing clock. The clocking re-  
quirements of the MCLK input are independent of the PCM  
data transfer mode (i.e., Long Frame Sync, Short Frame  
Sync, IDL mode, or GCI mode).  
differentially or a 2 kload to the V  
pin. The MC14LC5480  
AG  
also has a pair of power amplifiers that are connected in a  
push–pull configuration. The PI pin is the inverting input to  
the PO– power amplifier. The non–inverting input is internally  
tied to the V  
pin. This allows this amplifier to be used in an  
AG  
inverting gain circuit with two external resistors. The PO+  
amplifier has a gain of minus one, and is internally con-  
nected to the PO– output. This complete power amplifier cir-  
cuit is a differential (push–pull) amplifier with adjustable gain  
that is capable of driving a 300 load to +12 dBm. The  
power amplifier may be powered down independently of the  
DIGITAL I/O  
The MC14LC5480 is pin selectable for Mu–Law or A–Law.  
Table 1 shows the 8–bit data word format for positive and  
negative zero and full scale for both companding schemes  
(see Tables 3 and 4 at the end of this document for a com-  
plete PCM word conversion table). Table 2 shows the series  
of eight PCM words for both Mu–Law and A–Law that corre-  
spond to a digital milliwatt. The digital mW is the 1 kHz cal-  
ibration signal reconstructed by the DAC that defines the  
absolute gain or 0 dBm0 Transmission Level Point (TLP) of  
the DAC. The 0 dBm0 level for Mu–Law is 3.17 dB below the  
maximum level for an unclipped tone signal. The 0 dBm0  
level for A–Law is 3.14 dB below the maximum level for an  
unclipped tone signal. The timing for the PCM data transfer is  
independent of the companding scheme selected. Refer to  
Figure 2 for a summary and comparison of the four PCM  
data interface modes of this device.  
rest of the chip by connecting the PI pin to V  
.
DD  
POWER–DOWN  
There are two methods of putting this device into a low  
power consumption mode, which makes the device nonfunc-  
tional and consumes virtually no power. PDI is the power–  
down input pin which, when taken low, powers down the  
device. Another way to power the device down is to hold both  
the FST and FSR pins low. When the chip is powered down,  
the V , TG, RO+, RO–, PO+, PO–, and DT outputs are high  
AG  
impedance. To return the chip to the power–up state, PDI  
must be high and the FST frame sync pulse must be present.  
Table 1. PCM Codes for Zero and Full Scale  
Mu–Law  
A–Law  
Chord Bits  
0 1 0  
Level  
+ Full Scale  
+ Zero  
Sign Bit  
Chord Bits  
0 0 0  
Step Bits  
0 0 0 0  
1 1 1 1  
1 1 1 1  
0 0 0 0  
Sign Bit  
Step Bits  
1 0 1 0  
0 1 0 1  
0 1 0 1  
1 0 1 0  
1
1
0
0
1
1
0
0
1 1 1  
1 0 1  
– Zero  
1 1 1  
1 0 1  
– Full Scale  
0 0 0  
0 1 0  
Table 2. PCM Codes for Digital mW  
Mu–Law  
A–Law  
Chord Bits  
0 1 1  
Phase  
π/8  
Sign Bit  
Chord Bits  
0 0 1  
Step Bits  
1 1 1 0  
1 0 1 1  
1 0 1 1  
1 1 1 0  
1 1 1 0  
1 0 1 1  
1 0 1 1  
1 1 1 0  
Sign Bit  
Step Bits  
0 1 0 0  
0 0 0 1  
0 0 0 1  
0 1 0 0  
0 1 0 0  
0 0 0 1  
0 0 0 1  
0 1 0 0  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
3π/8  
0 0 0  
0 1 0  
5π/8  
0 0 0  
0 1 0  
7π/8  
0 0 1  
0 1 1  
9π/8  
0 0 1  
0 1 1  
11π/8  
13π/8  
15π/8  
0 0 0  
0 1 0  
0 0 0  
0 1 0  
0 0 1  
0 1 1  
MOTOROLA  
MC14LC5480  
5
FST (FSR)  
BCLKT (BCLKR)  
DT  
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
DR  
DON’T CARE  
8
DON’T CARE  
Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking)  
FST (FSR)  
BCLKT (BCLKR)  
DT  
DR  
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
DON’T CARE  
8
DON’T CARE  
Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking)  
IDL SYNC (FST)  
IDL CLOCK (BCLKT)  
IDL TX (DT)  
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
DON’T  
CARE  
DON’T  
CARE  
IDL RX (DR)  
DON’T CARE  
8
8
B1–CHANNEL (FSR = 0)  
B2–CHANNEL (FSR = 1)  
Figure 2c. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common Clocking)  
FSC (FST)  
DCL (BCLKT)  
D
(DT)  
(DR)  
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
out  
DON’T  
CARE  
D
8
DON’T CARE  
in  
B1–CHANNEL (FSR = 0)  
B2–CHANNEL (FSR = 1)  
Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking)  
Figure 2. Digital Timing Modes for the PCM Data Interface  
MC14LC5480  
6
MOTOROLA  
Long Frame Sync  
used for two specific synchronizing functions. The first is to  
synchronize the PCM data word transfer, and the second is  
to control the internal analog–to–digital and digital–to–analog  
conversions. The term ‘‘Sync’’ refers to the function of syn-  
chronizing the PCM data word onto or off of the multiplexed  
serial PCM data bus, which is also known as a PCM high-  
way. The term ‘‘Short’’ comes from the duration of the frame  
sync measured in PCM data clock cycles. Short Frame Sync  
timing occurs when the frame sync is used as a ‘‘pre–syn-  
chronization’’ pulse that is used to tell the internal logic to  
clock out the PCM data word under complete control of the  
data clock. The Short Frame Sync is held high for one falling  
data clock edge. The device outputs the PCM data word be-  
ginning with the following rising edge of the data clock. This  
results in the PCM output going low impedance with the ris-  
ing edge of the transmit data clock, and remaining low im-  
pedance until the middle of the LSB (seven and a half PCM  
data clock cycles).  
Long Frame Sync is the industry name for one type of  
clocking format that controls the transfer of the PCM data  
words. (Refer to Figure 2a.) The ‘‘Frame Sync’’ or ‘‘Enable’’ is  
used for two specific synchronizing functions. The first is to  
synchronize the PCM data word transfer, and the second is  
to control the internal analog–to–digital and digital–to–analog  
conversions. The term ‘‘Sync’’ refers to the function of syn-  
chronizing the PCM data word onto or off of the multiplexed  
serial PCM data bus, which is also known as a PCM high-  
way. The term ‘‘Long’’ comes from the duration of the frame  
sync measured in PCM data clock cycles. Long Frame Sync  
timing occurs when the frame sync is used directly as the  
PCM data output driver enable. This results in the PCM out-  
put going low impedance with the rising edge of the transmit  
frame sync, and remaining low impedance for the duration of  
the transmit frame sync.  
The implementation of Long Frame Sync has maintained  
compatibility and been optimized for external clocking sim-  
plicity. This optimization includes the PCM data output going  
low impedance with the logical AND of the transmit frame  
sync (FST) with the transmit data bit clock (BCLKT). The op-  
timization also includes the PCM data output (DT) remaining  
low impedance until the middle of the LSB (seven and a half  
PCM data clock cycles) or until the FST pin is taken low,  
whichever occurs last. This requires the frame sync to be  
approximately rising edge aligned with the initiation of the  
PCM data word transfer, but the frame sync does not have a  
precise timing requirement for the end of the PCM data word  
transfer. The device recognizes Long Frame Sync clocking  
when the frame sync is held high for two consecutive falling  
edges of the transmit data clock. The transmit logic decides  
on each frame sync whether it should interpret the next  
frame sync pulse as a Long or a Short Frame Sync. This de-  
cision is used for receive circuitry also. The device is de-  
signed to prevent PCM bus contention by not allowing the  
PCM data output to go low impedance for at least two frame  
sync cycles after power is applied or when coming out of the  
powered down mode.  
The receive side of the device is designed to accept the  
same frame sync and data clock as the transmit side and to  
be able to latch its own transmit PCM data word. Thus the  
PCM digital switch needs to be able to generate only one  
type of frame sync for use by both transmit and receive sec-  
tions of the device.  
The logical AND of the receive frame sync with the receive  
data clock tells the device to start latching the 8–bit serial  
word into the receive data input on the falling edges of the  
receive data clock. The internal receive logic counts the re-  
ceive data clock cycles and transfers the PCM data word to  
the digital–to–analog converter sequencer on the ninth data  
clock rising edge.  
The device recognizes Short Frame Sync clocking when  
the frame sync is held high for one and only one falling edge  
of the transmit data clock. The transmit logic decides on each  
frame sync whether it should interpret the next frame sync  
pulse as a Long or a Short Frame Sync. This decision is used  
for receive circuitry also. The device is designed to prevent  
PCM bus contention by not allowing the PCM data output to  
go low impedance for at least two frame sync cycles after  
power is applied or when coming out of the powered down  
mode.  
The receive side of the device is designed to accept the  
same frame sync and data clock as the transmit side and to  
be able to latch its own transmit PCM data word. Thus the  
PCM digital switch needs to be able to generate only one  
type of frame sync for use by both transmit and receive sec-  
tions of the device.  
The falling edge of the receive data clock latching a high  
logic level at the receive frame sync input tells the device to  
start latching the 8–bit serial word into the receive data input  
on the following eight falling edges of the receive data clock.  
The internal receive logic counts the receive data clock  
cycles and transfers the PCM data word to the digital–to–  
analog converter sequencer on the rising data clock edge af-  
ter the LSB has been latched into the device.  
This device is compatible with four digital interface modes.  
To ensure that this device does not reprogram itself for a dif-  
ferent timing mode, the BCLKR pin must change logic state  
no less than every 125 µs. The minimum PCM data bit clock  
frequency of 64 kHz satisfies this requirement.  
Interchip Digital Link (IDL)  
The Interchip Digital Link (IDL) Interface is one of two  
standard synchronous 2B+D ISDN timing interface modes  
with which this device is compatible. In the IDL mode, the de-  
vice can communicate in either of the two 64 kbps B chan-  
nels (refer to Figure 2c for sample timing). The IDL mode is  
selected when the BCLKR pin is held high for two or more  
FST (IDL SYNC) rising edges. The digital pins that control  
the transmit and receive PCM word transfers are repro-  
grammed to accommodate this mode. The pins affected are  
FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of  
four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT),  
and IDL RX (DR). The IDL interface mode provides access to  
both the transmit and receive PCM data words with common  
control clocks of IDL Sync and IDL Clock. In this mode, the  
This device is compatible with four digital interface modes.  
To ensure that this device does not reprogram itself for a dif-  
ferent timing mode, the BCLKR pin must change logic state  
no less than every 125 µs. The minimum PCM data bit clock  
frequency of 64 kHz satisfies this requirement.  
Short Frame Sync  
Short Frame Sync is the industry name for the type of  
clocking format that controls the transfer of the PCM data  
words (refer to Figure 2b). The ‘‘Frame Sync’’ or ‘‘Enable’’ is  
MOTOROLA  
MC14LC5480  
7
FSR pin controls whether the B1 channel or the B2 channel  
is used for both transmit and receive PCM data word trans-  
fers. When the FSR pin is low, the transmit and receive PCM  
words are transferred in the B1 channel, and for FSR high  
the B2 channel is selected. The start of the B2 channel is ten  
IDL CLK cycles after the start of the B1 channel.  
The IDL SYNC (FST, Pin 14) is the input for the IDL frame  
synchronization signal. The signal at this pin is nominally  
high for one cycle of the IDL Clock signal and is rising edge  
aligned with the IDL Clock signal. (Refer to Figure 4 and the  
IDL Timing specifications for more details.) This event identi-  
fies the beginning of the IDL frame. The frequency of the IDL  
Sync signal is 8 kHz. The rising edge of the IDL SYNC (FST)  
should be aligned approximately with the rising edge of  
MCLK. MCLK must be one of the clock frequencies specified  
in the Digital Switching Characteristics table, and is typically  
tied to IDL CLK (BCLKT).  
edge aligned with the DCL clock signal. (Refer to Figure 6  
and the GCI Timing specifications for more details.) This  
event identifies the beginning of the GCI frame. The frequen-  
cy of the FSC synchronization signal is 8 kHz. The rising  
edge of the FSC (FST) should be aligned approximately with  
the rising edge of MCLK. MCLK must be one of the clock fre-  
quencies specified in the Digital Switching Characteristics  
table, and is typically tied to DCL (BCLKT).  
The DCL (BCLKT, Pin 12) is the input for the clock that  
controls the PCM data transfers. The clock applied at the  
DCL input is twice the actual PCM data rate. The GCI frame  
begins with the logical AND of the FSC with the DCL. This  
event initiates the PCM data word transfers for both transmit  
and receive. This pin accepts a GCI data clock frequency of  
512 kHz to 6.176 MHz for PCM data rates of 256 kHz to  
3.088 MHz.  
The GCI D  
(DT, Pin 13) is the output for the transmit  
out  
The IDL CLK (BCLKT, Pin 12) is the input for the PCM  
data clock. All IDL PCM transfers and data control sequenc-  
ing are controlled by this clock following the IDL SYNC. This  
pin accepts an IDL data clock frequency of 256 kHz to 4.096  
MHz.  
The IDL TX (DT, Pin 13) is the output for the transmit PCM  
data word. Data bits are output for the B1 channel on se-  
quential rising edges of the IDL CLK signal beginning after  
the IDL SYNC pulse. If the B2 channel is selected, then the  
PCM word transfer starts on the eleventh IDL CLK rising  
edge after the IDL SYNC pulse. The IDL TX pin will remain  
low impedance for the duration of the PCM word until the  
LSB after the falling edge of IDL CLK. The IDL TX pin will re-  
main in a high impedance state when not outputting PCM  
data or when a valid IDL Sync signal is missing.  
PCM data word. Data bits are output for the B1 channel on  
alternate rising edges of the DCL clock signal, beginning with  
the FSC pulse. If the B2 channel is selected, then the PCM  
word transfer starts on the seventeenth DCL rising edge after  
the FSC rising edge. The D  
for 15–1/2 DCL clock cycles. The D  
out  
impedance after the second falling edge of the DCL clock  
during the LSB of the PCM word. The D pin will remain in  
pin will remain low impedance  
pin becomes high  
out  
out  
a high–impedance state when not outputting PCM data or  
when a valid FSC signal is missing.  
The D (DR, Pin 8) is the input for the receive PCM data  
in  
word. Data bits are latched in for the B1 channel on alternate  
rising edges of the DCL clock signal, beginning with the se-  
cond DCL clock after the rising edge of the FSC pulse. If the  
B2 channel is selected then the PCM word is latched in start-  
ing on the eighteenth DCL rising edge after the FSC rising  
edge.  
The IDL RX (DR, Pin 8) is the input for the receive PCM  
data word. Data bits are input for the B1 channel on sequen-  
tial falling edges of the IDL CLK signal beginning after the  
IDL SYNC pulse. If the B2 channel is selected, then the PCM  
word is latched in starting on the eleventh IDL CLK falling  
edge after the IDL SYNC pulse.  
PRINTED CIRCUIT BOARD LAYOUT  
CONSIDERATIONS  
The MC14LC5480 is manufactured using high–speed  
CMOS VLSI technology to implement the complex analog  
signal processing functions of a PCM Codec–Filter. The ful-  
ly–differential analog circuit design techniques used for this  
device result in superior performance for the switched capac-  
itor filters, the analog–to–digital converter (ADC) and the dig-  
ital–to–analog converter (DAC). Special attention was given  
to the design of this device to reduce the sensitivities of  
noise, including power supply rejection and susceptibility to  
radio frequency noise. This special attention to design in-  
cludes a fifth order low–pass filter, followed by a third order  
high–pass filter whose output is converted to a digital signal  
with greater than 75 dB of dynamic range, all operating on a  
single 5 V power supply. This results in a Mu–Law LSB size  
for small audio signals of about 386 µV. The typical idle chan-  
nel noise level of this device is less than one LSB. In addition  
to the dynamic range of the codec–filter function of this de-  
vice, the input gain–setting op amp has the capability of  
greater than 35 dB of gain intended for an electret micro-  
phone interface.  
General Circuit Interface (GCI)  
The General Circuit Interface (GCI) is the second of two  
standard synchronous 2B+D ISDN timing interface modes  
with which this device is compatible. In the GCI mode, the  
device can communicate in either of the two 64 kbps B–  
channels. (Refer to Figure 2d for sample timing.) The GCI  
mode is selected when the BCLKR pin is held low for two or  
more FST (FSC) rising edges. The digital pins that control  
the transmit and receive PCM word transfers are repro-  
grammed to accommodate this mode. The pins affected are  
FST, FSR, BCLKT, DT, and DR. The GCI Interface consists  
of four pins: FSC (FST), DCL (BCLKT), D  
(DT), and D  
out  
in  
(DR). The GCI interface mode provides access to both the  
transmit and receive PCM data words with common control  
clocks of FSC (frame synchronization clock) and DCL (data  
clock). In this mode, the FSR pin controls whether the B1  
channel or the B2 channel is used for both transmit and re-  
ceive PCM data word transfers. When the FSR pin is low, the  
transmit and receive PCM words are transferred in the B1  
channel, and for FSR high the B2 channel is selected. The  
start of the B2 channel is 16 DCL cycles after the start of the  
B1 channel.  
This device was designed for ease of implementation, but  
due to the large dynamic range and the noisy nature of the  
environment for this device (digital switches, radio tele-  
phones, DSP front–end, etc.) special care must be taken to  
assure optimum analog transmission performance.  
The FSC (FST, Pin 14) is the input for the GCI frame syn-  
chronization signal. The signal at this pin is nominally rising  
MC14LC5480  
8
MOTOROLA  
PC BOARD MOUNTING  
resulting from the high speed digital current spikes. The  
magnitude of digitally induced voltage spikes may be  
hundreds of times larger than the analog signal the  
device is required to digitize.  
It is recommended that the device be soldered to the PC  
board for optimum noise performance. If the device is to be  
used in a socket, it should be placed in a low parasitic pin  
inductance (generally, low–profile) socket.  
7. Use a short, wide, low inductance trace to connect the  
V
power supply pin to the 5 V power supply.  
DD  
Depending on the application, a double–sided PCB with  
bypass capacitors to the V ground plane, as  
POWER SUPPLY, GROUND, AND NOISE  
CONSIDERATIONS  
V
DD  
SS  
described above, may complete the low impedance  
coupling for the power supply. For a multilayer PC board  
This device is intended to be used in switching applica-  
tions which often require plugging the PC board into a rack  
with power applied. This is known as ‘‘hot–rack insertion.’’ In  
these applications care should be taken to limit the voltage  
with a power plane, connecting all of the V  
pins to the  
DD  
power plane would be the optimal power distribution  
method. The integrated circuit layout and packaging  
on any pin from going positive of the V  
pins, or negative of  
pins. One method is to extend the ground and power  
DD  
considerations for the 5 V V  
power circuit are  
ground circuit.  
DD  
essentially the same as for the V  
the V  
SS  
SS  
contacts of the PCB connector. The device has input protec-  
tion on all pins and may source or sink a limited amount of  
current without damage. Current limiting may be accom-  
plished by series resistors between the signal pins and the  
connector contacts.  
The most important considerations for PCB layout deal  
with noise. This includes noise on the power supply, noise  
generated by the digital circuitry on the device, and cross  
coupling digital or radio frequency signals into the audio sig-  
nals of this device. The best way to prevent noise is to:  
1. Keep digital signals as far away from audio signals as  
possible.  
8. The V  
AG  
pin is the reference for all analog signal  
processing. In some applications the audio signal to be  
digitized may be referenced to the V ground. To  
SS  
reduce the susceptibility to noise at the input of the ADC  
section, the three–terminal op amp may be used in a  
differential to single–ended circuit to provide level  
conversion from the V  
ground to the V ground with  
SS  
AG  
noise cancellation. The op amp may be used for more  
than35dBofgaininmicrophoneinterfacecircuits, which  
will require a compact layout with minimum trace lengths  
as well as isolation from noise sources. It is recom-  
mended that the layout be as symmetrical as possible to  
avoid any imbalances which would reduce the noise  
cancelling benefits of this differential op amp circuit.  
Refer to the application schematics for examples of this  
circuitry.  
2. Keep radio frequency signals as far away from the audio  
signals as possible.  
3. Use short, low inductance traces for the audio circuitry  
to reduce inductive, capacitive, and radio frequency  
noise sensitivities.  
If possible, reference audio signals to the V  
pin  
pin. Handset receivers and tele-  
AG  
4. Use short, low inductance traces for digital and RF  
circuitry to reduce inductive, capacitive, and radio  
frequency radiated noise.  
instead of to the V  
SS  
phone line interface circuits using transformers may be  
audio signal referenced completely to the V pin. Re-  
AG  
fer to the application schematics for examples of this  
circuitry. The V pin cannot be used for ESD or line  
5. Bypass capacitors should be connected from the V  
DD  
and V  
AG  
pins to V  
with minimal trace length. Ceramic  
SS  
AG  
monolithic capacitors of about 0.1 µF are acceptable to  
decouple the device from its own noise. The V  
protection.  
DD  
9. For applications using multiple MC14LC5480 PCM  
capacitor helps supply the instantaneous currents of the  
digital circuitry in addition to decoupling the noise which  
may be generated by other sections of the device or  
Codec–Filters, theV  
V
AG  
pinscannotbetiedtogether.The  
AG  
pinsarecapableofsourcingandsinkingcurrentand  
will each be driving the node, which will result in large  
contention currents, crosstalk susceptibilities, and in-  
creased noise.  
other circuitry on the power supply. The V  
capacitor helps to reduce the impedance of the V  
decoupling  
pin  
AG  
AG  
to V  
at frequencies above the bandwidth of the V  
SS  
AG  
generator, which reduces the susceptibility to RF noise.  
6. Use a short, wide, low inductance trace to connect the  
10. The MC14LC5480 is fabricated with advanced high–  
speed CMOS technology that is capable of responding  
to noise pulses on the clock pins of 1 ns or less. It should  
benotedthatnoisepulsesofsuchshortdurationmaynot  
be seen with oscilloscopes that have less bandwidth  
than 600 MHz. The most often encountered sources of  
clock noise spikes are inductive or capacitive coupling of  
high–speed logic signals, and ground bounce. The best  
solution for addressing clock spikes from coupling is to  
separate the traces and use short low inductance PC  
board traces. To address ground bounce problems, all  
integrated circuits should have high frequency bypass  
capacitors directly across their power supply pins, with  
low inductance traces for ground and power supply. A  
less than optimum solution may be to limit the bandwidth  
of the trace by adding series resistance and/or capaci-  
tance at the input pin.  
V
groundpintothepowersupplyground. TheV pin  
SS  
SS  
is the digital ground and the most negative power supply  
pin for the analog circuitry. All analog signal processing  
is referenced to the V  
circuitry will probably be powered by this same ground,  
care must be taken to minimize high frequency noise in  
pin, but because digital and RF  
AG  
the V  
trace. Depending on the application, a double–  
ground plane connecting all of the  
pins together would be a good  
SS  
sided PCB with a V  
SS  
digital and analog V  
SS  
grounding method. A multilayer PC board with a ground  
plane connecting all of the digital and analog V pins  
SS  
together would be the optimal ground configuration.  
These methods will result in the lowest resistance and  
the lowest inductance in the ground circuit. This is  
important to reduce voltage spikes in the ground circuit  
MOTOROLA  
MC14LC5480  
9
MAXIMUM RATINGS (Voltages Referenced to V  
Rating  
Pin)  
SS  
Symbol  
Value  
Unit  
V
DC Supply Voltage  
V
DD  
– 0.5 to 6  
Voltage on Any Analog Input or Output Pin  
Voltage on Any Digital Input or Output Pin  
Operating Temperature Range  
Storage Temperature Range  
V
V
– 0.3 to V  
– 0.3 to V  
+ 0.3  
+ 0.3  
V
SS  
DD  
DD  
V
SS  
T
– 40 to + 85  
– 85 to +150  
°C  
°C  
A
T
stg  
POWER SUPPLY (T = – 40 to + 85°C)  
A
Characteristics  
Min  
Typ  
Max  
Unit  
V
DC Supply Voltage  
4.75  
5.0  
5.25  
Active Power Dissipation (V  
= 5 V)  
(No Load, PI V  
(No Load, PI V  
– 0.5 V)  
– 1.5 V)  
15  
15  
24  
25  
mW  
DD  
DD  
DD  
Power–Down Dissipation (V for Logic Levels Must be 3.0 V)  
IH  
PDI = V  
FST and FSR = V , PDI = V  
SS  
0.01  
0.05  
0.5  
1.0  
mW  
SS  
DD  
DIGITAL LEVELS (V  
= + 5 V ± 5%, V  
= 0 V, T = – 40 to + 85°C)  
A
DD  
SS  
Characteristics  
Symbol  
Min  
Max  
0.6  
Unit  
V
Input Low Voltage  
Input High Voltage  
V
IL  
V
IH  
2.4  
V
Output Low Voltage (DT Pin, I = 2.5 mA)  
OL  
V
OL  
0.4  
V
Output High Voltage (DT Pin, I  
= – 2.5 mA)  
V
I
V – 0.5  
DD  
V
OH  
OH  
Input Low Current (V  
V V  
)
I
– 10  
– 10  
– 10  
+ 10  
+ 10  
+ 10  
10  
µA  
µA  
µA  
pF  
pF  
SS  
in  
DD  
IL  
IH  
Input High Current (V  
V V )  
DD  
SS  
in  
Output Current in High Impedance State (V  
DT V  
)
I
SS  
DD  
OZ  
Input Capacitance of Digital Pins (Except DT)  
Input Capacitance of DT Pin when High–Z  
C
in  
C
15  
out  
NOTE: Bold type indicates a change from the MC145480 to the MC14LC5480.  
MC14LC5480  
10  
MOTOROLA  
ANALOG ELECTRICAL CHARACTERISTICS (V  
= + 5 V ± 5%, V  
= 0 V, T = – 40 to + 85°C)  
SS A  
DD  
Characteristics  
Min  
10  
1.2  
0
Typ  
Max  
± 1.0  
Unit  
µA  
Input Current  
TI+, TI–  
TI+, TI–  
TI+, TI–  
TI+, TI–  
TI+, TI–  
TI+, TI–  
± 0.1  
Input Resistance to V  
(V  
– 0.5 V V V  
in AG  
+ 0.5 V)  
MΩ  
pF  
AG AG  
Input Capacitance  
10  
Input Offset Voltage of TG Op Amp  
Input Common Mode Voltage Range  
Input Common Mode Rejection Ratio  
± 5  
mV  
V
V
– 2.0  
DD  
60  
3000  
95  
dB  
Gain Bandwidth Product (10 kHz) of TG Op Amp (R 10 k)  
kHz  
dB  
L
DC Open Loop Gain of TG Op Amp (R 10 k)  
L
Equivalent Input Noise (C–Message) Between TI+ and TI– at TG  
Output Load Capacitance for TG Op Amp  
Output Voltage Range for TG  
– 30  
dBrnC  
pF  
100  
V
(R = 10 kto V  
AG  
)
0.5  
1.0  
V
DD  
V
DD  
– 0.5  
– 1.0  
L
(R = 2 kto V  
)
L
AG  
Output Current (0.5 V V  
out  
V  
– 0.5 V)  
TG, RO+, RO–  
TG, RO+, and RO–  
RO+ or RO–  
± 1.0  
2
mA  
kΩ  
DD  
Output Load Resistance to V  
AG  
Output Impedance (0 to 3.4 kHz)  
Output Load Capacitance  
1
RO+ or RO–  
0
500  
± 25  
2.6  
pF  
DC Output Offset Voltage of RO+ or RO– Referenced to V  
AG  
mV  
V
V
AG  
Output Voltage Referenced to V  
(No Load)  
2.2  
± 2.0  
2.4  
± 10  
SS  
V
AG  
Output Current with ± 25 mV Change in Output Voltage  
mA  
dBC  
Power Supply Rejection Ratio  
(0 to 100 kHz @100 mVrms Applied to V  
Transmit  
Receive  
50  
50  
80  
75  
,
DD  
C–Message Weighting, All Analog Signals  
Referenced to V Pin)  
AG  
Power Drivers PI, PO+, PO–  
Input Current (V  
AG  
– 0.5 V PI V  
AG  
+ 0.5 V)  
PI  
PI  
PI  
10  
± 0.05  
± 1.0  
µA  
MΩ  
mV  
mV  
mA  
Input Resistance (V  
AG  
– 0.5 V PI V + 0.5 V)  
AG  
Input Offset Voltage  
Output Offset Voltage of PO+ Relative to PO– (Inverted Unity Gain for PO–)  
Output Current (V + 0.7 V PO+ or PO– V – 0.7 V)  
± 20  
± 50  
± 10  
SS  
DD  
PO+ or PO– Output Resistance (Inverted Unity Gain for PO–)  
Gain Bandwidth Product (10 kHz, Open Loop for PO–)  
1
1000  
kHz  
pF  
Load Capacitance (PO+ or PO– to V , or PO+ to PO–)  
AG  
0
1000  
+ 0.2  
Gain of PO+ Relative to PO– (R = 300 , + 3 dBm0, 1 kHz)  
– 0.2  
45  
0
dB  
L
Total Signal to Distortion at PO+ and PO– with a 300 Differential Load  
60  
dBC  
dB  
Power Supply Rejection Ratio  
(0 to 25 kHz @ 100 mVrms Applied to V  
0 to 4 kHz  
4 to 25 kHz  
40  
55  
40  
.
DD  
PO– Connected to PI. Differential or Measured  
Referenced to V Pin.)  
AG  
NOTE: Bold type indicates a change from the MC145480 to the MC14LC5480.  
MOTOROLA  
MC14LC5480  
11  
ANALOG TRANSMISSION PERFORMANCE  
(V  
DD  
= + 5 V ± 5%, V  
= 0 V, All Analog Signals Referenced to V , 0 dBm0 = 0.775 Vrms = + 0 dBm @ 600 , FST = FSR = 8 kHz,  
SS  
AG  
BCLKT = MCLK = 2.048 MHz Synchronous Operation, T = – 40 to + 85°C, Unless Otherwise Noted)  
A
End–to–End  
A/D  
D/A  
Characteristics  
Absolute Gain (0 dBm0 @ 1.02 kHz, T = 25°C, V  
Units  
Min  
Max  
Min  
Max  
Min  
Max  
= 5.0 V)  
– 0.25 + 0.25 – 0.25 + 0.25  
dB  
A
DD  
Absolute Gain Variation with Temperature (Referenced to 25°C)  
0 to + 70°C  
– 40 to + 85°C  
± 0.03  
± 0.05  
± 0.03  
± 0.05  
dB  
dB  
dB  
Absolute Gain Variation with Power Supply (T = 25°C)  
± 0.03  
± 0.03  
A
Gain vs Level Tone (Mu–Law, Relative to – 10 dBm0, 1.02 kHz)  
+ 3 to – 40 dBm0  
– 0.30 + 0.20 – 0.20 + 0.20  
– 0.8  
– 1.2  
– 40 to – 50 dBm0  
– 50 to – 55 dBm0  
+ 0.40 – 0.40 + 0.40  
+ 0.80 – 0.80 + 0.80  
Gain vs Level Pseudo Noise, CCITT G.712  
(A–Law, Relative to – 10 dBm0)  
– 10 to – 40 dBm0  
– 40 to – 50 dBm0  
– 50 to – 55 dBm0  
– 0.25 + 0.25 – 0.25 + 0.25  
– 0.60 + 0.30 – 0.30 + 0.30  
– 1.00 + 0.45 – 0.45 + 0.45  
dB  
dBC  
dB  
Total Distortion, 1.02 kHz Tone (Mu–Law, C–Message Weighting)  
+ 3 dBm0  
0 to – 30 dBm0  
– 40 dBm0  
34  
36  
30  
25  
34  
36  
30  
25  
– 45 dBm0  
Total Distortion, Pseudo Noise, CCITT G.714 (A–Law)  
– 3 dBm0  
– 6 to – 27 dBm0  
– 34 dBm0  
30  
36  
34  
29  
19  
14  
30  
36  
35  
30  
20  
15  
– 40 dBm0  
– 50 dBm0  
– 55 dBm0  
Idle Channel Noise (For End–to–End and A/D, See Note 1)  
(Mu–Law, C–Message Weighted)  
(A–Law, Psophometric Weighted)  
17  
– 69  
11  
– 79  
dBrnc0  
dBm0p  
Frequency Response (Relative to 1.02 kHz @ 0 dBm0)  
15 Hz  
50 Hz  
60 Hz  
– 40  
– 30  
– 26  
– 0.4  
– 0.5  
– 0.5  
– 0.5  
– 0.5  
0
0
0
0
dB  
200 Hz  
– 1.0  
300 to 3000 Hz  
3000 to 3200 Hz  
3300 Hz  
– 0.20 + 0.15 – 0.15 + 0.15  
– 0.20 + 0.20 – 0.20 + 0.20  
– 0.35 + 0.15 – 0.35 + 0.15  
– 0.8  
3400 Hz  
4000 Hz  
0
– 14  
– 32  
– 0.85  
0
– 14  
30  
4600 Hz to 100 kHz  
In–Band Spurious (1.02 kHz @ 0 dBm0, Transmit and Receive)  
300 to 3400 Hz  
dB  
dB  
– 48  
– 48  
– 48  
Out–of–Band Spurious at RO+ (300 to 3400 Hz @ 0 dBm0 in)  
4600 to 7600 Hz  
7600 to 8400 Hz  
8400 to 100,000 Hz  
– 30  
– 40  
– 30  
– 30  
– 40  
– 30  
Idle Channel Noise Selective (8 kHz, Input = V , 30 Hz Bandwidth)  
AG  
– 70  
– 70  
205  
dBm0  
µs  
Absolute Delay (1600 Hz)  
315  
Group Delay Referenced to 1600 Hz  
500 to 600 Hz  
600 to 800 Hz  
210  
130  
70  
35  
70  
– 40  
– 40  
– 40  
– 30  
85  
µs  
800 to 1000 Hz  
1000 to 1600 Hz  
1600 to 2600 Hz  
2600 to 2800 Hz  
2800 to 3000 Hz  
95  
145  
110  
175  
Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2)  
– 75  
– 75  
dB  
dB  
Intermodulation Distortion of Two Frequencies of Amplitudes  
(– 4 to – 21 dBm0 from the Range 300 to 3400 Hz)  
– 41  
– 41  
– 41  
NOTES:  
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.  
2. Selectively measured while stimulated with 2667 Hz @ – 50 dBm0.  
3. Bold type indicates a change from the MC145480 to the MC14LC5480.  
MC14LC5480  
12  
MOTOROLA  
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC  
(V  
DD  
= + 5 V ± 5%, V  
= 0 V, All Digital Signals Referenced to V , T = – 40 to + 85°C, C = 150 pF, Unless Otherwise Noted)  
SS  
SS  
A
L
Ref.  
No.  
Characteristics  
Min  
Typ  
Max  
Unit  
1
Master Clock Frequency for MCLK  
256  
512  
kHz  
1536  
1544  
2048  
2560  
4096  
1
2
MCLK Duty Cycle for 256 kHz Operation  
45  
50  
50  
50  
50  
64  
50  
50  
20  
80  
0
55  
%
ns  
ns  
ns  
ns  
ns  
ns  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)  
Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)  
Rise Time for All Digital Signals  
3
4
50  
50  
5
Fall Time for All Digital Signals  
6
Setup Time from MCLK Low to FST High  
7
Setup Time from FST High to MCLK Low  
8
Bit Clock Data Rate for BCLKT or BCLKR  
4096  
9
Minimum Pulse Width High for BCLKT or BCLKR  
Minimum Pulse Width Low for BCLKT or BCLKR  
Hold Time from BCLKT (BCLKR) Low to FST (FSR) High  
Setup Time for FST (FSR) High to BCLKT (BCLKR) Low  
Setup Time from DR Valid to BCLKR Low  
10  
11  
12  
13  
14  
Hold Time from BCLKR Low to DR Invalid  
50  
LONG FRAME SPECIFIC TIMING  
15  
16  
17  
18  
Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low  
Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data  
Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data  
50  
10  
60  
60  
60  
ns  
ns  
ns  
ns  
Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge  
of FST to DT Output High Impedance  
19  
Minimum Pulse Width Low for FST or FSR  
50  
ns  
SHORT FRAME SPECIFIC TIMING  
20  
21  
22  
23  
Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low  
Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low  
Delay Time from BCLKT High to DT Data Valid  
50  
50  
10  
10  
60  
60  
ns  
ns  
ns  
ns  
Delay Time from the 8th BCLKT Low to DT Output High Impedance  
MOTOROLA  
MC14LC5480  
13  
1
7
4
3
5
6
2
MCLK  
8
1
2
3
4
5
6
7
8
9
BCLKT  
12  
9
11  
15  
10  
FST  
DT  
16  
18  
17  
18  
16  
MSB  
CH1  
CH2  
CH3  
ST1  
ST2  
ST3  
LSB  
8
1
2
3
4
5
6
7
8
9
BCLKR  
FSR  
11  
15  
9
12  
10  
14  
13  
MSB  
CH1  
CH2  
CH3  
ST1  
ST2  
ST3  
LSB  
DR  
Figure 3. Long Frame Sync Timing  
MC14LC5480  
14  
MOTOROLA  
1
7
4
3
5
6
2
MCLK  
12  
8
1
2
3
4
5
6
7
8
9
BCLKT  
FST  
9
20  
21  
10  
11  
23  
22  
22  
MSB  
CH1  
CH2  
CH3  
ST1  
ST2  
ST3  
LSB  
DT  
8
1
2
3
4
5
6
7
8
9
BCLKR  
20  
9
21  
10  
11  
12  
FSR  
DR  
14  
13  
MSB  
CH1  
CH2  
CH3  
ST1  
ST2  
ST3  
LSB  
Figure 4. Short Frame Sync Timing  
MOTOROLA  
MC14LC5480  
15  
DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE  
(V  
DD  
= 5.0 V ± 5%, T = – 40 to + 85°C, C = 150 pF, See Figure 5 and Note 1)  
A L  
Ref.  
No.  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
Characteristics  
Min  
Max  
Unit  
Time Between Successive IDL Syncs  
Note 2  
Hold Time of IDL SYNC After Falling Edge of IDL CLK  
Setup Time of IDL SYNC Before Falling Edge IDL CLK  
IDL Clock Frequency  
20  
60  
256  
50  
50  
20  
75  
10  
10  
ns  
ns  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4096  
IDL Clock Pulse Width High  
IDL Clock Pulse Width Low  
Data Valid on IDL RX Before Falling Edge of IDL CLK  
Data Valid on IDL RX After Falling Edge of IDL CLK  
Falling Edge of IDL CLK to High–Z on IDL TX  
Rising Edge of IDL CLK to Low–Z and Data Valid on IDL TX  
Rising Edge of IDL CLK to Data Valid on IDL TX  
50  
60  
50  
NOTES:  
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.  
2. In IDL mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words  
are accessed during the B2 channel as shown in Figure 5. IDL accesses must occur at a rate of 8 kHz (125 µs interval).  
31  
IDLE SYNC  
(FST)  
32  
33  
32  
34  
35  
IDL CLOCK  
(BCLKT)  
1
2
3
4
5
6
7
8
9
10  
39  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1
2
36  
41  
39  
40  
41  
40  
IDL TX  
(DT)  
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB  
38  
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB  
38  
37  
37  
IDL RX  
(DR)  
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB  
MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB  
Figure 5. IDL Interface Timing  
MC14LC5480  
16  
MOTOROLA  
DIGITAL SWITCHING CHARACTERISTICS FOR GCI MODE  
(V  
DD  
= 5.0 V ± 5%, T = – 40 to + 85°C, C = 150 pF, See Figure 6 and Note 1)  
A L  
Ref.  
No.  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
Characteristics  
Min  
Max  
Unit  
Time Between Successive FSC Pulses  
DCL Clock Frequency  
Note 2  
512  
50  
50  
20  
60  
6176  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DCL Clock Pulse Width High  
DCL Clock Pulse Width Low  
Hold Time of FSC After Falling Edge of DCL  
Setup Time of FSC to DCL Falling Edge  
Rising Edge of DCL (After Rising Edge of FSC) to Low Impedance and Valid Data of D  
60  
60  
60  
50  
out  
Rising Edge of FSC (While DCL is High) to Low Impedance and Valid Data of D  
out  
Rising Edge of DCL to Valid Data on D  
out  
Second DCL Falling Edge During LSB to High Impedance of D  
10  
20  
out  
Setup Time of D Before Rising Edge of DCL  
in  
Hold Time of D After DCL Rising Edge  
in  
60  
NOTES:  
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.  
2. In GCI mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words  
are accessed during the B2 channel as shown in Figure 6. GCI accesses must occur at a rate of 8 kHz (125 µs interval).  
42  
FSC  
(FST)  
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34  
DCL  
(BCLKT)  
51  
50  
50  
48  
51  
49  
MSB CH1  
53  
CH2  
CH2  
CH3 ST1  
ST2  
ST2  
ST3 LSB  
MSB CH1  
CH2  
CH3  
CH3  
ST1  
53  
ST2  
ST3 LSB  
D
(DT)  
(DR)  
out  
52  
52  
CH2  
MSB CH1  
CH3  
ST1  
ST3  
LSB  
MSB CH1  
ST1  
ST2  
ST3  
LSB  
D
in  
46  
FSC  
(FST)  
46  
47  
43  
44  
DCL  
(BCLKT)  
5
1
2
3
4
49  
45  
48  
D
(DT)  
(DR)  
MSB  
CH1  
out  
52  
53  
D
MSB  
CH1  
in  
Figure 6. GCI Interface Timing  
MOTOROLA  
MC14LC5480  
17  
0.1  
µ
F
+
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
RO+  
RO–  
PI  
V
10 k  
AG  
AUDIO OUT  
ANALOG IN  
1.0  
1.0  
µ
F
F
10 k  
TI+  
TI–  
3
10 kΩ  
10 k  
4
PO–  
PO+  
TG  
µ
5
Mu/A  
+ 5 V  
6
V
V
+ 5 V  
DD  
SS  
7
FSR  
DR  
FST  
DT  
8 kHz  
0.1 µF  
8
PCM OUT  
2.048 MHz  
9
BCLKR  
PDI  
BCLKT  
MCLK  
10  
PCM IN  
Figure 7. MC14LC5480 Test Circuit with Differential Input and Output  
AUDIO OUT  
0.1  
µ
F
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
R
2 k  
RO+  
RO–  
PI  
10 kΩ  
V
L
AG  
1.0  
1.0  
µ
F
F
10 k  
TI+  
TI–  
10 k  
3
68 µF  
AUDIO OUT  
10 kΩ  
10 kΩ  
10 k  
ANALOG IN  
+
4
PO–  
PO+  
TG  
R
150  
L
µ
5
Mu/A  
+ 5 V  
10 k  
6
V
V
+ 5 V  
DD  
SS  
7
FSR  
DR  
FST  
DT  
8 kHz  
0.1 µF  
8
PCM OUT  
2.048 MHz  
9
BCLKR  
PDI  
BCLKT  
MCLK  
10  
PCM IN  
Figure 8. MC14LC5480 Test Circuit with Input and Output Referenced to V  
SS  
MC14LC5480  
18  
MOTOROLA  
2.048 MHz  
18 pF  
18 pF  
10 M  
+ 5 V  
2.048 MHz  
(BCLKT, BCLKR, MCLK)  
300  
V
R
OSC IN  
OSC  
OUT 1 OUT 2  
OSC  
CC  
8 kHz  
(FST, FSR)  
MC74HC4060  
Q4  
0.1 µF  
GND  
Q8  
+ 5 V  
V
CC  
J
Q
J
Q
1/2 MC74HC73  
1/2 MC74HC73  
K
Q
K
Q
GND  
R
R
+ 5 V  
8 kHz  
256  
1
2
3
4
5
6
7
8
9
2.048 MHz  
Figure 9. Long Frame Sync Clock Circuit for 2.048 MHz  
+5 V  
1 k  
SIDETONE  
0.1  
µF  
68 µF  
1 kΩ  
420 pF  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
RO+  
RO–  
V
AG  
75 k  
0.1  
µ
F
F
1 k  
TI+  
MIC  
1 k  
3
4
PI  
TI–  
TG  
0.1  
µ
PO–  
PO+  
75 kΩ  
REC  
5
+ 5 V  
Mu/A  
420 pF  
6
V
V
+ 5 V  
DD  
SS  
7
IDL SYNC – 8 kHz  
IDL TX  
FSR  
DR  
FST  
DT  
0.1 µF  
8
+ 5 V  
9
BCLKT  
BCLKR  
PDI  
IDL CLOCK – 2.048 MHz  
10  
MCLK  
IDL RX  
B1 – 0 V  
B2 – + 5 V  
Figure 10. MC14LC5480 Analog Interface to Handset with IDL Clocking  
MOTOROLA  
MC14LC5480  
19  
1.0  
µF  
10 kΩ  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
RO+  
RO–  
PI  
V
AG  
10 k  
10 k  
TI+  
TI–  
R0 = 600  
TIP  
R0  
3
0.1 µF  
10 kΩ  
4
PO–  
PO+  
TG  
N = 1  
N = 1  
5
Mu/A  
+ 5 V  
RING  
6
V
V
+ 5 V  
DD  
SS  
7
FSR  
DR  
FST  
DT  
FSC – 8 kHz  
0.1 µF  
8
D
out  
9
BCLKR  
PDI  
BCLKT  
MCLK  
DCL – 4.096 MHz  
10  
D
in  
B1 – 0 V  
B2 – + 5 V  
Figure 11. MC14LC5480 Transformer Interface to 600 Telephone Line with GCI Clocking  
1.0 µF  
10 k  
R0 = 600  
TIP  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
RO+  
RO–  
PI  
V
AG  
10 k  
TI+  
TI–  
N = 0.5  
1/4 R0  
10 kΩ  
3
0.1 µF  
20 kΩ  
4
PO–  
PO+  
TG  
N = 0.5  
5
– 48 V  
Mu/A  
+ 5 V  
6
+ 5 V  
N = 0.5  
V
V
SS  
DD  
7
8 kHz  
FSR  
DR  
FST  
DT  
RING  
0.1 µF  
8
PCM OUT  
2.048 MHz  
9
BCLKR  
PDI  
BCLKT  
MCLK  
10  
PCM IN  
Figure 12. MC14LC5480 Step–Up Transformer Interface to 600 Telephone Line  
MC14LC5480  
20  
MOTOROLA  
Table 3. Mu–Law Encode–Decode Characteristics  
Normalized  
Digital Code  
Encode  
Decision  
Levels  
Normalized  
Decode  
Levels  
1
2
3
4
5
6
7
8
Chord  
Number  
Number  
of Steps  
Step  
Size  
Sign  
Chord Chord Chord Step  
Step Step  
Step  
8159  
7903  
4319  
4063  
2143  
2015  
1055  
991  
511  
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
8031  
4191  
2079  
1023  
495  
231  
99  
8
16  
256  
7
6
5
4
3
2
1
16  
16  
16  
16  
16  
16  
128  
64  
32  
16  
8
479  
239  
223  
103  
95  
4
35  
33  
31  
15  
1
2
1
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
NOTES:  
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.  
2. Digital code includes inversion of all magnitude bits.  
MOTOROLA  
MC14LC5480  
21  
Table 4. A–Law Encode–Decode Characteristics  
Normalized  
Digital Code  
Encode  
Decision  
Levels  
Normalized  
Decode  
Levels  
1
2
3
4
5
6
7
8
Chord  
Number  
Number  
of Steps  
Step  
Size  
Sign  
Chord Chord Chord Step  
Step Step  
Step  
4096  
3968  
2176  
2048  
1088  
1024  
544  
512  
272  
256  
136  
128  
68  
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032  
2112  
1056  
528  
264  
132  
66  
7
16  
128  
6
5
4
3
2
16  
16  
16  
16  
16  
32  
64  
32  
16  
8
4
64  
1
2
2
1
0
NOTES:  
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.  
2. Digital code includes inversion of all even numbered bits.  
MC14LC5480  
22  
MOTOROLA  
PACKAGE DIMENSIONS  
P SUFFIX  
PLASTIC DIP  
CASE 738–03  
-A-  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEAD WHEN  
FORMED PARALLEL.  
20  
1
11  
10  
B
4. DIMENSION B DOES NOT INCLUDE MOLD  
FLASH.  
C
L
INCHES  
MILLIMETERS  
DIM  
A
B
C
D
E
F
G
J
K
L
M
N
MIN  
MAX  
1.070  
0.260  
0.180  
0.022  
MIN  
25.66  
6.10  
3.81  
0.39  
1.27 BSC  
1.27  
2.54 BSC  
0.21  
MAX  
27.17  
6.60  
4.57  
0.55  
1.010  
0.240  
0.150  
0.015  
0.050 BSC  
0.050  
0.100 BSC  
0.008  
0.110  
-T-  
SEATING  
PLANE  
K
M
0.070  
1.77  
E
N
0.015  
0.140  
0.38  
3.55  
G
F
J 20 PL  
2.80  
0.300 BSC  
15  
0.040  
7.62 BSC  
15  
0.51 1.01  
D 20 PL  
M
M
0.25 (0.010)  
T
B
0°  
°
0°  
°
0.020  
M
M
0.25 (0.010)  
T
A
DW SUFFIX  
SOG PACKAGE  
CASE 751D–04  
NOTES:  
–A–  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
20  
11  
4. MAXIMUM MOLD PROTRUSION 0.150  
(0.006) PER SIDE.  
10X P  
–B–  
5. DIMENSION D DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.13  
(0.005) TOTAL IN EXCESS OF D DIMENSION  
AT MAXIMUM MATERIAL CONDITION.  
M
M
0.010 (0.25)  
B
1
10  
MILLIMETERS  
INCHES  
20X D  
DIM  
A
B
C
D
MIN  
12.65  
7.40  
2.35  
0.35  
0.50  
MAX  
12.95  
7.60  
2.65  
0.49  
0.90  
MIN  
MAX  
0.510  
0.299  
0.104  
0.019  
0.035  
J
0.499  
0.292  
0.093  
0.014  
0.020  
M
S
S
0.010 (0.25)  
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC  
0.050 BSC  
0.25  
0.10  
0
0.32  
0.25  
7
0.010  
0.004  
0
0.012  
0.009  
7
R X 45  
10.05  
0.25  
10.55  
0.75  
0.395  
0.010  
0.415  
0.029  
C
SEATING  
PLANE  
–T–  
M
18X G  
K
MOTOROLA  
MC14LC5480  
23  
SD SUFFIX  
SSOP  
CASE 940C–02  
NOTES:  
1. CONTROLLING DIMENSION: MILLIMETER.  
2. DIMENSIONS AND TOLERANCES PER ANSI  
Y14.5M, 1982.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD FLASH OR PROTRUSIONS AND ARE  
MEASURED AT THE PARTING LINE. MOLD  
FLASH OR PROTRUSIONS SHALL NOT  
EXCEED 0.15MM PER SIDE.  
20  
11  
10  
B
–R–  
C
1
4. DIMENSION IS THE LENGTH OF TERMINAL  
FOR SOLDERING TO A SUBSTRATE.  
5. TERMINAL POSITIONS ARE SHOWN FOR  
REFERENCE ONLY.  
0.076 (0.003)  
A
6. THE LEAD WIDTH DIMENSION DOES NOT  
INCLUDE DAMBAR PROTRUSION.  
ALLOWABLE DAMBAR PROTRUSION SHALL  
BE 0.08MM TOTAL IN EXCESS OF THE LEAD  
WIDTH DIMENSION.  
–P–  
N
M
M
MILLIMETERS  
INCHES  
0.25 (0.010)  
R
DIM  
A
B
C
D
MIN  
7.10  
5.20  
1.75  
0.25  
0.65  
MAX  
7.30  
5.38  
1.99  
0.38  
1.00  
MIN  
MAX  
0.287  
0.212  
0.078  
0.015  
0.039  
L
0.280  
0.205  
0.069  
0.010  
0.026  
J
M
F
G
H
J
L
M
N
0.65 BSC  
0.026 BSC  
0.59  
0.10  
7.65  
0
0.75  
0.20  
7.90  
8
0.023  
0.004  
0.301  
0
0.030  
0.008  
0.311  
8
G
F
H
D
NOTE 4  
0.05  
0.21  
0.002  
0.008  
M
S
0.120 (0.005)  
T P  
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding  
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,  
andspecificallydisclaimsanyandallliability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different  
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does  
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in  
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of  
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such  
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless  
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.  
Motorola and  
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.  
How to reach us:  
USA/EUROPE: Motorola Literature Distribution;  
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,  
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447  
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315  
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609  
INTERNET: http://Design–NET.com  
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,  
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298  
MC14LC5480/D  
配单直通车
MC14LC5480DW产品参数
型号:MC14LC5480DW
是否Rohs认证: 不符合
生命周期:Transferred
包装说明:SOP, SOP20,.4
Reach Compliance Code:unknown
HTS代码:8542.39.00.01
风险等级:5.56
压伸定律:A/MU-LAW
滤波器:YES
最大增益公差:0.25 dB
JESD-30 代码:R-PDSO-G20
JESD-609代码:e0
长度:12.8 mm
线性编码:NOT AVAILABLE
功能数量:1
端子数量:20
工作模式:SYNCHRONOUS/ASYNCHRONOUS
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP20,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
电源:5 V
认证状态:Not Qualified
座面最大高度:2.65 mm
子类别:Codecs
标称供电电压:5 V
表面贴装:YES
技术:CMOS
电信集成电路类型:PCM CODEC
温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
宽度:7.5 mm
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!