欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • MCM69P737TQ3.0
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • MCM69P737TQ3.0图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • MCM69P737TQ3.0
  • 数量19759 
  • 厂家MOT 
  • 封装QFP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • MCM69P737TQ3.0图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • MCM69P737TQ3.0
  • 数量6000 
  • 厂家MOT 
  • 封装QFP 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • MCM69P737TQ3.0图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • MCM69P737TQ3.0
  • 数量26500 
  • 厂家FREESCAL 
  • 封装TQFP 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • MCM69P737TQ3.0图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • MCM69P737TQ3.0
  • 数量3536 
  • 厂家MOT 
  • 封装QFP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • MCM69P737TQ3.0图
  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • MCM69P737TQ3.0
  • 数量4500 
  • 厂家FREESCALE 
  • 封装N/A 
  • 批号2024 
  • 上海原装现货库存,欢迎查询!
  • QQ:2719079875QQ:2719079875 复制
    QQ:2300949663QQ:2300949663 复制
  • 15821228847 QQ:2719079875QQ:2300949663
  • MCM69P737TQ3.0图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • MCM69P737TQ3.0
  • 数量65000 
  • 厂家FREESCAL 
  • 封装TQFP 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • MCM69P737TQ3.0图
  • 长荣电子

     该会员已使用本站14年以上
  • MCM69P737TQ3.0
  • 数量
  • 厂家MOT 
  • 封装QFP 
  • 批号00+ 
  • 现货
  • QQ:172370262QQ:172370262 复制
  • 754-4457500 QQ:172370262
  • MCM69P737TQ3.0图
  • 深圳市瑞天芯科技有限公司

     该会员已使用本站7年以上
  • MCM69P737TQ3.0
  • 数量20000 
  • 厂家MOTOROLA 
  • 封装QFP 
  • 批号22+ 
  • 深圳现货库存,保证原装正品
  • QQ:1940213521QQ:1940213521 复制
  • 15973558688 QQ:1940213521
  • MCM69P737TQ3.0图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • MCM69P737TQ3.0
  • 数量9800 
  • 厂家MOTOROLA(摩托罗拉) 
  • 封装TQFP 
  • 批号24+ 
  • 原厂渠道,全新原装现货,欢迎查询!
  • QQ:97877807QQ:97877807 复制
  • 171-4755-1968(微信同号) QQ:97877807
  • MCM69P737TQ3.0图
  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
  • MCM69P737TQ3.0
  • 数量8500 
  • 厂家N/A 
  • 封装QFP 
  • 批号20+ 
  • 全新原装挺实单欢迎来撩/可开票
  • QQ:1092793871QQ:1092793871 复制
  • -0755-88910020 QQ:1092793871
  • MCM69P737TQ3.0图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • MCM69P737TQ3.0
  • 数量18000 
  • 厂家原厂品牌 
  • 封装原厂外观 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921

产品型号MCM69P737TQ3.0的概述

芯片MCM69P737TQ3.0的概述 MCM69P737TQ3.0是一款高性能的多功能集成电路芯片,广泛应用于现代电子设备中,这些设备通常涉及到计算、通信和控制应用。凭借其多种功能和灵活性,该芯片为工程师和设计师提供了一个强大的工具,能够满足多种不同的需求。 MCM69P737TQ3.0采用了先进的半导体制造工艺,具有低功耗和高效能的特点,可以在各种工作条件下稳定运行。其设计理念是为了应对日益增长的电子设备对处理能力和功能集成度的需求。此外,该芯片还具备良好的兼容性,能够方便地与其他集成电路和外围设备联接。 芯片MCM69P737TQ3.0的详细参数 在具体的技术参数方面,MCM69P737TQ3.0的关键指标包括: - 工作电压:一般在3.3V到5V之间,这一范围内运行可以确保芯片的稳定性。 - 工作温度范围:该芯片能够在广泛的温度范围内工作,通常为-40°C至+85°C,这样的设...

产品型号MCM69P737TQ3.0R的Datasheet PDF文件预览

Order this document  
by MCM69P737/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69P737  
128K x 36 Bit Pipelined  
BurstRAM Synchronous  
Fast Static RAM  
TheMCM69P737isa4M–bitsynchronousfaststaticRAMdesignedtoprovide  
a burstable, high performance, secondary cache for the PowerPC and other  
high performance microprocessors. It is organized as 128K words of 36 bits  
each. This device integrates input registers, an output register, a 2–bit address  
counter, and high speed SRAM onto a single monolithic circuit for reduced parts  
count in cache data RAM applications. Synchronous design allows precise cycle  
control with the use of an external clock (K).  
ZP PACKAGE  
PBGA  
CASE 999–02  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable(G) and linear burst order (LBO) are clock (K) controlled through positive–  
edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM69P737 (burst sequence  
operates in linear or interleaved mode dependent upon the state of LBO) and  
controlled by the burst address advance (ADV) input pin.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls  
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte  
writes SBx are asserted with SW. All bytes are written if either SGW is asserted  
or if all SBx and SW are asserted.  
For read cycles, pipelined SRAMs output data is temporarily stored by an  
edge–triggeredoutput register and then released to the output buffers at the next  
rising edge of clock (K).  
The MCM69P737 operates from a 3.3 V core power supply and all outputs  
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-  
dard JESD8–5 compatible.  
MCM69P737–3.0: 3 ns Access/5 ns Cycle (200 MHz)  
MCM69P737–3.2: 3.2 ns Access/5.5 ns Cycle (183 MHz)  
MCM69P737–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)  
MCM69P737–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)  
MCM69P737–4: 4 ns Access/7.5 ns Cycle (133 MHz)  
3.3 V ± 5% Core Power Supply for MCM69P737–3.0 and  
MCM69P737–3.2  
3.3 V + 10%, – 5% Core Power Supply for MCM69P737–3.5,  
MCM69P737–3.8, and MCM69P737–4  
2.5 V or 3.3 V I/O Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Single–Cycle Deselect Timing  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
PB1 Version 2.0 Compatible  
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
REV 8  
12/10/98  
Motorola, Inc. 1998  
FUNCTIONAL BLOCK DIAGRAM  
LBO  
ADV  
K
BURST  
COUNTER  
CLR  
2
17  
ADSC  
ADSP  
128K x 36  
ARRAY  
K2  
2
SA  
SA1  
SA0  
17  
15  
ADDRESS  
REGISTER  
SGW  
SW  
WRITE  
REGISTER  
a
36  
36  
SBa  
WRITE  
REGISTER  
b
SBb  
SBc  
4
DATA–IN  
REGISTER  
DATA–OUT  
REGISTER  
WRITE  
REGISTER  
c
K
WRITE  
REGISTER  
d
SBd  
K2  
K
SE1  
SE2  
SE3  
ENABLE  
REGISTER  
ENABLE  
REGISTER  
G
DQa – DQd  
MCM69P737  
2
MOTOROLA FAST SRAM  
PIN ASSIGNMENTS  
1
2
3
4
5
6
7
10099 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
A
B
C
D
E
DQc  
DQc  
DQc  
DDQ  
1
2
3
4
5
6
7
V
SA  
SE2  
SA  
SA ADSP  
SA ADSC  
SA  
SA  
SA  
SA  
SE3  
SA  
V
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQb  
DQb  
DQb  
V
DDQ  
DDQ  
NC  
NC  
V
DDQ  
V
NC  
SA  
V
NC  
SS  
DD  
V
SS  
DQc  
DQc  
DQc  
DQc  
DQb  
DQb  
DQb  
DQb  
DQc  
DQc  
DQc  
DQc  
DQc  
V
NC  
SE1  
G
V
DQb DQb  
DQb DQb  
SS  
SS  
SS  
SS  
SS  
SS  
8
9
V
V
V
V
V
F
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
SS  
V
V
DQb  
DQb  
SS  
DDQ  
V
DQb  
V
DDQ  
DDQ  
V
DDQ  
DQc  
G
DQc  
DQc SBc  
DQc  
ADV  
SGW  
SBb  
DQb DQb  
DQb DQb  
DQc  
NC  
H
V
NC  
DQc  
V
V
SS  
SS  
NC  
SS  
V
DD  
J
K
L
NC  
SS  
DQd  
DQd  
V
NC  
V
V
V
NC  
V
V
DDQ  
DD  
DDQ  
DD  
DQd  
DQd SBd  
DD  
DD  
V
DQa  
DQa  
DQd  
V
K
V
DQa DQa  
DQa DQa  
SS  
SS  
V
DQd  
NC  
SW  
SA1  
SA0  
SBa  
DDQ  
SS  
V
V
DDQ  
SS  
V
M
N
P
V
DQd  
DQd  
DQd  
V
V
V
V
DQa  
V
DDQ  
DQd  
DQd  
DQd  
DQd  
DDQ  
SS  
SS  
SS  
SS  
DQa  
DQa  
DQa  
DQa  
DQd  
V
DQa DQa  
DQa DQa  
SS  
SS  
DQd  
V
V
V
SS  
SS  
R
T
V
V
DDQ  
DQd  
DQd  
DQd  
DDQ  
NC  
NC  
SA  
LBO  
V
NC  
SA  
NC  
NC  
DD  
DQa  
DQa  
DQa  
NC  
NC  
SA  
NC  
SA  
NC  
SA  
NC  
NC  
NC  
U
31 3233 343536 3738 3940 414243 444546 4748 49 50  
V
V
DDQ  
DDQ  
TOP VIEW 119 BUMP PBGA  
TOP VIEW 100 PIN TQFP  
Not to Scale  
MCM69P737  
3
MOTOROLA FAST SRAM  
PBGA PIN DESCRIPTIONS  
Pin Locations  
Symbol  
Type  
Description  
4B  
ADSC  
Input  
Synchronous Address Status Controller: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
READ, WRITE, or chip deselect.  
4A  
ADSP  
Input  
Synchronous Address Status Processor: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
new READ, WRITE, or chip deselect (exception — chip deselect does  
not occur when ADSP is asserted and SE1 is high).  
4G  
ADV  
DQx  
Input  
I/O  
Synchronous Address Advance: Increments address count in  
accordance with counter type selected (linear/interleaved).  
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P  
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H  
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H  
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P  
Synchronous Data I/O: “x” refers to the byte being read or written  
(byte a, b, c, d).  
4F  
G
Input  
Asynchronous Output Enable Input:  
Low — enables output buffers (DQx pins).  
High — DQx pins are high impedance.  
4K  
3R  
K
Input  
Input  
Clock: This signal registers the address, data in, and all control signals  
except G and LBO.  
LBO  
Linear Burst Order Input: This pin must remain in steady state (this  
signal not registered or latched). It must be tied high or low.  
Low — linear burst counter (68K/PowerPC).  
High — interleaved burst counter (486/i960/Pentium).  
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,  
5C, 6C, 2R, 6R, 3T, 4T, 5T  
SA  
Input  
Input  
Synchronous Address Inputs: These inputs are registered and must  
meet setup and hold times.  
4N, 4P  
SA1, SA0  
Synchronous Address Inputs: These pins must be wired to the two  
LSBs of the address bus for proper burst operation. These inputs are  
registered and must meet setup and hold times.  
5L, 5G, 3G, 3L  
(a) (b) (c) (d)  
SBx  
SE1  
Input  
Input  
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte  
a, b, c, d). SGW overrides SBx.  
4E  
Synchronous Chip Enable: Active low to enable chip.  
Negated high — blocks ADSP or deselects chip when ADSC is  
asserted.  
2B  
6B  
4H  
SE2  
SE3  
Input  
Input  
Input  
Synchronous Chip Enable: Active high for depth expansion.  
Synchronous Chip Enable: Active low for depth expansion.  
SGW  
Synchronous Global Write: This signal writes all bytes regardless of the  
status of the SBx and SW signals. If only byte write signals SBx are  
being used, tie this pin high.  
4M  
SW  
Input  
Synchronous Write: This signal writes only those bytes that have been  
selected using the byte write SBx pins. If only byte write signals SBx  
are being used, tie this pin low.  
4C, 2J, 4J, 6J, 4R  
V
Supply Core Power Supply.  
Supply I/O Power Supply.  
Supply Ground.  
DD  
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U  
V
DDQ  
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,  
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P  
V
SS  
1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R,  
7R, 1T, 2T, 6T, 7T, 2U, 3U, 4U, 5U, 6U  
NC  
No Connection: There is no connection to the chip.  
MCM69P737  
4
MOTOROLA FAST SRAM  
TQFP PIN DESCRIPTIONS  
Pin Locations  
Symbol  
Type  
Description  
85  
ADSC  
Input  
Synchronous Address Status Controller: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
READ, WRITE, or chip deselect.  
84  
ADSP  
Input  
Synchronous Address Status Processor: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
new READ, WRITE, or chip deselect (exception — chip deselect does  
not occur when ADSP is asserted and SE1 is high).  
83  
ADV  
DQx  
Input  
I/O  
Synchronous Address Advance: Increments address count in  
accordance with counter type selected (linear/interleaved).  
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63  
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80  
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13  
Synchronous Data I/O: “x” refers to the byte being read or written  
(byte a, b, c, d).  
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30  
86  
G
Input  
Asynchronous Output Enable Input:  
Low — enables output buffers (DQx pins).  
High — DQx pins are high impedance.  
89  
31  
K
Input  
Input  
Clock: This signal registers the address, data in, and all control signals  
except G and LBO.  
LBO  
Linear Burst Order Input: This pin must remain in steady state (this  
signal not registered or latched). It must be tied high or low.  
Low — linear burst counter (68K/PowerPC).  
High — interleaved burst counter (486/i960/Pentium).  
32, 33, 34, 35, 44, 45, 46,  
47, 48, 49, 50, 81, 82, 99, 100  
SA  
Input  
Input  
Synchronous Address Inputs: These inputs are registered and must  
meet setup and hold times.  
36, 37  
SA1, SA0  
Synchronous Address Inputs: these pins must be wired to the two LSBs  
of the address bus for proper burst operation. These inputs are  
registered and must meet setup and hold times.  
93, 94, 95, 96  
(a) (b) (c) (d)  
SBx  
SE1  
Input  
Input  
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte  
a, b, c, d). SGW overrides SBx.  
98  
Synchronous Chip Enable: Active low to enable chip.  
Negated high — blocks ADSP or deselects chip when ADSC is  
asserted.  
97  
92  
88  
SE2  
SE3  
Input  
Input  
Input  
Synchronous Chip Enable: Active high for depth expansion.  
Synchronous Chip Enable: Active low for depth expansion.  
SGW  
Synchronous Global Write: This signal writes all bytes regardless of the  
status of the SBx and SW signals. If only byte write signals SBx are  
being used, tie this pin high.  
87  
SW  
Input  
Synchronous Write: This signal writes only those bytes that have been  
selected using the byte write SBx pins. If only byte write signals SBx  
are being used, tie this pin low.  
15, 41, 65, 91  
V
Supply Core Power Supply.  
Supply I/O Power Supply.  
Supply Ground.  
DD  
4, 11, 20, 27, 54, 61, 70, 77  
V
DDQ  
5, 10, 17, 21, 26, 40,  
55, 60, 67, 71, 76, 90  
V
SS  
14, 16, 38, 39, 42, 43, 64, 66  
NC  
No Connection: There is no connection to the chip.  
MCM69P737  
5
MOTOROLA FAST SRAM  
TRUTH TABLE (See Notes 1 Through 5)  
Address  
Used  
3
2, 4  
Next Cycle  
Deselect  
SE1  
1
SE2  
X
X
0
SE3  
X
1
ADSP  
ADSC  
ADV  
X
X
X
X
X
X
X
0
G
DQx  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
DQ  
Write  
None  
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
1
X
1
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
Deselect  
None  
0
X
X
X
X
X
X
1
Deselect  
None  
0
X
1
Deselect  
None  
X
X
0
X
0
Deselect  
None  
X
0
5
Begin Read  
Begin Read  
Continue Read  
Continue Read  
Continue Read  
Continue Read  
Suspend Read  
Suspend Read  
Suspend Read  
Suspend Read  
Begin Write  
External  
External  
Next  
1
X
5
0
1
0
READ  
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
READ  
READ  
READ  
READ  
READ  
READ  
READ  
READ  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
Next  
0
0
Next  
0
1
High–Z  
DQ  
Next  
1
0
0
Current  
Current  
Current  
Current  
External  
Next  
X
X
1
1
1
High–Z  
DQ  
1
0
1
1
High–Z  
DQ  
1
1
0
0
X
0
X
X
X
X
X
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
Continue Write  
Continue Write  
Suspend Write  
Suspend Write  
NOTES:  
X
1
X
X
X
X
X
X
X
X
Next  
0
Current  
Current  
X
1
1
1
1. X = Don’t Care. 1 = logic high. 0 = logic low.  
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.  
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t  
) following G going low.  
GLQX  
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must  
also remain negated at the completion of the write cycle to ensure proper write data hold times.  
5. This read assumes the RAM was previously deselected.  
LINEAR BURST ADDRESS TABLE (LBO = V  
)
SS  
1st Address (External)  
X . . . X00  
2nd Address (Internal)  
X . . . X01  
3rd Address (Internal)  
X . . . X10  
4th Address (Internal)  
X . . . X11  
X . . . X01  
X . . . X10  
X . . . X11  
X . . . X00  
X . . . X10  
X . . . X11  
X . . . X00  
X . . . X01  
X . . . X11  
X . . . X00  
X . . . X01  
X . . . X10  
INTERLEAVED BURST ADDRESS TABLE (LBO = V  
)
DD  
2nd Address (Internal)  
1st Address (External)  
X . . . X00  
3rd Address (Internal)  
X . . . X10  
4th Address (Internal)  
X . . . X11  
X . . . X01  
X . . . X00  
X . . . X11  
X . . . X10  
X . . . X01  
X . . . X11  
X . . . X10  
X . . . X10  
X . . . X00  
X . . . X01  
X . . . X11  
X . . . X01  
X . . . X00  
WRITE TRUTH TABLE  
Cycle Type  
Read  
SGW  
SW  
H
L
SBa  
X
SBb  
SBc  
X
SBd  
X
H
H
H
H
H
H
H
L
X
H
H
L
Read  
H
H
H
Write Byte a  
Write Byte b  
Write Byte c  
Write Byte d  
Write All Bytes  
Write All Bytes  
L
L
H
H
L
H
H
H
L
H
H
H
L
L
H
L
H
H
L
L
L
L
L
X
X
X
X
X
MCM69P737  
6
MOTOROLA FAST SRAM  
ABSOLUTE MAXIMUM RATINGS (See Note 1)  
This device contains circuitry to protect the  
inputs against damage due to high static volt-  
ages or electric fields; however, it is advised  
that normal precautions be taken to avoid  
application of any voltage higher than maxi-  
mum rated voltages to this high–impedance  
circuit.  
Rating  
Power Supply Voltage  
I/O Supply Voltage  
Symbol  
Value  
Unit Notes  
V
DD  
V
– 0.5 to + 4.6  
V
SS  
V
DDQ  
V
– 0.5 to V  
V
V
2
2
SS  
DD  
Input Voltage Relative to V  
Any Pin Except V  
DD  
for  
V , V  
in out  
V
V
– 0.5 to  
SS  
SS  
+ 0.5  
DD  
Input Voltage (Three–State I/O)  
V
IT  
V
V
– 0.5 to  
+ 0.5  
V
2
SS  
DDQ  
Output Current (per I/O)  
Package Power Dissipation  
Ambient Temperature  
Die Temperature  
I
± 20  
mA  
W
out  
P
1.6  
0 to 70  
110  
3
3
D
T
°C  
°C  
°C  
°C  
A
T
J
Temperature Under Bias  
Storage Temperature  
NOTES:  
T
bias  
– 10 to 85  
T
– 55 to 125  
stg  
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are  
exceeded. Functional operation should be restricted to RECOMMENDED OPER-  
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended  
periods of time could affect device reliability.  
2. This is a steady–state DC parameter that is in effect after the power supply has  
achieved its nominal operating level. Power sequencing is not necessary.  
3. Power dissipation capability is dependent upon package characteristics and use  
environment. See Package Thermal Characteristics.  
PACKAGE THERMAL CHARACTERISTICS — PBGA  
Rating  
Symbol  
Max  
Unit  
Notes  
Junction to Ambient (@ 200 lfm)  
Single–Layer Board  
Four–Layer Board  
R
38  
22  
°C/W  
1, 2  
θJA  
Junction to Board (Bottom)  
Junction to Case (Top)  
NOTES:  
R
R
14  
5
°C/W  
°C/W  
3
4
θJB  
θJC  
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient  
temperature, air flow, board population, and board thermal resistance.  
2. Per SEMI G38–87.  
3. Indicates the average thermal resistance between the die and the printed circuit board.  
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).  
PACKAGE THERMAL CHARACTERISTICS — TQFP  
Rating  
Symbol  
Max  
Unit  
Notes  
Junction to Ambient (@ 200 lfm)  
Single–Layer Board  
Four–Layer Board  
R
40  
25  
°C/W  
1, 2  
θJA  
Junction to Board (Bottom)  
Junction to Case (Top)  
NOTES:  
R
R
17  
9
°C/W  
°C/W  
3
4
θJB  
θJC  
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient  
temperature, air flow, board population, and board thermal resistance.  
2. Per SEMI G38–87.  
3. Indicates the average thermal resistance between the die and the printed circuit board.  
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).  
MCM69P737  
7
MOTOROLA FAST SRAM  
DC OPERATING CONDITIONS AND CHARACTERISTICS  
(V  
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)  
DD  
A
RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply (Voltages Referenced to V  
SS  
= 0 V)  
Typ  
3.3  
3.3  
2.5  
Parameter  
Symbol  
Min  
3.135  
3.135  
2.375  
– 0.3  
1.7  
Max  
3.465  
3.6  
Unit  
V
Supply Voltage  
MCM69P737–3.0, –3.2  
V
DD  
MCM69P737–3.5, –3.8, –4  
V
I/O Supply Voltage  
V
DDQ  
2.9  
V
Input Low Voltage  
V
IL  
0.7  
V
Input High Voltage  
V
IH  
V
DD  
+ 0.3  
V
Input High Voltage (I/O Pins)  
V
IH2  
1.7  
V
DDQ  
+ 0.3  
V
RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply (Voltages Referenced to V  
SS  
= 0 V)  
Typ  
3.3  
3.3  
3.3  
Parameter  
Symbol  
Min  
3.135  
3.135  
3.135  
– 0.5  
2
Max  
Unit  
V
Supply Voltage  
MCM69P737–3.0, –3.2  
V
DD  
3.465  
3.6  
MCM69P737–3.5, –3.8, –4  
V
I/O Supply Voltage  
V
DDQ  
V
DD  
V
Input Low Voltage  
V
IL  
0.8  
V
Input High Voltage  
V
IH  
V
DD  
+ 0.5  
V
Input High Voltage (I/O Pins)  
V
IH2  
2
V
DDQ  
+ 0.5  
V
V
IH  
V
SS  
V
– 1.0 V  
SS  
20% t  
(MIN)  
KHKH  
Figure 1. Undershoot Voltage  
MCM69P737  
8
MOTOROLA FAST SRAM  
DC CHARACTERISTICS AND SUPPLY CURRENTS  
Parameter  
Symbol  
Min  
Typ  
Max  
± 1  
Unit  
µA  
Notes  
Input Leakage Current (0 V V V  
in  
)
I
lkg(I)  
DD  
Output Leakage Current (0 V V V  
)
I
lkg(O)  
± 1  
µA  
in  
DDQ  
AC Supply Current (Device Selected,  
All Outputs Open, Freq = Max),  
MCM69P737–3.0  
MCM69P737–3.2  
MCM69P737–3.5  
MCM69P737–3.8  
MCM69P737–4  
I
475  
450  
425  
400  
375  
mA  
1, 2, 3  
DDA  
Includes V  
Only  
DD  
CMOS Standby Supply Current (Device Deselected, Freq = 0,  
= Max, All Inputs Static at CMOS Levels)  
I
45  
mA  
mA  
mA  
4, 5  
4, 6  
4, 5  
SB2  
SB3  
SB4  
V
DD  
TTL Standby Supply Current (Device Deselected, Freq = 0,  
= Max, All Inputs Static at TTL Levels)  
I
50  
V
DD  
Clock Running (Device Deselected,  
Freq = Max, V = Max,  
MCM69P737–3.0  
MCM69P737–3.2  
MCM69P737–3.5  
MCM69P737–3.8  
MCM69P737–4  
I
210  
200  
190  
180  
165  
DD  
All Inputs Toggling at CMOS Levels)  
Static Clock Running (Device Deselected, Freq = Max,  
= Max, All Inputs Static at TTL Levels)  
I
95  
mA  
4, 6  
SB5  
V
DD  
Output Low Voltage (I  
= 2 mA) V  
= 2.5 V  
V
1.7  
0.7  
V
V
V
V
OL  
DDQ  
OL  
Output High Voltage (I  
= – 2 mA) V  
= 2.5 V  
V
OH  
OL  
OL  
DDQ  
Output Low Voltage (I  
= 8 mA) V  
= 3.3 V  
V
OL2  
0.4  
DDQ  
Output High Voltage (I  
= – 4 mA) V  
= 3.3 V  
DDQ  
V
OH2  
2.4  
OL  
NOTES:  
1. Reference AC Operating Conditions and Characteristics for input and timing.  
2. All addresses transition simultaneously low (LSB) then high (MSB).  
3. Data states are all zero.  
4. Device is deselected as defined by the Truth Table.  
5. CMOS levels for I/Os are V V  
6. TTL levels for I/Os are V V or V  
IT IL  
+ 0.2 V or V  
. TTL levels for other inputs are V V or V .  
IH2 in IL  
– 0.2 V. CMOS levels for other inputs are V V  
in  
+ 0.2 V or V – 0.2 V.  
DD  
IT  
SS  
DDQ  
SS  
IH  
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)  
A
Parameter  
Symbol  
Min  
Typ  
4
Max  
5
Unit  
pF  
Input Capacitance  
C
in  
Input/Output Capacitance  
C
7
8
pF  
I/O  
MCM69P737  
9
MOTOROLA FAST SRAM  
AC OPERATING CONDITIONS AND CHARACTERISTICS  
(V  
= 3.3 v + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)  
DD  
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V  
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V  
Input Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20 to 80%)  
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V  
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted  
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)  
–3.0  
200 MHz  
–3.2  
183 MHz  
–3.5  
166 MHz  
–3.8  
150 MHz  
–4  
133 MHz  
Parameter  
Cycle Time  
Symbol  
Unit  
ns  
Notes  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
t
5
2
3
5.5  
2.2  
2.2  
6
6.7  
2.6  
2.6  
7.5  
3
KHKH  
Clock High Pulse Width  
Clock Low Pulse Width  
Clock Access Time  
t
2.4  
2.4  
ns  
4
4
KHKL  
KLKH  
KHQV  
t
2
3
ns  
t
3.2  
3.2  
3.5  
3.5  
3.8  
3.5  
4
ns  
Output Enable to Output  
Valid  
t
3
3.8  
ns  
GLQV  
Clock High to Output Active  
t
t
0
0
0
0
0
ns  
ns  
5, 6  
5
KHQX1  
Clock High to Output  
Change  
1.5  
1.5  
1.5  
1.5  
1.5  
KHQX2  
Output Enable to Output  
Active  
t
0
0
0
0
0
ns  
5, 6  
GLQX  
Output Disable to Q High–Z  
Clock High to Q High–Z  
t
3
3.2  
3.5  
3.5  
3.5  
3.5  
3.5  
3.8  
3.5  
ns  
ns  
ns  
5, 6  
5, 6  
GHQZ  
t
1.5  
1.2  
3.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
KHQZ  
ADKH  
Setup Times:  
Address  
t
ADSP, ADSC, ADV  
Data In  
t
ADSKH  
t
DVKH  
Write  
Chip Enable  
t
WVKH  
t
EVKH  
Hold Times:  
Address  
ADSP, ADSC, ADV  
Data In  
t
0.4  
0.5  
0.5  
0.5  
0.5  
ns  
KHAX  
t
KHADSX  
t
KHDX  
Write  
Chip Enable  
t
KHWX  
t
KHEX  
NOTES:  
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP  
or ADSC is asserted.  
2. All read and write cycle timings are referenced from K or G.  
3. V  
= 3.3 V ± 5% for MCM69P737–3.0 and MCM69P737–3.2 devices only.  
DD  
4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between  
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at V /2. In some  
DDQ  
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is  
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.  
5. This parameter is sampled and not 100% tested.  
6. Measured at ± 200 mV from steady state.  
OUTPUT  
Z
= 50 Ω  
0
R
= 50 Ω  
L
1.25 V  
Figure 2. AC Test Load  
MCM69P737  
10  
MOTOROLA FAST SRAM  
5
4
3
2
OUTPUT  
C
L
1
0
0
20  
40  
60  
80  
100  
LUMPED CAPACITANCE, C (pF)  
L
Figure 3. Lumped Capacitive Load and Typical Derating Curve  
OUTPUT LOAD  
OUTPUT  
TEST POINT  
BUFFER  
UNLOADED RISE AND FALL TIME MEASUREMENT  
2.0  
2.0  
INPUT  
0.5  
0.5  
WAVEFORM  
2.0  
2.0  
OUTPUT  
0.5  
0.5  
WAVEFORM  
t
t
f
r
NOTES:  
1. Input waveform has a slew rate of 1 V/ns.  
2. Rise time is measured from 0.5 to 2.0 V unloaded.  
3. Fall time is measured from 2.0 to 0.5 V unloaded.  
Figure 4. Unloaded Rise and Fall Time Characterization  
MCM69P737  
11  
MOTOROLA FAST SRAM  
2.9  
2.5  
PULL–UP  
I (mA) MIN  
2.3  
2.1  
VOLTAGE (V)  
I (mA) MAX  
– 0.5  
0
– 38  
– 38  
– 38  
– 26  
– 105  
– 105  
– 105  
– 83  
0.8  
1.25  
1.25  
0.8  
1.5  
2.3  
2.7  
2.9  
– 20  
– 70  
– 30  
– 10  
0
0
0
0
0
0
– 38  
CURRENT (mA)  
– 105  
(a) Pull–Up for 2.5 V I/O Supply  
3.6  
3.135  
2.8  
PULL–UP  
I (mA) MIN  
VOLTAGE (V)  
I (mA) MAX  
– 0.5  
0
– 50  
– 50  
– 50  
– 46  
– 150  
– 150  
– 150  
– 130  
1.65  
1.4  
1.4  
1.65  
2.0  
3.135  
3.6  
– 35  
0
– 101  
– 25  
0
0
0
0
– 50  
– 100  
– 150  
CURRENT (mA)  
(b) Pull–Up for 3.3 V I/O Supply  
V
DD  
PULL–DOWN  
VOLTAGE (V)  
I (mA) MIN  
I (mA) MAX  
– 0.5  
0
0
0
0
0
1.6  
0.4  
0.8  
10  
20  
20  
40  
1.25  
1.25  
1.6  
31  
40  
40  
63  
80  
80  
2.8  
0.3  
0
3.2  
3.4  
40  
40  
80  
80  
0
40  
CURRENT (mA)  
80  
(c) Pull–Down  
Figure 5. Typical Output Buffer Characteristics  
MCM69P737  
12  
MOTOROLA FAST SRAM  
MCM69P737  
13  
MOTOROLA FAST SRAM  
APPLICATION INFORMATION  
STOP CLOCK OPERATION  
clock pulse width and edge rates must be guaranteed when  
starting and stopping the clocks.  
To achieve the lowest power operation for all three stop  
clock modes, stop read, stop write, and stop deselect:  
In the stop clock mode of operation, the SRAM will hold all  
state and data values even though the clock is not running  
(full static operation). The SRAM design allows the clock to  
start with ADSP and ADSC, and stops the clock after the last  
write data is latched, or the last read data is driven out.  
When starting and stopping the clock, the AC clock timing  
and parametrics must be strictly maintained. For example,  
Force the clock to a low state.  
Force the control signals to an inactive state (this  
guarantees any potential source of noise on the clock  
input will not start an unplanned on activity).  
Force the address inputs to a low state.  
STOP CLOCK WITH READ TIMING  
K
ADSP  
ADDRESS  
A1  
A2  
ADV  
DQx  
Q(A1)  
Q(A1+1)  
Q(A2)  
ADSP  
(INITIATES  
BURST READ)  
CLOCK STOP  
(CONTINUE  
BURST READ)  
WAKE UP ADSP  
(INITIATES BURST READ)  
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (V ).  
IL  
Best results are obtained if V < 0.2 V.  
IL  
MCM69P737  
14  
MOTOROLA FAST SRAM  
STOP CLOCK WITH WRITE TIMING  
K
ADSC  
ADDRESS  
WRITE  
ADV  
A1  
A2  
DATA IN  
DQx  
D(A1)  
D(A1+1)  
V
OR V FIXED (SEE NOTE)  
IL  
D(A2)  
IH  
HIGH–Z  
ADSC  
(INITIATES  
CLOCK STOP  
(CONTINUE  
WAKE UP ADSC  
(INITIATES BURST WRITE)  
BURST WRITE)  
BURST WRITE)  
NOTE: While the clock is stopped, DATA IN must be fixed in a high (V ) or low (V ) state to reduce the DC current of the  
IH  
IL  
input buffers. For lowest power operation, all data and address lines should be held in a low (V ) state and control  
IL  
lines held in an inactive state.  
MCM69P737  
15  
MOTOROLA FAST SRAM  
STOP CLOCK WITH DESELECT OPERATION TIMING  
K
ADSC  
SE1  
DATA IN  
V
OR V FIXED (SEE NOTE)  
IL  
IH  
HIGH–Z  
DQx  
DATA  
DATA  
CONTINUE  
BURST READ  
CLOCK STOP  
(DESELECTED)  
WAKE UP  
(DESELECTED)  
NOTE: While the clock is stopped, DATA IN must be fixed in a high (V ) or low (V ) state to reduce the DC current of the  
IH  
IL  
input buffers. For lowest power operation, all data and address lines should be held in a low (V ) state and control  
IL  
lines held in an inactive state.  
MCM69P737  
16  
MOTOROLA FAST SRAM  
NON–BURST SYNCHRONOUS OPERATION  
CONTROL PIN TIE VALUES EXAMPLE (H V , L V  
IH  
)
IL  
Although this BurstRAM has been designed for PowerPC–  
based and other high end MPU–based systems, these  
SRAMs can be used in other high speed L2 cache or  
memory applications that do not require the burst address  
feature. Most L2 caches designed with a synchronous inter-  
face can make use of the MCM69P737. The burst counter  
feature of the BurstRAM can be disabled, and the SRAM can  
be configured to act upon a continuous stream of addresses.  
See Figure 6.  
Non–Burst  
ADSP ADSC ADV SE1 SE2 LBO  
Sync Non–Burst,  
Pipelined SRAM  
H
L
H
L
H
X
NOTE: Although X is specified in the table as a don’t care, the pin  
must be tied either high or low.  
K
ADDR  
SE3  
A
B
C
D
E
F
G
H
W
G
DQ  
Q(A)  
Q(B)  
Q(C)  
Q(D)  
D(E)  
D(F)  
D(G)  
D(H)  
READS  
WRITES  
Figure 6. Example Configuration as Non–Burst Synchronous SRAM  
ORDERING INFORMATION  
(Order by Full Part Number)  
MCM  
69P737  
XX  
X
X
Motorola Memory Prefix  
Part Number  
Blank = Trays, R = Tape and Reel  
Speed (3.0 = 3 ns, 3.2 = 3.2 ns,  
3.5 = 3.5 ns, 3.8 = 3.8 ns, and 4 = 4 ns)  
Package (ZP = PBGA, TQ = TQFP)  
Full Part Numbers — MCM69P737ZP3.0 MCM69P737ZP3.2  
MCM69P737ZP3.0R MCM69P737ZP3.2R MCM69P737ZP3.5R MCM69P737ZP3.8R MCM69P737ZP4R  
MCM69P737TQ3.0 MCM69P737TQ3.2 MCM69P737TQ3.5 MCM69P737TQ3.8 MCM69P737TQ4  
MCM69P737TQ3.0R MCM69P737TQ3.2R MCM69P737TQ3.5R MCM69P737TQ3.8R MCM69P737TQ4R  
MCM69P737ZP3.5  
MCM69P737ZP3.8  
MCM69P737ZP4  
MCM69P737  
17  
MOTOROLA FAST SRAM  
PACKAGE DIMENSIONS  
ZP PACKAGE  
7 x 17 BUMP PBGA  
CASE 999–02  
0.20  
4X  
119X  
b
B
D
M
0.3  
A B C  
E
C
NOTES:  
M
0.15  
A
1. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
7
6 5 4 3 2 1  
A
B
C
D
E
F
G
H
J
2. ALL DIMENSIONS IN MILLIMETERS.  
3. DIMENSION b IS THE MAXIMUM SOLDER BALL  
DIAMETER MEASURED PARALLEL TO DATUM A.  
4. DATUM A, THE SEATING PLANE, IS DEFINED BY  
THE SPHERICAL CROWNS OF THE SOLDER  
BALLS.  
D1  
D2  
MILLIMETERS  
K
L
DIM  
A
A1  
A2  
A3  
D
D1  
D2  
E
E1  
E2  
b
MIN  
–––  
0.50  
1.30  
0.80  
MAX  
2.40  
0.70  
1.70  
1.00  
M
N
P
R
T
16X e  
U
22.00 BSC  
20.32 BSC  
19.40 19.60  
14.00 BSC  
7.62 BSC  
6X  
e
E2  
E1  
BOTTOM VIEW  
TOP VIEW  
11.90  
0.60  
1.27 BSC  
12.10  
0.90  
e
0.25  
A
A
A3  
A2  
0.35  
0.20  
A
A
SEATING  
PLANE  
SIDE VIEW  
A1  
A
MCM69P737  
18  
MOTOROLA FAST SRAM  
TQ PACKAGE  
TQFP  
CASE 983A–01  
4X  
80  
e
0.20 (0.008)  
H
A–B  
D
2X 30 TIPS  
0.20 (0.008)  
e/2  
C
A–B  
D
–D–  
51  
B
B
50  
81  
–X–  
E/2  
X=A, B, OR D  
–A–  
–B–  
VIEW Y  
E1  
E
BASE  
METAL  
PLATING  
b1  
E1/2  
31  
100  
c1  
c
1
30  
b
D1/2  
D/2  
D1  
M
S
S
0.13 (0.005)  
C
A–B  
D
D
SECTION B–B  
2X 20 TIPS  
0.20 (0.008)  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
C
A–B  
D
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF  
LEAD AND IS COINCIDENT WITH THE LEAD  
WHERE THE LEAD EXITS THE PLASTIC BODY AT  
THE BOTTOM OF THE PARTING LINE.  
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED  
AT DATUM PLANE –H–.  
A
2
3
0.10 (0.004)  
C
–H–  
5. DIMENSIONS D AND E TO BE DETERMINED AT  
SEATING PLANE –C–.  
–C–  
SEATING  
PLANE  
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD  
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25  
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO  
INCLUDE MOLD MISMATCH AND ARE  
DETERMINED AT DATUM PLANE –H–.  
7. DIMENSION b DOES NOT INCLUDE DAMBAR  
PROTRUSION. DAMBAR PROTRUSION SHALL  
NOT CAUSE THE b DIMENSION TO EXCEED 0.45  
(0.018).  
VIEW AB  
S
0.05 (0.002)  
S
1
MILLIMETERS  
INCHES  
MIN  
0.25 (0.010)  
DIM  
A
A1  
A2  
b
b1  
c
c1  
D
MIN  
–––  
MAX  
1.60  
0.15  
1.45  
0.38  
0.33  
0.20  
0.16  
MAX  
0.063  
0.006  
0.057  
0.015  
0.013  
0.008  
0.006  
GAGE PLANE  
R2  
–––  
0.002  
0.053  
0.009  
0.009  
0.004  
0.004  
A2  
0.05  
1.35  
0.22  
0.22  
0.09  
0.09  
L2  
L
R1  
A1  
22.00 BSC  
0.866 BSC  
D1  
E
E1  
e
20.00 BSC  
16.00 BSC  
14.00 BSC  
0.65 BSC  
0.787 BSC  
0.630 BSC  
0.551 BSC  
0.026 BSC  
L1  
VIEW AB  
L
0.45  
1.00 REF  
0.50 REF  
0.75  
0.018  
0.039 REF  
0.020 REF  
0.030  
L1  
L2  
S
R1  
R2  
0.20  
–––  
–––  
0.20  
7
0.008  
–––  
–––  
0.008  
7
0.08  
0.08  
0
0.003  
0.003  
0
1
2
3
0
11  
11  
–––  
13  
13  
0
11  
11  
–––  
13  
13  
MCM69P737  
19  
MOTOROLA FAST SRAM  
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and  
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola  
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,includingTypicals”  
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of  
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other  
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury  
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola  
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees  
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Motorola was negligent regarding the design or manufacture of the part. Motorola and  
Opportunity/Affirmative Action Employer.  
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal  
Mfax is a trademark of Motorola, Inc.  
How to reach us:  
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;  
JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141,  
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488  
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,  
Motorola Fax Back System  
– US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298  
– http://sps.motorola.com/mfax/  
HOME PAGE: http://motorola.com/sps/  
CUSTOMER FOCUS CENTER: 1-800-521-6274  
MCM69P737/D  
配单直通车
MCM69P737TQ3.2产品参数
型号:MCM69P737TQ3.2
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:MOTOROLA INC
零件包装代码:QFP
包装说明:LQFP,
针数:100
Reach Compliance Code:unknown
ECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41
风险等级:5.51
最长访问时间:3.2 ns
JESD-30 代码:R-PQFP-G100
JESD-609代码:e0
长度:20 mm
内存密度:4718592 bit
内存集成电路类型:CACHE SRAM
内存宽度:36
功能数量:1
端子数量:100
字数:131072 words
字数代码:128000
工作模式:SYNCHRONOUS
最高工作温度:70 °C
最低工作温度:
组织:128KX36
封装主体材料:PLASTIC/EPOXY
封装代码:LQFP
封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified
座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mm
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!