全新 原装 现货 热卖 AM3352BZCZ60
日期:2018-6-6Features 1234567 – 32KB of L1 Data Cache with Single Error- 8226; Highlights Detection (parity) – Up to 1-GHz Sitara™ ARM® Cortex™-A8 32‑Bit RISC Microprocessor – 256KB of L2 Cache with Error Correcting Code (ECC) 8226; NEON™ SIMD Coprocessor 8226; 32KB of L1 Instruction and 32KB Data – 176KB of On-Chip Boot ROM Cache with Single-Error Detection (parity) – 64KB of Dedicated RAM 8226; 256KB of L2 Cache with Error Correcting – Emulation and Debug Code (ECC) 8226; JTAG – mDDR(LPDDR), DDR2, DDR3, DDR3L – Interrupt Controller (up to 128 interrupt Support requests) – General-Purpose Memory Support (NAND, 8226; On-Chip Memory (Shared L3 RAM) NOR, SRAM) Supporting Up to 16-bit ECC – 64 KB of General-Purpose On-Chip Memory – SGX530 3D Graphics Engine Controller (OCMC) RAM – LCD and Touchscreen Controller – Accessible to all Masters – Programmable Real-Time Unit and Industrial – Supports Retention for Fast Wake-Up Communication Subsystem (PRU-ICSS) 8226; External Memory Interfaces (EMIF) – Real-Time Clock (RTC) – mDDR(LPDDR), DDR2, DDR3, DDR3L – Up to Two USB 2.0 High-Speed OTG Ports Controller: with Integrated PHY 8226; mDDR: 200-MHz Clock (400-MHz Data – 10, 100, 1000 Ethernet Switch Supporting Up Rate) to Two Ports 8226; DDR2: 266-MHz Clock (532-MHz Data – Serial Interfaces Including: Rate) 8226; Two Controller Area Network Ports (CAN) 8226; DDR3: 400-MHz Clock (800-MHz Data Rate) 8226; Six UARTs, Two McASPs, Two McSPI, and Three I2C Ports 8226; DDR3L: 400-MHz Clock (800-MHz Data – 12-Bit Successive Approximation Register Rate) (SAR) ADC 8226; 16-Bit Data Bus – Up to Three 32-Bit Enhanced Capture 8226; 1 GB of Total Addressable Space Modules (eCAP) 8226; Supports One x16 or Two x8 Memory – Up to Three Enhanced High-Resolution PWM Device Configurations Modules (eHRPWM) – General-Purpose Memory Controller (GPMC) – Crypto Hardware Accelerators (AES, SHA, 8226; Flexible 8-Bit and 16-Bit Asynchronous PKA, RNG) Memory Interface with Up to seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM) 8226; MPU Subsystem 8226; Uses BCH Code to Support 4-Bit, 8-Bit, or – Up to 1-GHz ARM® Cortex™-A8 32-Bit RISC 16-Bit ECC Microprocessor 8226; Uses Hamming Code to Support 1-Bit – NEON™ SIMD Coprocessor ECC – 32KB of L1 – Error Locator Module (ELM) Instruction Cache with SingleError Detection (parity) 8226; Used in Conjunction with the GPMC to Locate Addresses of Data Errors from Week) and Time (Hours-Minutes-Seconds) Syndrome Polynomials Generated Using Information a BCH Algorithm – Internal 32.768-kHz Oscillator, RTC Logic 8226; Supports 4-Bit, 8-Bit, and 16-Bit per 512- and 1.1-V Internal LDO byte Block Error Location Based on BCH – Independent Power-on-Reset Algorithms (RTC_PWRONRSTn) Input 8226; Programmable Real-Time Unit and Industrial – Dedicated Input Pin (EXT_WAKEUP) for Communication Subsystem (PRU-ICSS) External Wake Events – Supports protocols such as EtherCAT® , – Programmable Alarm Can be Used to PROFIBUS, PROFINET, EtherNet/IP™, and Generate Internal Interrupts to the PRCM (for more Wake Up) or Cortex-A8 (for Event – Peripherals Inside the PRU-ICSS Notification) 8226; One UART Port with Flow Control Pins, – Programmable Alarm Can be Used with Supports Up to 12 Mbps External Output (PMIC_POWER_EN) to 8226; Two MII Ethernet Ports that Support Enable the Power Management IC to Restore Industrial Ethernet, such as EtherCAT Non-RTC Power Domains 8226; One MDIO Port 8226; Peripherals 8226; One Enhanced Capture (eCAP) Module – Up to Two USB 2.0 High-Speed OTG Ports with Integrated PHY 8226; Power Reset and Clock Management (PRCM) Module – Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps) – Controls the entry and Exit of Stand-By and Deep-Sleep Modes 8226; Integrated Switch – Responsible for Sleep Sequencing, Power 8226; Each MAC Supports MII, RMII, RGMII and Domain Switch-Off Sequencing, Wake-Up MDIO Interfaces Sequencing and Power Domain Switch-On 8226; Ethernet MACs and Switch Can Operate Sequencing Independent of Other Functions – Clocks 8226; IEEE 1588v2 Precision Time Protocol (PTP) 8226; Integrated 15-35 MHz High-Frequency Oscillator Used to Generate a Reference – Up to Two Controller-Area Network (CAN) Clock for Various System and Peripheral Ports Clocks 8226; Supports CAN Version 2 Parts A and B 8226; Supports Individual Clock Enable and – Up to Two Multichannel Audio Serial Ports Disable Control for Subsystems and (McASP) Peripherals to Facilitate Reduced Power 8226; Transmit and Receive Clocks Up to 50 Consumption MHz 8226; Five ADPLLs to Generate System Clocks 8226; Up to Four Serial Data Pins per McASP (MPU Subsystem, DDR Interface, USB Port with Independent TX and RX Clocks and Peripherals [MMC and SD, UART, 8226; Supports Time Division Multiplexing SPI, I2C], L3, L4, Ethernet, GFX [SGX530], (TDM), Inter-IC Sound (I2S), and similar LCD Pixel Clock) Formats – Power 8226; Supports Digital Audio Interface 8226; Two Non-Switchable Power Domains Transmission (SPDIF, IEC60958-1, and (Real-Time Clock [RTC], Wake-Up Logic AES-3 Formats) [WAKE-UP]) 8226; FIFO Buffers for Transmit and Receive 8226; Three Switchable Power Domains (MPU (256 bytes) Subsystem [MPU], SGX530 [GFX], – Up to Six UARTs Peripherals and Infrastructure [PER]) 8226; All UARTs Support IrDA and CIR Modes 8226; Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die 8226; All UARTs Support RTS and CTS Flow Control Temperature, Process Variation and Performance 8226; UART1 Supports Full Modem control (Adaptive Voltage Scaling [AVS]) – Up to Two Master and Slave McSPI Serial 8226; Dynamic Voltage Frequency Scaling Interfaces (DVFS) 8226; Up to Two Chip Selects 8226; Real-Time Clock (RTC) 8226; Up to 48 MHz – Real-Time Date (Day-Month-Year-Day of – Up to Three MMC, SD, and SDIO Port8226; 1-Bit, 4-Bit and 8-Bit MMC, SD, and SDIO a Firmware Timer Modes 8226; 512-Word Deep Internal FIFO 8226; MMCSD0 has dedicated Power Rail for 8226; Supported Display Types: 1.8-V or 3.3-V Operation – Character Displays - Uses LCD 8226; Up to 48-MHz Data Transfer Rate Interface Display Driver (LIDD) 8226; Supports Card Detect and Write Protect Controller to Program these Displays 8226; Complies with MMC4.3 and SD and SDIO – Passive Matrix LCD Displays - Uses 2.0 Specifications LCD Raster Display Controller to – Up Provide Timing and Data for Constant to Three I2C Master and Slave Interfaces Graphics Refresh to a Passive Display 8226; Standard Mode (up to 100 kHz) – Active Matrix LCD Displays - Uses 8226; Fast Mode (up to 400 kHz) External Frame Buffer Space and the – Up to Four Banks of General-Purpose IO Internal DMA Engine to Drive (GPIO) Streaming Data to the Panel 8226; 32 GPIOs per Bank (Multiplexed with – 12-Bit Successive Approximation Register Other Functional Pins) (SAR) ADC 8226; GPIOs Can be Used as Interrupt Inputs 8226; 200K Samples per Second (Up to Two Interrupt Inputs per Bank) 8226; Input Can be Selected from any of the – Up to Three External DMA Event Inputs That Eight Analog Inputs Multiplexed Through Can Also be Used as Interrupt Inputs an 8:1 analog Switch – Eight 32-Bit General-Purpose Timers 8226; Can be Configured to Operate as a 4-wire, 8226; DMTIMER1 is a 1-ms Timer Used for 5-wire, or 8-wire Resistive Touch Screen Operating System (OS) Ticks Controller (TSC) Interface 8226; DMTIMER4 - DMTIMER7 are Pinned Out – Up to Three 32-Bit Enhanced Capture – One Watchdog Timer Modules (eCAP) – SGX530 3D Graphics Engine 8226; Configurable as Three Capture Inputs or 8226; Tile-Based Architecture Delivering Up to Three Auxiliary PWM Outputs 20 Million Polygons per second – Up to Three Enhanced High-Resolution PWM 8226; Universal Scalable Shader Engine is a Modules (eHRPWM) Multi-Threaded Engine Incorporating 8226; Dedicated 16-Bit Time-Base Counter with Pixel and Vertex Shader Functionality Time and Frequency Controls 8226; Advanced Shader Feature Set in Excess 8226; Configurable as Six Single-Ended, Six of Microsoft VS3.0, PS3.0 and OGL2.0 Dual-Edge Symmetric, or Three Dual- 8226; Industry Standard API Support of Edge Asymmetric Outputs Direct3D Mobile, OGL-ES 1.1 and 2.0, – Up to Three 32-Bit Enhanced Quadrature OpenVG 1.0, and OpenMax Encoder Pulse (eQEP) Modules 8226; Fine-Grained Task Switching, Load 8226; Device Identification Balancing and Power Management – Contains Electrical fuse Farm (FuseFarm) of 8226; Advanced Geometry DMA Driven Which Some Bits are Factory Programmable Operation for Minimum CPU Interaction 8226; Production ID 8226; Programmable High-Quality Image Anti- 8226; Device Part Number (Unique JTAG ID) Aliasing 8226; Device Revision (readable by Host ARM) 8226; Fully Virtualized Memory Addressing for 8226; Debug Interface Support OS Operation in a Unified Memory Architecture – JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug – LCD Controller – Supports Device Boundary Scan 8226; Up to 24-Bits Data Output; 8-Bits per – Supports IEEE 1500 Pixel (RGB) 8226; Resolution Up to 2048x2048 (With 8226; DMA Maximum 126-MHz Pixel Clock) – On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers 8226; Integrated LCD Interface Display Driver (TPTC) and One Third-Party Channel (LIDD) Controller Controller (TPCC), Which Supports Up to 64 8226; Integrated Raster Controller Programmable Logical Channels and Eight 8226; Integrated DMA Engine to Pull Data from QDMA Channels. EDMA is Used for: the External Frame Buffer without 8226; Transfers to and from On-Chip Memories Burdening the Processor via Interrupts or8226; Transfers to and from External Storage 8226; Security (EMIF, General-Purpose Memory – Crypto Hardware Accelerators (AES, SHA, Controller, Slave Peripherals) PKA, RNG) 8226; Inter-Processor Communication (IPC) 8226; Boot Modes – Integrates Hardware-Based Mailbox for IPC – Boot Mode is Selected via Boot and Spinlock for Process Synchronization Configuration Pins Latched on the Rising Between the Cortex-A8, PRCM, and PRU- Edge of the PWRONRSTn Reset Input Pin ICSS 8226; Packages: 8226; Mailbox Registers that Generate – 298-Pin S-PBGA-N298 Via Channel™ Interrupts package – Four Initiators (Cortex-A8, PRCM, (ZCE Suffix), 0.65-mm Ball Pitch PRU0, PRU1) – 324-Pin S-PBGA-N324 package 8226; Spinlock has 128 Software-Assigned (ZCZ Suffix), 0.80-mm Ball Pitch Lock Registers 1.2 Applications 8226; Gaming Peripherals 8226; Connected Vending Machines 8226; Home and Industrial Automation 8226; Weighing Scales 8226; Consumer Medical Appliances 8226; Educational Consoles 8226; Printers 8226; Advanced Toys 8226; Smart Toll Systems
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