MJB42供应商报价哪里找芯片批发报价原理和应用中文资料-中国IC网-芯三七

MJB41C (NPN), MJB42C

(PNP)

Preferred Devices

Complementary Silicon

Plastic Power Transistors

D²PAK for Surface Mount

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• Lead Formed for Surface Mount Applications in Plastic Sleeves

(No Suffix)

COMPLEMENTARY SILICON

POWER TRANSISTORS

6 AMPERES

• Lead Formed Version in 16 mm Tape & Reel (“T4” Suffix)

• Electrically the Same as TIP41 and T1P42 Series

100 VOLTS

65 WATTS

MAXIMUM RATINGS

Rating

Collector–Emitter Voltage

Collector–Base Voltage

Emitter–Base Voltage

Symbol

Value

100

5.0

Unit

Vdc

Adc

V

CEO

MARKING DIAGRAM

V

CB

V

EB

MJB4xC

YWW

Collector Current – Continuous

– Peak

I

C

6.0

10

2

Base Current

I

B

2.0

Adc

D PAK

CASE 418B

STYLE 1

Total Power Dissipation

P

D

@ T = 25_C

C

65

0.52

Watts

W/_C

Derate above 25_C

MJB4xC = Specific Device Code

Total Power Dissipation

P

D

x

= 1 or 2

@ T = 25_C

A

2.0

0.016

Watts

Y

= Year

Derate above 25_C

W/_C

mJ

WW

= Work Week

Unclamped Inductive Load Energy

(Note 1.)

E

62.5

Operating and Storage Junction

Temperature Range

T , T

–65 to

+150

_C

J

stg

ORDERING INFORMATION

Device

Package

Shipping

THERMAL CHARACTERISTICS

Characteristic

2

MJB41C

D PAK

50 Units/Rail

800/Tape & Reel

50 Units/Rail

Symbol

Max

1.92

62.5

50

Unit

_C/W

2

Thermal Resistance, Junction to Case

Thermal Resistance, Junction to Ambient

R

θ

JC

JA

MJB41CT4

MJB42C

D PAK

R

θ

2

D PAK

Thermal Resistance, Junction to Ambient

(Note 2.)

R

2

MJB42CT4

D PAK

800/Tape & Reel

Maximum Lead Temperature

for Soldering Purposes,

T

L

260

_C

Preferred devices are recommended choices for future use

1/8″ from Case for 10 Seconds

and best overall value.

1. I = 2.5 A, L = 20 mH, P.R.F. = 10 Hz, V = 10 V, R = 100 W

C

CC

BE

2. When surface mounted to an FR–4 board using the minimum recommended

pad size.

Semiconductor Components Industries, LLC, 2001

1

Publication Order Number:

March, 2001 – Rev. 0

MJB41C/D

MJB41C (NPN), MJB42C (PNP)

ELECTRICAL CHARACTERISTICS (T = 25_C unless otherwise noted)

C

Characteristic

Symbol

Min

Max

Unit

OFF CHARACTERISTICS

Collector–Emitter Sustaining Voltage (Note 3.) (I = 30 mAdc, I = 0)

V

CEO(sus)

100

–

Vdc

mAdc

µAdc

mAdc

C

B

Collector Cutoff Current (V = 60 Vdc, I = 0)

I

CEO

0.7

100

50

CE

B

Collector Cutoff Current (V = 100 Vdc, V = 0)

I

–

CE

EB

CES

EBO

Emitter Cutoff Current (V = 5.0 Vdc, I = 0)

I

–

BE

C

ON CHARACTERISTICS (Note 3.)

DC Current Gain (I = 0.3 Adc, V = 4.0 Vdc)

h

FE

30

15

–

75

–

C

CE

DC Current Gain (I = 3.0 Adc, V = 4.0 Vdc)

C

CE

Collector–Emitter Saturation Voltage (I = 6.0 Adc, I = 600 mAdc)

V

CE(sat)

–

1.5

2.0

Vdc

C

B

Base–Emitter On Voltage (I = 6.0 Adc, V = 4.0 Vdc)

V

BE(on)

C

CE

DYNAMIC CHARACTERISTICS

Current–Gain – Bandwidth Product

f

3.0

20

–

MHz

–

T

(I = 500 mAdc, V = 10 Vdc, f = 1.0 MHz)

test

C

CE

Small–Signal Current Gain

(I = 0.5 Adc, V = 10 Vdc, f = 1.0 kHz)

h

fe

C

CE

3. Pulse Test: Pulse Width v 300 µs, Duty Cycle v 2.0%.

T

A

T

C

4.0 80

3.0 60

2.0 40

1.0 20

T

C

T

A

0

20

40

60

100

120

140

160

80

T, TEMPERATURE (°C)

Figure 1. Power Derating

V

CC

+ā30 V

2.0

1.0

T = 25°C

J

R

C

25 µs

V

CC

I /I = 10

= 30 V

0.7

0.5

SCOPE

+11 V

0

C B

R

B

0.3

0.2

t

r

-ā9.0 V

D

1

t , t ≤ 10 ns

0.1

0.07

0.05

r

f

DUTY CYCLE = 1.0%

t @ V

d

≈ 5.0 V

-ā4 V

BE(off)

R and R VARIED TO OBTAIN DESIRED CURRENT LEVELS

C

B

0.03

0.02

D MUST BE FAST RECOVERY TYPE, e.g.:

1

ąą1N5825 USED ABOVE I ≈ 100 mA

0.06 0.1

0.2

0.4 0.6

1.0

2.0

4.0 6.0

B

ąąMSD6100 USED BELOW I ≈ 100 mA

B

I , COLLECTOR CURRENT (AMP)

C

Figure 2. Switching Time Test Circuit

Figure 3. Turn–On Time

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2

MJB41C (NPN), MJB42C (PNP)

1.0

0.7

0.5

D = 0.5

0.3

0.2

0.1

P

0.1

0.07

0.05

(pk)

Z

= r(t) R

θ

JC

= 1.92°C/W MAX

θ

JC(t)

0.05

R

θ

JC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t

0.02

0.01

t

1

0.03

0.02

t

1

2

T

- T = P

C

Z

θ

J(pk)

(pk) JC(t)

DUTY CYCLE, D = t /t

1 2

SINGLE PULSE

0.05

0.01

0.02

1.0

0.2

0.5

1.0

2.0

5.0

10

20

50

100

200

500

1.0 k

t, TIME (ms)

Figure 4. Thermal Response

10

There are two limitations on the power handling ability of

a transistor: average junction temperature and second

0.5Ăms

5.0

breakdown. Safe operating area curves indicate I – V

C

CE

1.0Ăms

3.0

2.0

limits of the transistor that must be observed for reliable

operation; i.e., the transistor must not be subjected to greater

dissipation than the curves indicate.

SECONDARY BREAKDOWN LTD

BONDING WIRE LTD

5.0Ăms

1.0

0.5

The data of Figure 5 is based on T

variable depending on conditions. Second breakdown pulse

= 150_C; T is

J(pk)

C

THERMAL LIMITATION @ T = 25°C

C

(SINGLE PULSE)

limits are valid for duty cycles to 10% provided T

J(pk)

CURVES APPLY BELOW RATED V

CEO

0.3

0.2

v 150_C.

T

may be calculated from the data in

J(pk)

Figure 4. At high case temperatures, thermal limitations will

reduce the power that can be handled to values less than the

limitations imposed by second breakdown.

0.1

5.0

10

20

40

60

80 100

V

CE

, COLLECTOR-EMITTER VOLTAGE (VOLTS)

Figure 5. Active–Region Safe Operating Area

5.0

300

T = 25°C

J

3.0

2.0

T = 25°C

J

200

V

CC

I /I = 10

= 30 V

C B

t

s

I = I

B1 B2

1.0

C

ib

0.7

0.5

100

70

0.3

0.2

t

f

ob

50

0.1

0.07

0.05

30

0.06 0.1

0.2

0.4 0.6

1.0

2.0

4.0 6.0

0.5

1.0

2.0 3.0

5.0

10

20 30

50

I , COLLECTOR CURRENT (AMP)

C

V , REVERSE VOLTAGE (VOLTS)

R

Figure 6. Turn–Off Time

Figure 7. Capacitance

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3

MJB41C (NPN), MJB42C (PNP)

500

2.0

T = 25°C

300

200

J

V

CE

= 2.0 V

1.6

1.2

0.8

0.4

0

T = 150°C

J

100

70

25°C

I = 1.0 A

C

2.5 A

5.0 A

50

30

20

-ā55°C

10

7.0

5.0

0.06 0.1

0.2 0.3 0.4 0.6

1.0

2.0

4.0 6.0

10

20 30

50

100

200 300 500

1000

I , COLLECTOR CURRENT (AMP)

C

I , BASE CURRENT (mA)

B

Figure 8. DC Current Gain

Figure 9. Collector Saturation Region

2.0

1.6

1.2

0.8

0.4

0

+ā2.5

+ā2.0

+ā1.5

T = 25°C

J

*APPLIES FOR I /I ≤ h /4

C B

FE

+ā1.0

+ā0.5

0

+ā25°C to +ā150°C

*āθ FOR V

VC

CE(sat)

-ā55°C to +ā25°C

+ā25°C to +ā150°C

V

@ I /I = 10

C B

BE(sat)

-ā0.5

-ā1.0

-ā1.5

-ā2.0

-ā2.5

V

@ V = 4.0 V

CE

BE

θ

FOR V

BE

VB

-ā55°C to +ā25°C

@ I /I = 10

C B

CE(sat)

0.06 0.1

0.2 0.3 0.4 0.6

1.0

2.0 3.0 4.0 6.0

0.06 0.1

0.2 0.3

0.5

1.0

2.0 3.0 4.0 6.0

I , COLLECTOR CURRENT (AMP)

C

I , COLLECTOR CURRENT (AMP)

C

Figure 10. “On” Voltages

Figure 11. Temperature Coefficients

3

2

10

10ĂM

V

= 30 V

CE

V

CE

= 30 V

1.0ĂM

100Ăk

10Ăk

I = 10 x I

C

CES

T = 150°C

J

1

0

100°C

I

C

≈ I

CES

25°C

I = I

C

-1

CES

I = 2 x I

C

CES

10

1.0Ăk

0.1Ăk

-2

REVERSE

FORWARD

(TYPICAL I VALUES

CES

OBTAINED FROM FIGURE 12)

-3

-ā0.3 -ā0.2 -ā0.1

V

0

+ā0.1 +ā0.2 +ā0.3 +ā0.4 +ā0.5 +ā0.6 +ā0.7

20

40

60

80

100

120

140

160

, BASE-EMITTER VOLTAGE (VOLTS)

T , JUNCTION TEMPERATURE (°C)

BE

J

Figure 12. Collector Cut–Off Region

Figure 13. Effects of Base–Emitter Resistance

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4

MJB41C (NPN), MJB42C (PNP)

INFORMATION FOR USING THE D²PAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the

total design. The footprint for the semiconductor packages

must be the correct size to ensure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

0.33

8.38

0.08

2.032

0.24

0.42

10.66

6.096

0.04

1.016

0.12

3.05

0.63

17.02

inches

mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a

Although one can almost double the power dissipation with

this method, one will be giving up area on the printed

circuit board which can defeat the purpose of using surface

function of the Collector pad size. These can vary from the

minimum pad size for soldering to a pad size given for

maximum power dissipation. Power dissipation for a

mount technology. For example, a graph of R

Collector pad area is shown in Figure 14.

versus

θJA

surface mount device is determined by T

, the

J(max)

maximum rated junction temperature of the die, R , the

thermal resistance from the device junction to ambient, and

70

θJA

Board Material = 0.0625″

G-10/FR-4, 2 oz Copper

°

T = 25°C

A

the operating temperature, T . Using the values provided

A

60

50

2.5 Watts

3.5 Watts

on the data sheet, P can be calculated as follows:

D

T_J(max)– T_A

P_D

=

R_θ

JA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

40

30

20

5 Watts

into the equation for an ambient temperature T of 25°C,

A

one can calculate the power dissipation of the device. For a

2

D PAK device, P is calculated as follows.

D

0

2

4

6

8

10

12

14

16

150°C – 25°C

= 2.5 Watts

P_D

=

A, Area (square inches)

50°C/W

Figure 14. Thermal Resistance versus Collector Pad

Area for the D²PAK Package (Typical)

2

The 50°C/W for the D PAK package assumes the use of

the recommended footprint on a glass epoxy printed circuit

board to achieve a power dissipation of 2.5 Watts. There are

other alternatives to achieving higher power dissipation

from the surface mount packages. One is to increase the

area of the Collector pad. By increasing the area of the

collection pad, the power dissipation can be increased.

Another alternative would be to use a ceramic substrate

or an aluminum core board such as Thermal Clad . Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

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MJB41C (NPN), MJB42C (PNP)

SOLDER STENCIL GUIDELINES

2

Prior to placing surface mount components onto a printed

circuit board, solder paste must be applied to the pads.

Solder stencils are used to screen the optimum amount.

These stencils are typically 0.008 inches thick and may be

made of brass or stainless steel. For packages such as the

SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,

SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode

packages, the stencil opening should be the same as the pad

size or a 1:1 registration. This is not the case with the DPAK

typical stencil for the DPAK and D PAK packages. The

pattern of the opening in the stencil for the Collector pad is

not critical as long as it allows approximately 50% of the

pad to be covered with paste.

SOLDER PASTE

OPENINGS

2

and D PAK packages. If one uses a 1:1 opening to screen

solder onto the Collector pad, misalignment and/or

“tombstoning” may occur due to an excess of solder. For

these two packages, the opening in the stencil for the paste

should be approximately 50% of the tab area. The opening

for the leads is still a 1:1 registration. Figure 15. shows a

STENCIL

Figure 15. Typical Stencil for DPAK and

D²PAK Packages

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within

a short time could result in device failure. Therefore, the

following items should always be observed in order to

minimize the thermal stress to which the devices are

subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied

during cooling.

* Soldering a device without preheating can cause

excessive thermal shock and stress which can result in

damage to the device.

* Due to shadowing and the inability to set the wave height

2

to incorporate other surface mount components, the D PAK

is not recommended for wave soldering.

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MJB41C (NPN), MJB42C (PNP)

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of

The line on the graph shows the actual temperature that

might be experienced on the surface of a test board at or

near a central solder joint. The two profiles are based on a

high density and a low density board. The Vitronics

SMD310 convection/infrared reflow soldering system was

used to generate this profile. The type of solder used was

62/36/2 Tin Lead Silver with a melting point between

177–189°C. When this type of furnace is used for solder

reflow work, the circuit boards and solder joints tend to

heat first. The components on the board are then heated by

conduction. The circuit board, because it has a large surface

area, absorbs the thermal energy more efficiently, then

distributes this energy to the components. Because of this

effect, the main body of a component may be up to 30

degrees cooler than the adjacent solder joints.

control settings that will give the desired heat pattern. The

operator must set temperatures for several heating zones,

and a figure for belt speed. Taken together, these control

settings make up a heating “profile” for that particular

circuit board. On machines controlled by a computer, the

computer remembers these profiles from one operating

session to the next. Figure 16. shows a typical heating

profile for use when soldering a surface mount device to a

printed circuit board. This profile will vary among

soldering systems but it is a good starting point. Factors that

can affect the profile include the type of soldering system in

use, density and types of components on the board, type of

solder used, and the type of board or substrate material

being used. This profile shows temperature versus time.

STEP 5

HEATING

ZONES 4 & 7

SPIKE"

STEP 6

VENT

STEP 7

COOLING

STEP 1

PREHEAT

ZONE 1

RAMP"

STEP 4

HEATING

ZONES 3 & 6

SOAK"

STEP 2

VENT

STEP 3

HEATING

SOAK" ZONES 2 & 5

RAMP"

205° TO 219°C

PEAK AT

SOLDER JOINT

200°C

150°C

170°C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

160°C

150°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

100°C

140°C

MASS OF ASSEMBLY)

100°C

50°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL)

T

MAX

Figure 16. Typical Solder Heating Profile

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7

MJB41C (NPN), MJB42C (PNP)

PACKAGE DIMENSIONS

2

D PAK

CASE 418B–03

ISSUE D

C

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

E

V

–B–

INCHES

DIM MIN MAX

MILLIMETERS

4

MIN

8.64

9.65

4.06

0.51

1.14

MAX

9.65

10.29

4.83

0.89

1.40

A

B

C

D

E

G

H

J

0.340

0.380

0.160

0.020

0.045

0.380

0.405

0.190

0.035

0.055

A

S

1

2

3

0.100 BSC

2.54 BSC

0.080

0.018

0.090

0.575

0.045

0.110

0.025

0.110

0.625

0.055

2.03

0.46

2.79

0.64

–T–

SEATING

PLANE

K

S

V

2.29

2.79

K

14.60

1.14

15.88

1.40

J

G

STYLE 1:

PIN 1. BASE

H

D 3 PL

2. COLLECTOR

3. EMITTER

4. COLLECTOR

M

T B

0.13 (0.005)

Thermal Clad is a registered trademark of the Bergquist Company

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

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Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

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Toll–Free from Mexico: Dial 01–800–288–2872 for Access –

then Dial 866–297–9322

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Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

001–800–4422–3781

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German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)

Email: ONlit–german@hibbertco.com

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Email: ONlit–french@hibbertco.com

Email: ONlit–asia@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2700

Email: r14525@onsemi.com

English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT)

Email: ONlit@hibbertco.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, UK, Ireland

MJB41C/D

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