MK5814
Low EMI Clock Generator
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
Connect to 4-32 MHz crystal or clock.
1
2
3
X1/ICLK
GND
S1
Input
Power Connect to ground.
Input
Function select 1 input. Selects spread amount and direction per table above.
(default-internal mid-level).
4
S0
Input
Function select 0 input. Selects spread amount and direction per table above.
(default-internal mid-level).
5
6
7
8
SSCLK
FRSEL
VDD
Output Clock output with Spread spectrum
Input Function select for input frequency range. Default to mid-level “M”.
Power Connect to +3.3 V.
XO Crystal connection to 4-32 MHz crystal. Leave unconnected for clock
X2
PCB Layout Recommendations
External Components
For optimum device performance and lowest output
phase noise, observe the following guidelines:
The MK5814 requires a minimum number of external
components for proper operation.
1) Mount the 0.01µF decoupling capacitor on the
component side of the board as close to the VDD pin
as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to
the VDD pin and the PCB trace to the ground via
should be kept as short as possible.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 7 and 2. Connect the
capacitor as close to these pins as possible. For
optimum device performance, mount the decoupling
capacitor on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
2) To minimize EMI, place the 33Ω series-termination
resistor (if needed) close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, thus minimizing vias through
other signal layers. Other signal traces should be
routed away from the MK5814 device. This includes
signal traces located underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Series Termination Resistor
Use series termination when the PCB trace between
the clock output and the load is over 1 inch. To series
terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the
clock line. Place the resistor as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20Ω.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant crystal. To
optimize the initial accuracy, connect crystal capacitors
from pins X1 to ground and X2 to ground. The value of
these capacitors is given by the following equation:
Tri-level Select Pin Operation
The S1 and S0 select pins are tri-level, meaning that
they have three separate states to make the selections
shown in the table on page 2. To select the M (mid)
level, the connection to these pins must be eliminated
by either floating them originally, or tri-stating the GPIO
pins which drive the select pins.
Crystal caps (pF) = (C - 6) x 2
L
MDS 5814 A
3
Revision 020204
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com