MMC2001HCAB33B全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

MMC2080/2075/D

Rev. 0, 10/1999

Semiconductor Products Sector

MMC2080/2075

Advance Information

MMC2080/2075 Integrated Processor with

Roaming FLEX™ Decoder

Part 1 Introduction

The MMC2080/2075 is designed to provide the messaging and paging marketplace with a powerful and

flexible solution to carry communications design into the next millennium. The MMC2080 integrates two

of Motorola’s most successful product families, M•CORE™ and the Roaming FLEX™ alphanumeric

decoders, a combination that will set a new standard in the communications industry. Except for the FLEX

decoder, the MMC2075 offers all features of the MMC2080.

Both the The MMC2080/2075 are members of the low-power, high-performance M•CORE family of 32-bit

microcontroller units (MCUs). The M•CORE is a streamlined execution engine that provides many of the

performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining

performance, speed, and cost efficiency in a compact, low-power design, the M•CORE microRISC

architecture is a natural solution for applications where battery life and systems cost are critical design goals.

Given that a total system’s components and processor core determine its power consumption, the instruction

set architecture (ISA) for the M•CORE is designed to optimize the trade-off between performance and total

power consumption. The result is system-wide reduction of total energy consumption with maintenance of

acceptable performance levels. Memory power consumption (both on-chip and external) is a major factor in

system energy consumption. By adopting 16-bit instruction encoding, and thus significantly decreasing the

memory bandwidth needed for a high rate of instruction execution, the MMC2080/2075 minimizes the

overhead of memory system energy consumption.

The MMC2080/2075 also reduces power consumption by coupling a fully static design with dynamic power

management and low-voltage operation. Versatile power management is achieved through automatic power

downs of any internal functional blocks not needed on a clock-by-clock basis. Power conservation modes

are also provided for absolute power conservation.

A table of contents for this document appears on the following page. Figure 1 on page 3 and Figure 2 on

page 4 provide simplified block diagrams of the MMC2080/2075.

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

Part 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

1.3

1.4

1.5

1.6

Conventions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Integrated Roaming FLEX Protocol and the MMC2080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Part 2 Signal and Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

2.2

MMC2080/2075 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Tables of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Part 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.1

3.2

General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Part 4 Pin-out and Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1

4.2

4.3

BGA Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PGA Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Ordering Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Part 5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1

5.2

Heat Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Electrical Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2

MMC2080/2075 Technical Data

ꢀ

Preliminary

I/O

JTAG

POR

PLL

CXFC

RESET

RSTOUT

DE

TMS

TCK

TDI

TDO

TRST

SIM

SCI

OnCE

CPU

UCLK

MPC7/URXD

MPC6/UTXD

MPC5/UCTS

MPC4/URTS

XTAL

EXTAL

OSC

MPC3/TIC1

MPC2/TOC1

INTC

Timer1

Timer0

MPD[7:0]/D[15:8]

(MPIO)

MPC1/TIC0

MPC0/TOC0

96K ROM

MPIO

D[7:0]

A[21:0]

EB[1:0]

BW8

MPE4/LOCK

MPE3/MOSI

MPE2/MISO

MPE1/SS

SPI1-FSC

Keypad

6K RAM

APB

WE

OE

TA

MPE0/SCLK

External

Bus

Bridge

MPB[7:4]/ROW[3:0]

MPB[3:0]/COL[3:0]

ABORT

BUSCLK

IRQ

MPA[5:0]

SEL[2:0], SEL3

XBOOT

CNFG

LOBAT

EXTS[1:0]

CLKOUT

SYMCLK

S[7:1]

FLEX

SPI0

Melody

S0/IFIN

BGNT

BREQ

Arbiter

MLDY

MMC2080 Only

JTAG

I/O

Figure 1. MMC2080/2075 144 Block Diagram (144-Pin Package)

ꢀ

Introduction

Preliminary

3

I/O

JTAG

POR

PLL

CXFC

TC[2:0]

RESET

RSTOUT

DE

TMS

TCK

TDI

TDO

TRST

SIM

SCI

OnCE

CPU

UCLK

MPC7/URXD

MPC6/UTXD

MPC5/UCTS

MPC4/URTS

XTAL

EXTAL

OSC

MPC3/TIC1

MPC2/TOC1

INTC

Timer1

Timer0

MPD[7:0]/D[15:8]

(MPIO)

D[7:0]

D[31:16]

A[21:0]

EB[1:0]

DVLEB[1:0]

BW8

MPC1/TIC0

MPC0/TOC0

96K ROM

MPIO

MPE4/LOCK

MPE3/MOSI

MPE2/MISO

MPE1/SS

WE

SPI1-FSC

Keypad

OE

6K RAM

APB

TA

MPE0/SCLK

External

Bus

Bridge

TEA

ABORT

BUSCLK

MPB[7:4]/ROW[3:0]

MPB[3:0]/COL[3:0]

IRQ

DSTAT[5:0]

DVLMX

MPA[5:0]

SEL[2:0], SEL3

DVLSEL

XBOOT

DVL[1:0]

CNFG

LOBAT

EXTS[1:0]

CLKOUT

SYMCLK

S[7:1]

SHS

FLEX

SPI0

Melody

S0/IFIN

BGNT

BREQ

Arbiter

MLDY

MMC2080 Only

HIGHZ

PULL_EN

JTAG

I/O

Figure 2. MMC2080/2075 DVL Block Diagram (208-Pin Package)

4

MMC2080/2075 Technical Data

ꢀ

Preliminary

Conventions and Terminology

1.1 Conventions and Terminology

This document uses the following conventions:

•

OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.

Logic level one is a voltage that corresponds to Boolean true (1) state.

Logic level zero is a voltage that corresponds to Boolean false (0) state.

To set a bit or bits means to establish logic level one.

To clear a bit or bits means to establish logic level zero.

A signal is an electronic construct whose state or changes in state convey information.

A pin is an external physical connection. The same pin can be used to connect a number of signals.

Asserted means that a discrete signal is in active logic state.

— Active low signals change from logic level one to logic level zero.

— Active high signals change from logic level zero to logic level one.

Deasserted means that an asserted discrete signal changes logic state.

— Active low signals change from logic level zero to logic level one.

— Active high signals change from logic level on to logic level zero.

•

LSB means least significant bit or bits. MSB means most significant bit or bits. References to low

and high bytes or words are spelled out.

Please refer to the examples in Table 1.

Table 1. Data Conventions

Signal/Symbol

Logic State

True

Signal State

Asserted

Voltage

V_IL/V_OL

V_IH/V_OH

V_IL/V_OL

False

Deasserted

Asserted

True

False

Deasserted

ꢀ

Introduction

Preliminary

5

Features

1.2 Features

The MMC2080/2075 offers the following suite of features.

•

M•CORE™ RISC Processor

— 32-bit load/store M•CORE RISC architecture

— Fixed 16-bit instruction length

— 16-entry 32-bit general-purpose register file

— 32-bit internal address and data buses

— Efficient, four-stage, fully interlocked execution pipeline

— Single-cycle execution for most instructions; two cycles for branches and memory accesses

— Special branch, byte, and bit manipulation instructions

— Support for byte, halfword, and word memory accesses

— Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register

file

•

Integrated Roaming FLEX alphanumeric decoder (MMC2080 only)

— FLEX paging protocol signal processor

— 1600, 3200, and 6400 bits per second (bps) decoding

— Highly programmable receiver control

— FLEX message fragmentation and group messaging support

— SSID and NID roaming support

— Internal demodulator and data slicer

— Improved battery savings via partial address correlation and intermittent receiver clock

— Full support for revision G1.9 of the FLEX protocol

— External CAP code access through parallel or serial FLASH/PROM

On-chip memory

•

— 24 K × 32 CPU ROM (96 K)

— 1.5 K × 32 CPU RAM (6 K)

On-chip peripherals

— Asynchronous serial communications interface (SCI) with IrDA capability

— Synchronous serial peripheral interface (SPI)

— Frequency synthesizer controller (FSC)

— Melody generator

— 4 × 4 keypad interface

— Multipurpose I/O ports (MPIO)

— Two 16-bit general purpose timers

— Time-of-day (TOD) timer

— Watchdog timer

— Vectored interrupt controller with 16 programmable priority levels

6

MMC2080/2075 Technical Data

ꢀ

Preliminary

Features

— Oscillator and PLL with software selectable speeds

— AMBA peripheral bridge depipelines system bus for simpler peripheral bus

— 8/16-bit external system bus with 22-bit address bus

Operating features

•

— Processor operation to 10 MHz over full operating range

— Low-power modes

— OnCE™ (On-Chip Emulation) debug module

— Voltage range 1.8 V to 3.6 V; temperature range -20 °C to 85 °C

— Chip-select outputs for four external devices (4 Mbyte per chip select, 16 Mbyte directly

addressable)

— Programmable wait states for external accesses

— External boot option

— External bus interface that accepts internal, half-word, and byte transfers

— External device that may become system bus master

Development tools

•

— Development option (different package) that adds select to bypass internal ROM

— Development option (different package) that extends external bus to 32 bits

— External bus that can display internal transfers

ꢀ

Introduction

Preliminary

7

Integrated Roaming FLEX Protocol and the MMC2080

1.3 Integrated Roaming FLEX Protocol and the MMC2080

The MMC2080 integrates several field-proven technologies, providing a versatile Roaming FLEX solution.

The MMC2080 operates the integrated FLEX decoder in an efficient power-consumption mode, allowing

the CPU to operate in a low-power mode when monitoring for message information. The Roaming FLEX

protocol is a multichannel, high-performance protocol that leading service providers worldwide have

adopted as a de facto standard for roaming paging. Roaming FLEX protocol gives service providers

increased capacity, added reliability, enhanced pager battery performance, and the ability to control a PLL-

synthesized receiver and to receive paging messages from a list of paging channels. Finally, the MMC2080

gives the service provider an upward migration path that is completely transparent to the end user.

1.4 Target Applications

The MMC2080/2075 is intended for use in wireless and paging applications. The MMC2080 is designed

for applications needing an M•CORE CPU coupled with a roaming FLEX Decoder. The MMC2075 is

intended for applications requiring the processing power and flexibility of the M•CORE CPU.

1.5 Product Documentation

The three documents listed in Table 2 are required for a complete description of the MMC2080/2075 and

are necessary to design properly with the part. Documentation is available from a local Motorola distributor,

a Motorola Semiconductor Products Sector sales office, a Motorola Literature Distribution Center, or the

World Wide Web. See the last page of this document for contact information.

Table 2. MMC2080/2075 Documentation

Document Name

Description of Contents

Order Number

M•CORE Reference Manual

Detailed description of the M•CORE MCU and

instruction set

MCORERM/AD

MMC2080/2075 User’s Manual

Detailed description of the MMC2080/2075 memory,

peripherals, and interfaces

MMC2080/2075UM/D

MMC2080/2075/D

MMC2080/2075 Technical Data

MMC2080/2075 pin and package descriptions;

electrical and timing specifications

1.6 Ordering Information

Table 3 lists the information you need to supply when placing an order. Consult a Motorola Semiconductor

Products Sector sales office or authorized distributor to determine availability and to order parts.

Table 3. MMC2080/2075 Ordering Information

Supply

Voltage

Count

Part

Package Type

Order Number

MMC2080

MMC2075

MMC2080

MMC2075

3 V

12 mm x 12 mm MAP BGA

43 mm x 43 mm Ceramic PGA

144

208

MMC2080VF001

MMC2075VF001

Contact Factory

Development Use Only

8

MMC2080/2075 Technical Data

ꢀ

Preliminary

MMC2080/2075 Pin Descriptions

Part 2 Signal and Connection Descriptions

The pins and signals of the MMC2080/2075 are described in the following sections. Figure 3 on page 10

and Figure 4 on page 11 are top and bottom views, respectively, of the 12 mm x 12 mm MAP Ball Grid

Array (BGA) package, and Figure 5 on page 12 and Figure 6 on page 13 are top and bottom views,

respectively, of the 43 mm x 43 mm ceramic Pin Grid Array (PGA) package, showing the pin-outs. Table 4

on page 14 and Table 5 on page 17 list the pins by number and signal name.

Figure 7 on page 21 is a representational pin-out of the chip, grouping the signals by their function. Table 6

on page 20 identifies the number of signals for each group and refers to Table 8 on page 23 through Table 20

on page 27, which are organized according to signal type and give a brief description of each signal pin.

2.1 MMC2080/2075 Pin Descriptions

The following section provides information about the available packages for this product, including

diagrams of the package pin-outs and tables describing how the signals of the MMC2080/2075 are allocated.

There are two packages for each part:

•

The 144-pin I/O, STD small ball (SMBALL) mold array process (MAP) ball grid array (BGA),

12 mm x 12 mm package. Table 4 on page 14 identifies the signal associated with each pin.

•

The 208-pin I/O, PGA, 43 mm x 43 mm ceramic package. Table 5 on page 17 identifies the signal

associated with each pin.

ꢀ

Signal and Connection Descriptions

9

Preliminary

MMC2080/2075 Pin Descriptions

1

2

3

4

5

6

7

8

9

10

11

12

13

V

MPB5/

ROW1

MPB2/

COL2

MPB0/

COL0

V

SS

DD

I/O

SS

DD

I/O

EB1

SEL1

SEL0

SEL2

SEL3

S2*

S1*

LOBAT* CLKOUT*

A

B

C

D

E

Core

I/O

V

MPB7/

ROW3

MPB6/

ROW2

V

DD

SS

BW8

ABORT

EB0

S7*

S6*

S5*

S4*

S3*

MLDY EXTS1*

Core

I/O

MPB4/

ROW0

MPB3/

COL3

MPB1/

COL1

V

DD

I/O

V

SS

IRQ

MPA0

D0

TA

SYMCLK EXTS0*

I/O

V

DD

MPE4/

LOCK

MPE3/

MOSI

DD

SS

MPA1

D2

OE

WE

XBOOT S0/IFIN

Core

V

SS

DD

BUSCLK

D1

EXTAL

XTAL

OSC

I/O

OSC

V

DD

SS

A21

MPA3

MPA2

D3

CXFC

A19

F

I/O

PLL

V

SS

MPA5

MPA4

D8

D4

A20

A18

G

H

J

Core

V

SS

I/O

V

DD

I/O

V

DD

I/O

D9

A16

A17

BREQ

V

MPE1/

SS

MPE2/

MISO

V

SS

D5

D10

BGNT

TDI

A15

A14

Core

I/O

V

MPC0/

TOC0

MPC5/

UCTS

MPE0/

SCLK

DD

D11

D6

D12

D7

A1

A8

A12

A10

A13

K

L

Core

V

MPC3/

TIC1

MPC6/

UTXD

V

DD

I/O

V

SS

DD

D13

TDO

TRST

A0

A5

A3

A4

A11

Core

I/O

V

MPC2/

TOC1

MPC7/

URXD

V

DD

SS

D14

D15

TCK

A2

A7

A6

TEST RSTOUT

UCLK

M

N

I/O

V

DD

I/O

MPC1/

TIC0

V

SS

I/O

MPC4/

URTS

V

SS

I/O

TMS

A9

DE

RESET

Top View

* Signal available only in 2080

Figure 3. MMC2080/2075 BGA (144-Pin) Top View

10

MMC2080/2075 Technical Data

ꢀ

Preliminary

MMC2080/2075 Pin Descriptions

13

12

11

10

9

8

7

6

5

4

3

2

1

V

MPB0/

COL0

MPB2/

COL2

MPB5/

ROW1

V

SS

DD

I/O

SS

DD

I/O

SS

CLKOUT* LOBAT*

S2 *

S1*

SEL1

SEL0

SEL2

SEL3

EB1

A

B

C

D

E

Core

I/O

V

MPB6/

ROW2

MPB7/

ROW3

DD

SS

EXTS1* MLDY

S4*

S3*

S7*

S6*

S5*

EB0

ABORT

BW8

Core

I/O

V

DD

I/O

MPB1/

COL1

MPB3/

COL3

MPB4/

ROW0

SS

EXTS0* SYMCLK

TA

MPA0

D0

IRQ

I/O

V

MPE3/

MOSI

MPE4/

LOCK

DD

SS

DD

S0/IFIN XBOOT

WE

OE

MPA1

D2

Core

V

SS

DD

SS

XTAL

EXTAL

D1

BUSCLK

OSC

I/O

V

DD

SS

DD

A21

CXFC

A19

MPA2

D3

MPA3

F

PLL

I/O

V

SS

A18

A20

D4

MPA4

D8

MPA5

G

H

J

Core

V

DD

I/O

V

DD

I/O

V

SS

I/O

BREQ

A17

A16

D9

V

MPE2/

MISO

MPE1/

SS

A15

A14

BGNT

TDI

D10

D5

Core

I/O

V

MPE0/

SCLK

MPC5/

UCTS

MPC0/

TOC0

DD

A13

A12

A10

A8

A1

D12

D7

D11

D6

K

L

Core

V

DD

I/O

MPC6/

UTXD

MPC3/

TIC1

SS

DD

SS

A11

A5

A3

A4

TDO

TRST

A0

D13

Core

I/O

V

MPC7/

URXD

MPC2/

TOC1

V

SS

DD

UCLK

RSTOUT TEST

A7

A6

A2

D15

TCK

D14

M

N

I/O

V

SS

I/O

MPC4/

URTS

V

SS

I/O

MPC1/

TIC0

V

DD

I/O

RESET

DE

A9

TMS

Bottom View

* Signal available only in 2080

Figure 4. MMC2080/2075 BGA (144-Pin) Bottom View

ꢀ

Signal and Connection Descriptions

11

Preliminary

MMC2080/2075 Pin Descriptions

1

2

3

4

5

6

7

8

9

10

11

DVLEB0

S6*

12

13

14

15

16

NC

17

MPB6/ MPB4/

ROW2 ROW0

MPB2/ MPB0/

COL2

V

SS

BW8

TA DVLEB1 SEL3

SEL1

S7*

S2 * S0/IFIN DVLMX

MLDY

EXTS0*

A

B

C

D

E

F

COL0

I/O

Core

MPB5/

ROW1

MPB3/ MPB1/

NC

PULL_EN

WE

SEL2

S5*

S3*

DVL1 LOBAT*

NC

COL3

D16

COL1

V

DD

I/O

V

SS

I/O

V

DD

I/O

IRQ

NC

ABORT EB0

TEA XBOOT S1*

DVL0

EXTS1* DSTAT4

DSTAT5 DSTAT1

V

DD

SS

MPA1

D2

NC

EB1

OE

SEL0

S4* SYMCLK DVLSEL CLKOUT* NC

NC

Core

I/O

Core

MPB7/

ROW3

V

DD

I/O

V

SS

I/O

MPE3/

MOSI

BUSCLK

MPA0

V

SS

DD

D17

MPA4

MPA5

D4

MPA2

D0

DSTAT3 DSTAT2 DSTAT0

Core

OSC

V

SS

I/O

MPE4/

LOCK

V

DD

Core

DD

D1

TC2

XTAL

G

H

J

I/O

V

DD

I/O

V

DD

PLL

SS

D18

MPA3

D3

EXTAL

A21

CXFC

OSC

V

SS

D19

D20

D9

A20

Core

PLL

V

SS

I/O

D8

D21

BGNT

D25

NC

A17

A15

BREQ

TC1

K

L

M

N

P

V

MPE2/

MISO

DD

SS

D10

D12

D6

A14

A18

A16

A19

I/O

Core

MPE0/

SCLK

V

DD

I/O

D22

D23

D24

D7

A11

V

SS

I/O

MPE1/

SS

DD

D5

UCLK

NC

I/O

V

MPC6/

UTXD

V

SS

D11

NC

TCK

TC0

HIGHZ

A1

D26

D27

A3

A8

A7

DE

NC

A12

NC

A13

NC

Core

I/O

V

SS

MPC2/ MPC4/

TOC1 URTS

DD

D14

NC

A0

TEST RSTOUT NC

NC

R

T

U

Core

I/O

MPC1/

TIC0

MPC0/

A5

V

DD

D13

TMS

TDO

D28

A10

A6

D31

A9

RESET SHS

TOC0

Core

I/O

MPC3/

TIC1

V

SS

I/O

MPC5/ MPC7/

UCTS URXD

V

SS

I/O

D15

TDI

TRST

A2

A4

D29

D30

Top View

* Signal available only in 2080

Figure 5. MMC2080/2075 PGA (208-Pin) Top View

12

MMC2080/2075 Technical Data

ꢀ

Preliminary

MMC2080/2075 Pin Descriptions

17

16

NC

15

14

13

12

11

DVLEB0

S6*

10

9

8

7

6

5

4

3

2

1

V

MPB0/ MPB2/

COL0

MPB4/ MPB6/

ROW0 ROW2

SS

MLDY

EXTS0*

DVLMX S0/IFIN S2 *

NC LOBAT* DVL1

SEL1

S7*

SEL3 DVLEB1

TA

BW8

A

B

C

D

E

F

Core

I/O

COL2

MPB1/ MPB3/

COL1

MPB5/

ROW1

S3*

S5*

SEL2

WE

EB0

OE

PULL_EN

NC

COL3

V

DD

I/O

V

SS

I/O

V

DD

I/O

DSTAT4 EXTS1*

DSTAT1 DSTAT5

NC

DVL0

S1* XBOOT TEA

ABORT D16

NC

IRQ

V

DD

SS

NC CLKOUT DVLSEL SYMCLK

S4*

SEL0

EB1

NC

MPA1

D2

Core

I/O

Core

*

MPE3/

MOSI

V

SS

I/O

V

DD

I/O

MPB7/

ROW3

NC

MPA0

BUSCLK

V

DD

SS

DSTAT0 DSTAT2 DSTAT3

D0

MPA2

D17

MPA4

MPA5

D4

OSC

Core

V

DD

Core

MPE4/

LOCK

V

SS

I/O

V

DD

XTAL

TC2

D1

G

H

J

I/O

V

DD

PLL

V

DD

I/O

SS

CXFC

EXTAL

A21

MPA3

D3

D18

OSC

V

SS

A20

D20

D9

D19

PLL

Core

V

SS

I/O

TC1

BREQ

A15

A17

D21

BGNT

D25

NC

D8

K

L

M

N

P

MPE2/

MISO

V

DD

SS

A19

A18

A16

A14

D10

D12

D6

Core

I/O

V

DD

I/O

MPE0/

SCLK

A11

D23

D24

D7

D22

V

MPE1/

SS

DD

UCLK

NC

D5

I/O

V

MPC6/

UTXD

V

SS

A13

NC

A12

NC

DE

A8

A7

A3

D26

D27

TC0

HIGHZ

A1

TCK

NC

D11

I/O

Core

MPC4/ MPC2/

URTS

V

SS

DD

NC

NC RSTOUT TEST

A0

D14

NC

R

T

U

TOC1

I/O

Core

V

MPC0/

TOC0

MPC1/

TIC0

DD

SHS RESET

D31

A9

A10

A6

A5

D28

TDO

TMS

D13

I/O

Core

V

MPC7/ MPC5/

URXD UCTS

V

SS

I/O

MPC3/

TIC1

SS

I/O

D30

D29

A4

A2

TRST

TDI

D15

Bottom View

* Signal available only in 2080

Figure 6. MMC2080/2075 PGA (208-Pin) Bottom View

ꢀ

Signal and Connection Descriptions

13

Preliminary

MMC2080/2075 Pin Descriptions

Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 1 of 3)

Pin Number

Signal Name

Pin Number

Signal Name

A1

A2

Vss I/O

G10

G11

G12

G13

H1

A20

A19

MPB5/ROW1

BW8

A3

A18

A4

MPB2/COL2

MPB0/COL0

Vdd I/O

Vss Core

Vss I/O

D8

A5

A6

H2

A7

SEL1

H3

D9

A8

Vss I/O

H4

Vdd I/O

A16

A9

Vss Core

H10

H11

H12

H13

J1

A10

A11

A12

A13

B1

S2 (2080 Only)

LOBAT (2080 Only)

CLKOUT (2080 Only)

Vdd I/O

A17

Vdd I/O

BREQ

Vss Core

D5

MPB7/ROW3

MPB6/ROW2

BW8

J2

B2

J3

D10

B3

J4

BGNT

MPE1/SS

MPE2/MIS0

Vss I/O

A15

B4

ABORT

J10

J11

J12

J13

K1

B5

EB0

B6

Vdd Core

B7

SEL0

B8

S7 (2080 Only)

S4 (2080 Only)

S1 (2080 Only)

Vss I/O

D11

B9

K2

D12

B10

B11

B12

B13

C1

C2

K3

Vdd Core

TDI

K4

MLDY

K5

A1

EXTS1 (2080 Only)

IRQ

K6

MPC0/TOC0

MPC5/UCTS

Vdd Core

K7

MPA0

K8

14

MMC2080/2075 Technical Data

ꢀ

Preliminary

MMC2080/2075 Pin Descriptions

Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 2 of 3)

Pin Number

Signal Name

MPB4/ROW0

Pin Number

Signal Name

C3

C4

K9

K10

K11

K12

K13

L1

A8

A12

MPB3/COL3

MPB1/COL1

TA

C5

MPE0/SCLK

A13

C6

C7

SEL2

A14

C8

S6 (2080 Only)

S3 (2080 Only)

SYMCLK (2080 Only)

EXTS0 (2080 Only)

Vdd I/O

D6

C9

L2

D7

C10

C11

C12

C13

D1

L3

D13

L4

TDO

L5

Vss Core

MPC3/TIC1

A5

Vss I/O

L6

Vdd Core

D0

L7

D2

L8

MPC6/UTXD

Vdd I/O

A10

D3

MPA1

L9

D4

Vss CORE

OE

L10

L11

L12

L13

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

D5

Vss I/O

Vdd I/O

A11

D6

WE

D7

SEL3

D8

S5 (2080 Only)

XBOOT

D14

D9

D15

D10

D11

D12

D13

E1

S0/IFIN (2080 only)

MPE4/LOCK

Vdd Core

MPE3/MOSI

BUSCLK

Vss I/O

TRST

A2

MPC2/TOC1

A3

E2

MPC7/URXD

A7

E3

D2

E4

D1

TEST

ꢀ

Signal and Connection Descriptions

15

Preliminary

MMC2080/2075 Pin Descriptions

Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 3 of 3)

Pin Number

Signal Name

Vdd OSC

Pin Number

Signal Name

E10

E11

E12

E13

F1

M11

M12

M13

N1

RSTOUT

Vdd I/O

UCLK

Vdd I/O

TCK

EXTAL

XTAL

Vss OSC

Vdd I/O

MPA3

MPA2

Vdd I/O

Vdd PLL

CXFC

Vss PLL

A21

N2

F2

N3

TMS

F3

N4

A0

F4

N5

MPC1/TIC0

Vss I/O

A4

F10

F11

F12

F13

G1

N6

N7

N8

MPC4/URTS

A6

N9

MPA5

MPA4

D3

N10

N11

N12

N13

A9

G2

DE

G3

RESET

Vss I/O

G4

D4

16

MMC2080/2075 Technical Data

ꢀ

Preliminary

MMC2080/2075 Pin Descriptions

Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 1 of 4)

Pin Number

Signal Name

MPB6/ROW2

Pin Number

Signal Name

A1

A2

J4

J14

J15

J16

J17

K1

D3

A21

MPB4/ROW0

BW8

A3

A20

A4

MPB2/COL2

MPB0/COL0

TA

Vss Core

Vss PLL

D8

A5

A6

A7

DVLEB1

K2

Vss I/O

D9

A8

SEL3

K3

A9

SEL1

K4

D21

A10

A11

A12

A13

A14

A15

A17

B3

Vss I/O

K14

K15

K16

K17

L1

A17

DVLEB0

A15

Vss Core

BREQ

TC1

S2 (2080 Only)

S0/IFIN (2080 only)

DVLMX

Vdd I/O

Vss Core

D10

L2

MLDY

L3

MPB5/ROW1

PULL_EN

MPB3/COL3

MPB1/COL1

WE

L4

BGNT

A14

B4

L14

L15

L16

L17

M1

M2

M3

M4

M14

M15

M16

B5

MPE2/MIS0

A18

B6

B7

A19

B8

SEL2

D22

B9

S7 (2080 Only)

S5 (2080 Only)

S6 (2080 Only)

S3 (2080 Only)

DVL1

D23

B10

B11

B12

B13

B14

D12

D25

A11

MPE0/SCLK

A16

LOBAT (2080 Only)

ꢀ

Signal and Connection Descriptions

17

Preliminary

MMC2080/2075 Pin Descriptions

Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 2 of 4)

Pin Number

Signal Name

Pin Number

Signal Name

B17

C1

EXTS0 (2080 Only)

IRQ

M17

N1

Vdd I/O

D5

C5

D16

N2

D24

C6

ABORT

N3

D6

C7

EB0

N14

N15

N16

N17

P1

UCLK

Vdd I/O

MPE1/SS

Vss I/O

D11

C8

Vdd I/O

C9

TEA

C10

C11

C12

C13

C14

C16

C17

D1

XBOOT

S1 (2080 Only)

DVLO

P2

D7

Vss I/O

P3

TCK

Vdd I/O

P4

TC0

EXTS1 (2080 Only)

DSTAT4

Vdd Core

MPA1

P5

TCK

P6

TC0

P7

D26

D2

P8

VssCore

A3

D3

Vss I/O

P9

D4

EB1

P10

P11

P12

P15

P16

P17

R1

MPC6/UTXD

A8

D5

OE

D6

Vdd Core

OE

DE

D7

Vss I/O

A12

D8

VddCORE

SEL0

D9

A13

D10

D11

D12

D13

D16

S4 (2080 Only)

SYMCLK (2080 Only)

DVLSEL

CLKOUT (2080 Only)

DSTAT5

Vdd Core

D14

R2

R4

Vdd I/O

Vss I/O

HIGHZ

R5

R6

18

MMC2080/2075 Technical Data

ꢀ

Preliminary

MMC2080/2075 Pin Descriptions

Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 3 of 4)

Pin Number

Signal Name

DSTAT1

Pin Number

Signal Name

D17

E1

R7

R8

D27

A0

BUSCLK

D2

E2

R9

MPC2/TOC1

MPC4/URTS

A7

E3

MPA0

R10

R11

R12

R13

T1

E4

MPB7/ROW3

Vdd I/O

Vss I/O

MPE3/MOSI

D17

E15

E16

E17

F1

TEST

RSTOUT

D13

T4

TMS

F2

MPA2

T5

TDO

F3

D0

T6

A1

F4

Vss CORE

DSTAT3

DSTAT2

DSTAT0

Vdd OSC

MPA4

T7

MPC1/TIC0

D28

F14

F15

F16

F17

G1

T8

T9

MPC0/TOC0

A5

T10

T11

T12

T13

T14

T15

T16

U1

Vdd Core

Vdd I/O

A10

G2

Vdd I/O

Vss I/O

D1

G3

D31

G4

RESET

SHS

G14

G15

G16

G17

H1

MPE4/LOCK

Vdd Core

TC2

D15

U4

TDI

XTAL

U5

TRST

A2

MPA5

U6

H2

D18

U7

MPC3/TIC1

Vss I/O

A4

H3

Vdd I/O

MPA3

U8

H4

U9

ꢀ

Signal and Connection Descriptions

19

Preliminary

Tables of Signals

Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 4 of 4)

Pin Number

Signal Name

Pin Number

Signal Name

H14

H15

H16

H17

J1

EXTAL

U10

U11

U12

U13

U14

U15

U16

MPC5/UCTS

MPC7/URXD

D29

Vss OSC

CXFC

Vdd PLL

D4

A6

A9

J2

D19

D30

J3

D20

Vss I/O

2.2 Tables of Signals

The MMC2080 input and output signals are organized into functional groups in Table 6 and in Figure 7 on

page 21. Table 7 on page 22 displays data relating to I/O cell names, including descriptions and the

availability of Hi-Z impedance, pull-up resistors, and high drive-current capability. Table 8 on page 23

through Table 20 on page 27 are organized according to signal type and give a brief description of each

signal pin. Package type is indicated as “N” for the 144-pin normal-function package. All pins are available

in the 208-pin development extensions package.

Table 6. MMC2080 Signal Functional Group Organization

Functional Group

Number of Signals

Detailed Description

Arbitration signals

2

52

34

13

5

Table 20 on page 27

Table 8 on page 23

Table 9 on page 24

Table 10 on page 25

Table 11 on page 25

Table 12 on page 25

Table 13 on page 26

Table 14 on page 26

Table 15 on page 26

Table 16 on page 26

Table 17 on page 26

Table 18 on page 27

Table 19 on page 27

External system bus signals

Development extensions (208-pin package only)

FLEX signals

FSC/SPI signals

SCI signals

5

Timer signals

4

Melody generator signals

Keypad signals

1

8

Dedicated MPIO signals

SIM signals

6

2

JTAG/OnCE signals

Clock and power

6

40

20

MMC2080/2075 Technical Data

Preliminary

ꢀ

Tables of Signals

MMC2080

Arbitration

Signals

BREQ

BGNT

Arbitration Request

Arbitration Grant

Receive Data

Transmit Data

Clear-To-Send

Request-To-Send

UART Clock

MPC7/URXD

MPC6/UTXD

MPC5/UCTS

MPC4/URTS

UCLK

SCI

Signals

MPD[7:0]/D[15:8]

D[7:0]

High-Order Data Bus

Low-Order Data Bus

Address

Byte Enable

Bus Width (8-Bit)

Data Direction

A[21:0]

EB0–1

BW8

Timer1 Input Capture

Timer1 Output Capture

Timer0 Input Capture

Timer0 Output Capture

MPC3/TIC1

MPC2/TOC1

MPC1/TIC0

MPC0/TOC0

Timer

Signals

External

System

Bus

WE

OE

TA

Output Enable

Melody

Generator

Signal

Transfer Acknowledge

Data Transfer Abort

External Bus Clock

External Device Select

External Boot

Signals

Generator Waveform

MLDY

ABORT

BUSCLK

SEL0–3

XBOOT

IRQ

Row Detect

Column Detect

MPB[7:4]/ROW[3:0] Keypad

MPB[3:0]/COL[3:0]

Signals

Interrupt Request

MPA[5:0]

MPIO

Signals

D[31:16]

DVLEB0–1

DVL0–1

DVLSEL

DSTAT0–5

DVLMX

TC0–2

TEA

HIGHZ

PULL_EN

SHS

Extension

Byte Enable

V

RESET

RSTOUT

DD

SIM

Signals

Master Reset

Reset Output

Development Mode

Development Select

Development Status

Status Output Select

Transfer Code

Transfer Error Acknowledge

Tri-State Disable

Pull-up Enable

Development

Extensions

(208-Pin

Test Mode Select

Test Clock

TMS

TCK

TDI

TDO

TRST

DE

Package)

Test Data In

Test Data Out

TAP Reset

JTAG/OnCE

Signals

Debug Enable

Show Cycle Strobe

Oscillator Circuit Input

Oscillator Circuit Output

PLL Filter Capacitor

Core Power

EXTAL

XTAL

CXFC

LOBAT

EXTS0–1

CLKOUT

SYMCLK

S1–7

Low Battery

Extension Symbol

Clock Output

Symbol Clock

Serial Port

FLEX

Signals

V

CORE[5]

DD

Core Ground

I/O Pad Power

I/O Pad Ground

V CORE[5]

SS

IOV [11]

DD

Clock

and

Power

Serial Port

S0/IFIN

IOV [11]

SS

MPE4/LOCK

MPE3/MOSI

MPE2/MISO

MPE1/SS

Synthesizer Lock

Master in/Slave Out

Master Out/Slave In

Slave Select

Oscillator Power

Oscillator Ground

PLL Power

OSCV

DD

FSC/SPI

Signals

OSCV

SS

DD

PLLV

MPE0/SCLK

Serial Clock

PLL Ground

PLLV

SS

Figure 7. MMC2080 Signal Group Organization

ꢀ

Signal and Connection Descriptions

21

Preliminary

Tables of Signals

Table 7. I/O Cell Description

High

Drive

I/O Cell Name

Description

Hi-Z

Pull-up

Capable

OTP

Tri-state output with selectable drive strength; always enabled

with strong drive except during JTAG Hi-Z command or unless

otherwise stated

Y

N

Y

INHP

INHPP

IOHP

Input with hysteresis

N

Y

N

Y

N

Y

N

Y

N

INHP with selectable pull-up enable

INHP and OTP

IOHPPH

SWIOP

AIN/AOT

INHPP and OTP

High-current IOHPPH

Analog input/output (same cell)

22

MMC2080/2075 Technical Data

ꢀ

Preliminary

Tables of Signals

Table 8. External System Bus Signals

Signal Name

Dir

N

I/O Cell

Description

MPD[7:0]/D[15:8]

I/O

Y

IOHPPH

High-Order Data Bus—May be used as general I/O when the

data bus is configured as an 8-bit bus. Output drivers are

disabled and pull-up resistors are enabled during reset.

D[7:0]

A[21:0]

EB[1:0]

I/O

Y

IOHPPH

IOHP

Low-Order Data Bus—Output drivers are disabled and pull-up

resistors are enabled during reset.

Address—Input when BGNT is low; otherwise output. Twenty-

two bits is a 4 Mbyte address space.

IOHP

Byte Enable (active low)—Input when BGNT is low; otherwise

output. EB0 enables D[15:8] and EB1 enables D[7:0]. When the

data bus is configured as an 8-bit bus, EB0 is always released

(high) and EB1 is always asserted (low).

BW8

WE

I/O

Y

IOHPPH

IOHP

Bus Width 8 (open-drain, active low)—If this pin is driven low

either externally or internally, the external bus functions as an 8-

bit bus.

Write Enable (active low)—Input when BGNT is low. When WE

is low, data is driven by an external device and received by the

MMC2080. Output when BGNT is high. When WE is low, data is

driven by the MMC2080 and received by an external device.

OE

TA

I/O

O

Y

IOHP

OTP

Output Enable (active low)—Input when BGNT is low; when OE

is high, D[7:0] (and D[15:8] when in 16-bit mode) external data

drivers are disabled. Output when BGNT is high; when OE is

high, drivers are disabled.

Transfer Acknowledge (active low)—An external transaction

continues when this pin is high. When low, the external data

transfer cycle will complete. When MONITOR mode is set. TA

also indicates the end of internal transactions.

ABORT

O

Data Transfer Abort (active low)—When a transaction is

aborted, this pin is driven low.

BUSCLK

SEL[3:0]

O

Y

OTP

External Bus Clock.

External Device Select—SEL0 is always active low; SEL[3:1]

may be individually programmed as active low or active high.

After reset, SEL3 is active high. SEL1 and SEL2 are active low

after restart.

XBOOT

IRQ

I

Y

INHPP

OTP

External Boot (active low)—If this pin is low after a reset, the

external boot portion of the system memory map is enabled;

otherwise the internal boot map is enabled.

O

Interrupt Request—This is driven high when either a normal

interrupt or a fast interrupt is generated by the interrupt

controller.

ꢀ

Signal and Connection Descriptions

23

Preliminary

Tables of Signals

Table 9. Development Extensions (208-Pin Package)

Signal Name

Dir

N

I/O Cell

Description

D[31:16]

I/O

N

IOHPPH

Extension to provide a 32-bit external bus. The bus is enabled when

either DVL0 or _DVL0 is asserted.

DVLEB[1:0]

DVL[1:0]

I/O

I

N

IOHPPH

INHPP

Byte Enable (active low)—Input when BGNT is low; otherwise

output. DVLEB0 enables D[31:24] and DVLEB1 enables D[23:16].

Development Mode—When DVL1 is low, the internal ROM is

bypassed. If the ROM space is addressed when DVL1 is low and

XBOOT is high, the 32-bit extension is enabled and DVLSEL is

asserted to select an external memory.

When DVL0 is low, the 32-bit bus extension is enabled for external

bus masters (BGNT is low) and for debug monitor modes.

DVLSEL

O

N

OTP

Development Select (active low)—When DVL1 is low and XBOOT

is high, this output is asserted when the internal ROM locations are

addressed.

DVLMX

I

N

INHPP

OTP

Selects the output of DSTAT[5:0].

DSTAT[5:0]

O

When DVLMX is high, DSTAT is the low-order 6 bits of the interrupt

vector. When DVLMX is low, DSTAT[3:0] is the M•CORE pipeline

status, PSTAT[3:0], and DSTAT[5:4] is the transfer size in M•CORE

format.

TC[2:0]

TEA

O

I

N

OTP

Processor Transfer Code.

INHPP

Transfer Error Acknowledge (active low).

HIGHZ

I

Tri-State Disable (active low)—When asserted (low), all tri-state

outputs are disabled (high-z). This performs the same function as

the JTAG HIGHZ command.

PULL_EN

SHS

I

N

INHPP

OTP

Enable Pull-up Resistors—When low, all pull-up resistors (except

the pull-up resistor on this I/O cell) are disabled.

O

Show Cycle Strobe (active low)— Strobes low when data is valid.

24

MMC2080/2075 Technical Data

Preliminary

ꢀ

Tables of Signals

Table 10. FLEX Signals (MMC2080 Only)

Signal Name

Dir

N

I/O Cell

Description

LOBAT

In

Y

INHP

Low Battery—LOBAT is an input signal to indicate to the MMC2080

when external battery power is going low. (An external voltage

sensing circuit is required.) Polarity is programmable.

EXTS[1:0]

In

Y

IOHP

External Symbol —EXTS 1 is the MSB of the current FLEX symbol.

EXTS0 is the LSB of the current FLEX symbol. These pins are used

when demodulation is being performed externally.

CLKOUT*

SYMCLK

O

Y

OTP

Clock Output—CLKOUT is programmable as a 38.4 or 40 kHz

clock output (derived from oscillator).

Recovered Symbol Clock—Data is synchronized to the internal

clock, and this recovered clock output enhances lock-on capability

by reducing jitter from cable-induced noise.

S[7:1]

O

Y

OTP

Control Lines 1–7—These signals are the seven additional receiver

control lines. Selectable polarity.

S0/IFIN

I/O

IOHP

S0—This signal is a receiver control output line when the IDE bit is

clear (that is, the internal demodulator is disabled).

IFIN—This signal is a limited IF input when the IDE bit is set (that is,

the internal demodulator is enabled).

Table 11. FSC/SPI1 Signals

Signal Name

Dir

N

I/O Cell

Description

MPE4/LOCK

MPE3/MOSI

MPE2/MISO

MPE1/SS

I/O

Y

IOHPPH

External Synthesizer Lock Input—PIO when SPI1 is disabled

Master-out / Slave-in—PIO when SPI1 is disabled

Master-in / Slave-out—PIO when SPI1 is disabled

Slave Select (selectable polarity)—PIO when SPI1 is disabled

Serial Clock—PIO when SPI1 is disabled

MPE0/SCLK

Table 12. SCI Signals

Signal Name

Dir

N

I/O Cell

Description

MPC7/URXD

MPC6/UTXD

MPC5/UCTS

I/O

Y

IOHPPH

Receive Data—An input when used as URXD; otherwise a PIO

Transmit Data—An output when used as UTXD; otherwise a PIO

Clear-to-Send (active low)—An input when used as UCTS;

otherwise a PIO

MPC4/URTS

UCLK

I/O

Y

IOHPPH

Request-to-Send (active low)—An output when used as URTS;

otherwise a PIO

UART Clock

ꢀ

Signal and Connection Descriptions

25

Preliminary

Tables of Signals

Table 13. Timer Signals

Signal Name

Dir

N

I/O Cell

Description

MPC3/TIC1

I/O

Y

IOHPPH

Timer1 Input Capture—An input when used as TIC1; otherwise a

PIO

MPC2/TOC1

MPC1/TIC0

MPC0/TOC0

I/O

Y

Timer1 Output Capture—An output when used as TOC1;

otherwise a PIO

Timer0 Input Capture—An input when used as TIC0; otherwise a

PIO

Timer0 Output Capture—An output when used as TOC0;

otherwise a PIO

Table 14. Melody Generator Signal

Signal Name

Dir

N

I/O Cell

Description

Melody Generator Waveform

MLDY

O

Y

OTP

Table 15. Keypad Signals

Signal Name

Dir

N

I/O Cell

Description

MPB[7:4]/

ROW[3:0]

I/O

Y

IOHPPH

Row Detect—Inputs when used as row detect; otherwise a PIO

MPB[3:0]/

COL[3:0]

Y

Column Select—Open-drain outputs when used as column

select; otherwise a PIO

Table 16. MPIO Signals

Signal Name

Dir

N

I/O Cell

Description

MPA[5:0]

I/O

Y

SWIOP

These bits can be individually programmed as input (with selectable

pull-up resistor), output (with selectable drive strength), or external

interrupt (with selectable assertion level). Each GPIO input pin is

latched at the beginning of a read cycle.

Other pinswhen

configured as

PIO

I/O

Y

IOHPP

H

These bits can be individually programmed as input (with selectable

pull-up resistor) or output (with selectable drive strength). Each

MPIO input pin is latched at the beginning of a read cycle.

Table 17. SIM Signals

Signal Name

Dir

N

I/O Cell

Description

RESET

I

Y

INHP

OTP

External Reset (active low)

Reset Output (active low)

RSTOUT

O

26

MMC2080/2075 Technical Data

ꢀ

Preliminary

Tables of Signals

Table 18. JTAG/OnCE™ Signals

Signal Name

Dir

N

I/O Cell

Description

Test Mode Select—Pull-up resistor always enabled

TMS

TCK

TDI

I

Y

INHPP

OTP

Test Clock—Pull-up resistor always enabled

Test Data In—Pull-up resistor always enabled

Test Data Out

I

TDO

TRST

DE

O

I

INHP

TAP Reset (active low)

I/O

IOHPPH

Debug Enable (open drain, active low)

Table 19. Clock and Power

Signal Name

N

I/O Cell

Description

EXTAL

XTAL

Y

AIN

AOT

AIN

Oscillator circuit input—external 76.8 kHz crystal

Oscillator circuit output

CXFC

PLL filter capacitor

V

_ddCore (5)

V_ssCore(5)

_ddIO (11)

Power

Core power

Y

Power

Core ground

V

I/O pad power

I/O pad ground

Oscillator power

Oscillator ground

PLL power

V_ssIO (11)

V_ddOSC

V_ssOSC

V_ddPLL

V_ssPLL

PLL ground

Table 20. Arbitration Signals

Signal Name

Dir

N

I/O Cell

INHPP

Description

BREQ

I

Y

Arbitration Request (active low)—Request mastership of the

internal system bus; pull-up resistor always enabled

BGNT

O

Y

OTP

Arbitration Grant (active low)—Indicates system bus is granted to

external master

ꢀ

Signal and Connection Descriptions

27

Preliminary

General Characteristics

Part 3 Specifications

3.1 General Characteristics

The MMC2080/2075 specifications are preliminary, from design simulations, and may not be fully tested

or guaranteed at this early stage of the product life cycle. Finalized specifications will be published upon the

completion of full characterization and device qualifications.

3.2 Maximum Ratings

WARNING:

This device contains circuitry protecting against damage due to high static

voltage or electrical fields; however, normal precautions should be taken to

avoid exceeding maximum voltage ratings. Reliability is enhanced if

unused inputs are tied to an appropriate logic voltage level (for example,

either Vss or Vdd).

NOTE:

In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a

reasonable sum. A maximum specification is calculated using a worst-case

variation of process parameter values in one direction. The minimum

specification is calculated using the worst-case variation for the same

parameters in the opposite direction. Therefore, a “maximum” value for a

specification will never occur in the same device that has a “minimum”

value for another specification; adding a maximum to a minimum

represents a condition that can never exist.

Table 21. DC Absolute Maximum Operating Conditions

Characteristics

Symbol

Min

Typ

Max

Units

Supply (All)

Vdd

V_I

1.8

3.0

3.6

V

Input Voltage Range

Input Clamp Current

(V₁<0 or V₁>QVDDH)

I_I

mA

Output Clamp Current

(V₁<0 or V₁>QVDDH)

I_O

^oC

Storage Temperature Range

Remaining specification information to be provided.

28

MMC2080/2075 Technical Data

ꢀ

Preliminary

BGA Details

Part 4 Pin-out and Package Information

This section provides information about the available packages for this product. The MMC2080/2075 is

available in a 144-pin Ball Grid Array (BGA) package. A 208-pin Pin Grid Array (PGA) is produced for

engineering use only. Contact the factory for availability.

4.1 BGA Details

The MMC2080/2075 is offered in the JEDEC-standard, Mold Array Process (MAP), 12 mm x 12 mm BGA

with 0.8 mm ball pitch (0.4 mm small solder balls). Refer to Figure 8 for the package drawings and

dimensions.

4.1.1

BGA Package Mechanical Drawings

The mechanical drawings for the 144-pin Ball Grid Array package are shown in Figure 8.

X

D

DETAIL K

M

Y

LASER MARK FOR PIN 1

IDENTIFICATION IN

THIS AREA

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

3. DIMENSION b IS MEASURED AT THE MAXIMUM

SOLDER BALL DIAMETER, PARALLEL TO DATUM

PLANE Z.

4. DATUM Z (SEATING PLANE) IS DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

5. PARALLELISMMEASUREMENTSHALLEXCLUDE ANY

EFFECT OF MARK ON TOP SURFACE OF PACKAGE.

E

MILLIMETERS

DIM MIN

MAX

1.60

0.34

A

A1

A2

b

1.25

0.18

1.16 REF

0.35

0.45

M

D

E

e

12.00 BSC

0.80 BSC

0.15

12X e

METALIZED MARK

FOR PIN 1 IDENTIFICATION

IN THIS AREA

13 12 11 10

9

8

5

4

3

2

1

A

B

C

D

E

F

5

0.20 Z

A2

A

G

H

J

K

L

M

0.10 Z

A1

4

Z

N

DETAIL K

ROTATED 90 CLOCKWISE

°

3

144X

b

VIEW M-M

0.15 Z X Y

0.08

Z

Figure 8. MMC2080/2075 BGA Mechanical Drawings

ꢀ

Pin-out and Package Information

29

Preliminary

PGA Details

4.2 PGA Details

The MMC2080/2075 is also offered in a ceramic, 43 mm x 43 mm PGA for engineering use only. Contact

the factory for availability. Refer to Figure 9 for the package drawings and dimensions.

4.2.1

PGA Package Mechanical Drawings

The mechanical drawings for the 208-pin Ball Grid PGA package are shown in Figure 9.

F

C

D

A

G

SEATING

PLANE

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

3. MINIMUM SPACING BETWEEN CONDUCTORS SHALL

BE 0.500.

MILLIMETERS

DIM MIN

MAX

43.70

3.68

1.90

---

2.00

5.00

0.50

E

D

E

F

G

H

K

L

b

42.70

1.78

1.14

0.08

---

2.54

0.40

e

2.54 BSC

L

B

0.200 C

K

16X

e

A

B

C

D

E

F

4X

H

16X

e

G

H

J

K

L

M

N

P

R

T

U

17 16 15 14 13 12 11 10 9

8

7

6

5

4

3 2 1

208X

b

M

0.500

0.250

C A

C

B

Figure 9. MMC2080/2075 PGA Mechanical Drawings

30

MMC2080/2075 Technical Data

ꢀ

Preliminary

Ordering Drawings

4.3 Ordering Drawings

Complete mechanical information regarding MMC2080/2075 packaging is available by facsimile through

Motorola’s MFAX™ system. Call the following number to obtain information by facsimile:

(602) 244-6591

The MFAX automated system requests the following information:

•

The receiving facsimile telephone number, including area code or country code

The caller’s personal identification number (PIN)

NOTE:

For first-time callers, the system provides instructions for setting up a PIN,

which requires the entry of a name and telephone number.

•

The type of information requested:

— Instructions for using the system

— A literature order form

— Specific-part technical information or datasheets

— Other information described by the system messages

A total of three documents may be ordered per call.

The MMC2080/2075 144-pin BGA package mechanical drawing is referenced as Case 1248A-01 Rev. 0.

The MMC2080/2075 208-pin BGA package mechanical drawing is referenced as Case 1297-01 Rev. 0.

ꢀ

Pin-out and Package Information

31

Preliminary

Heat Dissipation

Part 5 Design Considerations

5.1 Heat Dissipation

An estimate of the MMC2080/2075 chip junction temperature, T_J, in °C can be obtained from the following

equation.

T_J= T_A+ (P_D× R_θJA

)

Where:

T_A= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

R

θJA

P_D= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and

a case-to-ambient thermal resistance, as follows:

R_θJA= R_θJC+ R_θCA

Where:

R

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

θJA

θJC

θCA

R

is device related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise

change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This

model is most useful for ceramic packages with heat sinks; ninety percent of the heat flow is dissipated

through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations

where the heat flow is split between a path to the case and an alternate path through the printed circuit board,

analysis of the device’s thermal performance may need the additional modeling capability of a system-level

thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the printed circuit

board to which the package is mounted. Again, if the estimations obtained from R

do not satisfactorily

θJA

answer whether the thermal performance is adequate, a system-level model may be appropriate.

A complicating factor is the existence of three common ways for determining the junction-to-case thermal

resistance in plastic packages:

•

To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that

surface has a proper heat sink.

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal

resistance is measured from the junction to where the leads are attached to the case.

If the temperature of the package case (T_T) is determined by a thermocouple, the thermal resistance

is computed using the value obtained by the equation (T_J- T_T)/P_D.

As noted previously, the junction-to-case thermal resistances quoted in this document are determined using

the first definition. From a practical standpoint, this value is also suitable for determining the junction

32

MMC2080/2075 Technical Data

ꢀ

Preliminary

Electrical Design Considerations

temperature from a case thermocouple reading in forced convection environments. In natural convection,

using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading

on the case of the package will estimate a junction temperature slightly hotter than the actual temperature.

Hence, the new thermal metric, thermal characterization parameter or Ψ_JT, has been defined to be (T_J- T_T)/

P_D. This value gives a better estimate of the junction temperature in natural convection when using the

surface temperature of the package. Remember that surface temperature readings of packages are subject to

significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat

loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the

top center of the package with thermally conductive epoxy.

NOTE:

Section 3, “Specifications,” on page 28 of this document contains the

package thermal values for this chip.

5.2 Electrical Design Considerations

WARNING:

This device contains protective circuitry to guard against damage due to

high static voltage or electrical fields. However, normal precautions are

advised to avoid application of any voltages higher than maximum rated

voltages to this high-impedance circuit. Reliability of operation is

enhanced if unused inputs are tied to an appropriate logic voltage level (for

example, either Vss or V^DD).

Use the following list of recommendations to assure correct operation:

•

Provide a low-impedance path from the board power supply to each Vdd pin on the MMC2080/

2075 and from the board ground to each Vss pin.

Use at least four 0.1 µF bypass capacitors positioned as close as possible to the four sides of the

package to connect the Vdd power source to Vss.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip Vdd and

Vss pins are less than 0.5 inch per capacitor lead.

•

Use at least a four-layer printed circuit board (PCB) with two inner layers for Vdd and Vss.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating

capacitance. This is especially critical in systems with higher capacitive loads that could create

higher transient currents in the Vdd and Vss circuits.

•

All inputs must be terminated (that is, not allowed to float) using CMOS levels.

Take special care to minimize noise levels on the PLL supply pins (both Vdd and Vss).

ꢀ

Design Considerations

33

Preliminary

OnCE, M•CORE, MFAX, Roaming FLEX, FLEX Alphanumeric Chip, FLEX Chip, FLEX Numeric Chip, and FLEX

Stack are trademarks of Motorola, Inc.

This document contains information on a new product. Specifications and information herein are subject to change

without notice.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can

and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must

be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent

rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems

intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the

failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use

Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,

employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or

unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

All other tradenames, trademarks, and registered trademarks are the property of their respective owners.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217

1-303-675-2140 or 1-800-441-2447

JAPAN: Motorola Japan, Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku,

Tokyo 106-8573 Japan. 81-3-3440-3569

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Silicon Harbour Centre, 2 Dai King Street,

Tai Po Industrial Estate, 2 Tai Po, N.T., Hong Kong. 852-26668334

Customer Focus Center: 1-800-521-6274

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HOME PAGE: http://motorola.com/sps

Motorola DSP Products Home Page: http://www.motorola-dsp.com

MMC2080/2075/D

型号:	MMC2001HCPV33B
生命周期：	Transferred
包装说明：	,
Reach Compliance Code：	unknown
风险等级：	5.79
Base Number Matches：	1

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