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产品型号MSM7716的Datasheet PDF文件预览

E2U0043-28-82  
This version: Aug. 1998  
Previous version: Nov. 1996  
¡ Semiconductor  
MSM7716  
Single Rail Linear CODEC  
GENERAL DESCRIPTION  
The MSM7716 is a single-channel CODEC CMOS IC for voice signals that contains filters for  
linear A/D and D/A conversion.  
Designed especially for a single-power supply and low-power applications, the device is  
optimized for applications for the analog interfaces of audio signal processing DSPs and digital  
wireless systems.  
The analog output signal can directly drive a ceramic type handset receiver. In addition, levels  
for analog outputs can be set by external control.  
FEATURES  
• Single power supply  
• Low power consumption  
Operating mode  
: +2.7 V to +3.6 V  
: 24 mW Typ.  
Power down mode  
: 0.05 mW Typ.  
• Digital signal input/output interface : 14-bit serial code in 2's complement format  
• Sampling frequency(fs)  
• Transmission clock frequency  
• Filter characteristics  
: 4 to 16 kHz  
: fs ¥ 14 min., 2048 kHz max.  
: when fs = 8 kHz, complies with ITU-T Recommen-  
dation G. 714  
• Built-in PLL eliminates a master clock  
• Two input circuits in transmit section  
• Two output circuits in receive section  
• Transmit gain adjustable using an external resistor  
• Receive gain adjustable by external control 8 steps, 4 dB/step  
• Transmit mic-amp is eliminated by the gain setting of a maximum of 36 dB.  
• Analog outputs can drive a load of a minimum of 1 kW ; an amplitude of a maximum of 4.0 V  
with push-pull driving.  
PP  
• Built-in reference voltage supply  
• Package options:  
32-pin plastic TSOP (TSOPI32-P-814-0.50-1K) (Product name : MSM7716TS-K)  
30-pin plastic SSOP (SSOP30-P-56-0.65-K)  
(Product name : MSM7716GS-K)  
1/22  
¡ Semiconductor  
MSM7716  
BLOCK DIAGRAM  
MAO  
PCMOUT  
RC  
LPF  
8th  
BPF  
14 BIT  
ADCONV  
+
MAIN  
SW 1  
SW 2  
TCONT  
PBO  
+
PBIN  
AUTO  
ZERO  
SYNC  
BCLK  
PLL  
SG  
GEN  
SGC  
VFO  
SG  
VR  
GEN  
RTIM  
RC  
LPF  
5th  
LPF  
14 BIT  
DACONV  
RCONT  
VOL  
PCMIN  
PDN  
SW 4  
PWD  
PWD logic  
+
SW 4  
AUXO  
PWI  
SW  
CONT  
DEN  
CDIN  
DCLK  
CONT  
Logic  
SW 3  
+
SW 3  
VOL  
CONT  
AOUT–  
AOUT+  
VDD  
AG  
DG  
+
2/22  
¡ Semiconductor  
MSM7716  
PIN CONFIGURATION (TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
MAIN  
MAO  
NC  
PDN  
SYNC  
NC  
NC  
NC  
BCLK  
PCMOUT  
PCMIN  
DG  
DEN  
CDIN  
NC  
NC  
PBO  
PBIN  
NC  
SGC  
AG  
AUXO  
AOUT+  
AOUT–  
NC  
NC  
NC  
DCLK  
VDD  
NC  
PWI  
VFO  
NC : No connect pin  
32-Pin Plastic TSOP  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
AG  
AUXO  
AOUT+  
AOUT–  
PWI  
VFO  
NC  
NC  
NC  
VDD  
DCLK  
NC  
CDIN  
DEN  
DG  
SGC  
PBIN  
PBO  
NC  
NC  
MAO  
MAIN  
NC  
NC  
PDN  
SYNC  
NC  
BCLK  
PCMOUT  
PCMIN  
NC : No connect pin  
30-Pin Plastic SSOP  
3/22  
¡ Semiconductor  
MSM7716  
PIN AND FUNCTIONAL DESCRIPTIONS  
MAIN, MAO  
Transmit microphone input and the level adjustment.  
MAINisconnectedtothenoninvertinginputoftheop-amp,andMAOisconnectedtotheoutput  
of the op-amp. The level adjustment should be configured as shown below.  
During power saving and power down modes, the MAO output is in high impedance state.  
R1 : variable  
R2 > 20 kW  
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F)  
MAO  
MAIN  
C1  
R2  
+
Microphone input  
R1  
Gain = R2/R1 < 63  
SG  
PBIN, PBO  
Transmit handset input and the level adjustment.  
PBIN is connected to the noninverting input of the op-amp, and PBO is connected to the output  
of the op-amp. The level adjustment should be configured as shown below.  
During power saving and power down, the PBO output is in high impedance state.  
R4  
R3 : variable  
R4 > 20 kW  
C2 > 1/(2 ¥ 3.14 ¥ 30 ¥ R3) (F)  
PBO  
PBIN  
C2  
Handset  
microphone input  
+
R3  
Gain = R4/R3 < 63  
SG  
V
DD  
Power supply pin for +2.7 to 3.6 V (Typically 3.0 V).  
AG  
Analog signal ground.  
DG  
Ground pin for the digital signal circuits.  
This ground is separated from the analog signal ground in this device. The DG pin must be  
connected to the AG pin on the printed circuit board.  
4/22  
¡ Semiconductor  
MSM7716  
VFO  
Receive filter output.  
The output signal has an amplitude of 2.0 V above and below the signal ground voltage when  
PP  
the digital signal of +3 dBm0 is input to PCMIN. VFO can drive a load of 20 kW or more.  
This output can be externally controlled in the level range of 0 to –28 dB in 4 dB increments.  
During power saving or power down, VFO output is at the voltage level (V /2) of SG with a  
DD  
high impedance state.  
PWI, AOUT+, AOUT–  
PWI is connected to the inverting input of the receive driver.  
The receive driver output is connected to the AOUT– pin. Thus, a receive level can be adjusted  
with the pins PWI, AOUT–, and VFO described above.  
The output of AOUT+ is inverted with respect to the output of AOUT– with a gain of 1.  
The output signal amplitudes are a maximum of 2.0 V  
.
PP  
These outputs, above and below the signal ground voltage (V /2), can drive a load of a  
DD  
minimum of 1 kW with push-pull driving (a load connected between AOUT+ and AOUT–).  
The output amplitudes are 4 V maximum during push-pull driving. These outputs can be  
PP  
mute controlled externally. These outputs are operational during power saving and output the  
SG voltage (V /2) in the high impedance state.  
DD  
AUXO  
Auxiliary receive filter output.  
The output signal is inverted with respect to the VFO output with a gain of 1. The output signal  
swings above and below the SG voltage (V /2), and can drive a minimum load of 0.5 kW with  
DD  
respect to the SG voltage.  
The output can be mute controlled externally.  
During power saving and power down, AUXO outputs the SG voltage (V /2) in the high  
DD  
impedance state.  
BCLK  
Shift clock signal input for PCMIN and PCMOUT.  
The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit  
and receive circuits to the power-saving state.  
5/22  
¡ Semiconductor  
MSM7716  
SYNC  
Synchronizing signal input.  
In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously  
with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all  
timing signals of the transmit section.  
Inthereceivesection,14bitsrequiredareselectedfromserialinputofPCMsignalsonthePCMIN  
pin by the synchronizing signal.  
Signals in the receive section are synchronized by this synchronizing signal. This signal must be  
synchronized in phase with the BCLK.  
When this signal frequency is 8 kHz, the transmit and receive section have the frequency  
characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in  
this data sheet.  
For different frequencies of the SYNC signal, the frequency values in this data sheet should be  
translated according to the following equation:  
Frequency values described in the data sheet  
¥ the SYNC frequency values to be actually used  
8 kHz  
Setting this signal to logic "1" or "0" drives the device to power-saving state.  
PCMIN  
PCM signal input.  
A serial PCM signal input to this pin is converted to an analog signal synchronously with the  
SYNC signal and BCLK signal.  
The data rate of the PCM signal is equal to the frequency of the BCLK signal.  
The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the  
internal register when shifted by 14 bits.  
The top of the data (MSD) is identified at the rising edge of SYNC.  
The input signal should be input in the 14-bit 2's complement format.  
The MSD bit represents the polarity of the signal with respect to the signal ground.  
6/22  
¡ Semiconductor  
MSM7716  
PCMOUT  
PCM signal output.  
The PCM output signal is output from MSD in sequential order, synchronously with the rising  
edge of the BCLK signal.  
MSD may be output at the rising edge of the SYNC signal, depending on the timing between  
BCLK and SYNC.  
This pin is in high impedance state except during 14-bit PCM output. It is also high impedance  
during power saving or power down mode.  
A pull-up resistor must be connected to this pin, because its output is configured as an open  
drain.  
The output coding format is in 14-bit 2's complement.  
The MSD represents a polarity of the signal with respect to the signal ground.  
Table 1  
Input/Output Level  
PCMIN/PCMOUT  
MSD  
+Full scale  
0
0
0
1
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
+1  
0
–1  
–Full scale  
PDN  
Power down control signal input.  
A digital "L" level drives both transmit and receive circuits to a power down state.  
The control registers are set to the initial state.  
SGC  
Connection of a bypass capacitor for generating the signal ground voltage level.  
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and  
the SGC pin.  
7/22  
¡ Semiconductor  
MSM7716  
DEN, DCLK, CDIN  
Serial control ports for the microcontroller interface.  
Writing data to the 8-bit control register enables control of the receive output level and the signal  
path.  
DEN is the "Enable" signal pin, DCLK is the data shift clock input pin, and CDIN is the control  
data input pin.  
Whenpowereddown(PDN=0), theinitialvaluesaresetasshowninTables2, 3, and4. Theinitial  
values are held unless the control data is written after power-down release.  
The control data is shifted at the rising edge of the DCLK signal and latched into the internal  
control register at the rising edge of the DEN signal.  
When the microcontroller interface is not used, these pins should be connected to DG.  
The bit map of the 8-bit control register is shown below.  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
SW1  
SW2  
SW3  
SW4  
VOL1  
VOL2  
VOL3  
8/22  
¡ Semiconductor  
MSM7716  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Power Supply Voltage  
Analog Input Voltage  
Digital Input Voltage  
Storage Temperature  
Symbol  
VDD  
Condition  
AG = DG = 0 V  
AG = DG = 0 V  
AG = DG = 0 V  
Rating  
Unit  
V
–0.3 to +7.0  
VAIN  
–0.3 to VDD + 0.3  
–0.3 to VDD + 0.3  
–55 to +150  
V
VDIN  
TSTG  
V
°C  
RECOMMENDED OPERATING CONDITIONS  
Parameter  
Power Supply Voltage  
Operating Temperature  
Analog Input Voltage  
Symbol  
Condition  
Min.  
Typ.  
3.0  
Max.  
Unit  
V
VDD  
2.7  
–30  
3.6  
+85  
1.4  
Ta  
+25  
°C  
VAIN Gain = 1  
VPP  
0.45 ¥  
VDD  
High Level Input Voltage  
Low Level Input Voltage  
VIH SYNC, BCLK, PCMIN, PDN,  
VDD  
V
V
DEN, DCLK, CDIN  
VIL  
0.16 ¥  
0
VDD  
Clock Frequency  
FC  
BCLK  
14 ¥ Fs  
128 ¥ Fs kHz  
Sync Pulse Frequency  
Clock Duty Ratio  
FS  
DC  
tIr  
SYNC  
4.0  
40  
8.0  
50  
16  
60  
kHz  
%
BCLK  
Digital Input Rise Time  
Digital Input Fall Time  
SYNC, BCLK, PCMIN, PDN,  
DEN, DCLK, CDIN  
50  
ns  
ns  
ns  
ns  
ns  
ns  
kW  
pF  
tIf  
50  
tXS, tRS BCLKÆSYNC, See Fig.1  
100  
100  
1 BCLK  
1 BCLK  
100  
100  
0.5  
Sync Pulse Setting Time  
t
SX, tSR SYNCÆBCLK, See Fig.1  
tWSH SYNC, See Fig.1  
tWSL SYNC, See Fig.1  
tDS Refer to Fig.1  
High Level Sync Pulse Width *1  
Low Level Sync Pulse Width *1  
PCMIN Setup Time  
PCMIN Hold Time  
tDH Refer to Fig.1  
RDL Pull-up resistor  
Digital Output Load  
DCLK Pulse Width  
DEN Setting Time 1  
DEN Setting Time 2  
CDL  
100  
tWCL DCLK Low width, See Fig.2  
tWCH DCLK High width, See Fig.2  
tCDL DCLKÆDEN, See Fig.2  
tDCL DENÆDCLK, See Fig.2  
tCDH DCLKÆDEN, See Fig.2  
tDCH DENÆDCLK, See Fig.2  
tCDS See Fig.2  
50  
ns  
ns  
ns  
ns  
50  
50  
50  
50  
50  
CDIN Setup Time  
CDIN Hold Time  
50  
tCDH See Fig.2  
50  
Transmit gain stage, Gain = 0 dB  
Voff  
–100  
–10  
+100  
+10  
1000  
mV  
mV  
ns  
Analog Input Allowable DC Offset  
Allowable Jitter Width  
Transmit gain stage, Gain = 20 dB  
SYNC, BCLK  
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is  
2048 kHz.  
9/22  
¡ Semiconductor  
MSM7716  
RECOMMENDED OPERATING CONDITIONS (Continued)  
Parameter  
Symbol  
Condition  
Min.  
20  
Typ.  
Max.  
Unit  
tSD  
100  
100  
100  
100  
tXD1 CL = 50 pF + 1 LSTTL  
tXD2 Pull-up resistor = 500 W  
tXD3  
20  
Digital Output Delay Time  
ns  
20  
20  
ELECTRICAL CHARACTERISTICS  
DC and Digital Interface Characteristics  
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C)  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
10.0  
8.0  
Max.  
17.0  
Unit  
mA  
V
DD = 3.6 V  
Operating mode,  
No signal  
IDD1  
VDD = 3.0 V  
13.0  
mA  
Power-saving mode, PDN = 1,  
Power Supply Current  
IDD2  
6.0  
0.01  
11.0  
0.05  
VDD  
mA  
mA  
V
SYNC, BCLK Æ OFF  
IDD3 Power-down mode, PDN = 0  
0.45 ¥  
High Level Input Voltage  
Low Level Input Voltage  
VIH  
SYNC, BCLK, PCMIN, DEN,  
VDD  
CDIN, DCLK, PDN  
VIL  
0.16 ¥  
VDD  
2.0  
0.0  
V
High Level Input Leakage Current  
Low Level Input Leakage Current  
Digital Output Low Voltage  
Digital Output Leakage Current  
Input Capacitance  
IIH  
IIL  
0.0  
0.2  
5
mA  
mA  
V
0.5  
VOL PCMOUT pull-up resistor = 500 W  
0.4  
IO  
10  
mA  
pF  
CIN  
10/22  
¡ Semiconductor  
MSM7716  
Transmit Analog Interface Characteristics  
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C)  
Parameter  
Input Resistance  
Symbol  
Condition  
Min.  
10  
Typ.  
Max.  
Unit  
MW  
kW  
pF  
RINX MAIN, PBIN  
Output Load Resistance  
Output Load Capacitance  
Output Amplitude  
RLGX MAO, PBO with respect to SG  
20  
CLGX  
VOGX  
30  
–0.7  
–20  
+0.7  
+20  
V
Offset Voltage  
VOSGX  
Gain = 1  
mV  
Receive Analog Interface Characteristics  
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C)  
Parameter  
Output Resistance  
Symbol  
Condition  
Min.  
Typ.  
Max.  
10  
Unit  
W
ROAO AUXO, AOUT+, AOUT-  
ROVO VFO  
100  
W
AUXO, AOUT+, AOUT– (each)  
with respect to SG  
RLAO  
0.5  
kW  
Output Load Resistance  
RLVO VFO with respect to SG  
CLAO Output open  
20  
50  
kW  
Output Load Capacitance  
Output Amplitude  
pF  
AUXO, AOUT+, AOUT–, VFO  
VOAO  
–1.0  
+1.0  
V
with respect to SG  
AUXO, AOUT+, AOUT–, VFO  
VOSA  
Offset Voltage  
–100  
+100  
mV  
with respect to SG  
11/22  
¡ Semiconductor  
MSM7716  
AC Characteristics  
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C)  
Freq.  
(Hz)  
Level  
(dBm0)  
Parameter  
Symbol  
Condition Min.  
Typ.  
Max.  
Unit  
Loss 1  
Loss 2  
Loss 3  
Loss 4  
Loss 5  
Loss 6  
Loss T1  
Loss T2  
Loss T3  
Loss T4  
Loss T5  
Loss T6  
LossR1  
LossR2  
LossR3  
LossR4  
LossR5  
SD 1  
60  
300  
20  
–0.2  
+0.4  
Analog  
1020  
2020  
3000  
3400  
60  
Reference  
to  
Overall Frequency Response  
0
dB  
–0.2  
+0.4  
+0.4  
1.6  
Analog  
–0.2  
0
20  
300  
–0.15  
+0.2  
Transmit Frequency Response  
(Expected Value)  
1020  
2020  
3000  
3400  
300  
Reference  
0
0
dB  
dB  
–0.15  
–0.15  
0
+0.2  
+0.2  
0.8  
–0.15  
+0.2  
1020  
2020  
3000  
3400  
Reference  
Receive Frequency Response  
(Expected Value)  
–0.15  
–0.15  
0.0  
+0.2  
+0.2  
0.8  
3
Analog  
to  
55.9  
55.9  
55.9  
45.9  
35.9  
25.9  
15.9  
58  
SD 2  
0
Analog  
SD 3  
–10  
–20  
–30  
–40  
–50  
3
Overall Signal to Distortion Ratio  
SD 4  
1020  
1020  
1020  
dB  
dB  
dB  
*1  
*1  
*1  
SD 5  
SD 6  
SD 7  
SD T1  
SD T2  
SD T3  
SD T4  
SD T5  
SD T6  
SD T7  
SD R1  
SD R2  
SD R3  
SD R4  
SD R5  
SD R6  
SD R7  
0
58  
–10  
–20  
–30  
–40  
–50  
3
58  
Transmit Signal to Distortion Ratio  
(Expected Value)  
48  
38  
28  
18  
58  
0
58  
–10  
–20  
–30  
–40  
–50  
58  
Receive Signal to Distortion Ratio  
(Expected Value)  
48  
38  
28  
18  
*1 Psophometric filter is used.  
12/22  
¡ Semiconductor  
MSM7716  
AC Characteristics (Continued)  
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C)  
Freq.  
(Hz)  
Level  
(dBm0)  
Parameter  
Symbol  
Condition Min.  
Typ.  
Max.  
Unit  
GT 1  
GT 2  
3
Analog  
to  
–0.4  
+0.01  
Reference  
0.00  
+0.4  
–10  
–40  
–50  
–55  
3
Analog  
Overall Gain Tracking  
GT 3  
1020  
1020  
1020  
–0.3  
–1.3  
–1.6  
–0.3  
+0.8  
+1.3  
+1.6  
+0.3  
dB  
GT 4  
–0.03  
GT 5  
–0.15  
GT T1  
GT T2  
GT T3  
GT T4  
GT T5  
GT R1  
GT R2  
GT R3  
GT R4  
GT R5  
+0.01  
–10  
–40  
–50  
–55  
3
Reference  
0.00  
Transmit Gain Tracking  
(Expected Value)  
–0.3  
–0.6  
–1.2  
–0.3  
+0.3  
+0.6  
+1.2  
+0.3  
dB  
dB  
–0.03  
+0.15  
–0.06  
–10  
–40  
–50  
–55  
Reference  
–0.02  
Receive Gain Tracking  
(Expected Value)  
–0.3  
–0.6  
–1.2  
+0.3  
+0.6  
+1.2  
–0.02  
–0.27  
13/22  
¡ Semiconductor  
MSM7716  
AC Characteristics (Continued)  
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C)  
Freq.  
(Hz)  
Level  
(dBm0)  
Parameter  
Symbol  
Condition Min.  
Typ.  
–70  
–76  
–76  
Max.  
–66  
Unit  
AIN: no signal  
Overall Idle Channel Noise  
Nidle A  
Nidle T  
NidleR  
*1  
dBmOp  
Transmit Idle Channel Noise  
(Expected Value)  
–74  
AIN: no signal  
dBmOp  
Vrms  
Receive Idle Channel Noise  
(Expected Value)  
*1  
–74  
VDD = 3.0 V  
AV T  
AV R  
0.338  
0.350  
0.500  
0.362  
0.518  
Absolute Level (Initial Level)  
1020  
0
Ta = 25°C  
0.483  
*2  
V
DD = +2.7  
AV Tt  
AV Rt  
–0.2  
–0.2  
+0.2  
+0.2  
dB  
dB  
Absolute Level  
to 3.6 V  
Ta = –30  
to 85°C  
A to A  
BCLK  
(Deviation of Temperature and Power)  
Absolute Delay  
tD  
1020  
500  
0
0
0.6  
ms  
ms  
= 64 kHz  
tGD T1  
75  
70  
0.325  
0.175  
0.325  
0.125  
0.325  
Transmit Group Delay  
tGD T2 600 to 2600  
*3  
*3  
tGD T3  
2800  
tGD R1 500 to 2600  
0.00  
0.12  
85  
Receive Group Delay  
Crosstalk Attenuation  
0
0
ms  
dB  
tGD R2 2800  
CR T  
1020  
CR R  
TRANS Æ RECV  
RECV Æ TRANS  
80  
*1 Psophometric filter is used.  
*2 AVT is defined at MAO and PBO-PCMOUT.  
AVR is defined at PCMIN-VFO.  
VOL = 0 dB  
*3 Minimum value of the group delay distortion  
14/22  
¡ Semiconductor  
MSM7716  
AC Characteristics (Continued)  
(Fs = 8 kHz, VDD = 2.7 V to 3.6 V, Ta = –30°C to +85°C)  
Freq.  
(Hz)  
4.6 kHz to  
72 kHz  
300 to  
3400  
Level  
(dBm0)  
Parameter  
Discrimination  
Symbol  
Condition Min.  
Typ.  
32  
Max.  
Unit  
dB  
0 to  
DIS  
S
0
0
30  
4000 Hz  
4.6 kHz to  
Out-of-band Spurious  
–37.5  
–52  
30  
–35  
–40  
dBm0  
dBm0  
100 kHz  
fa = 470  
fb = 320  
0 to  
Intermodulation Distortion  
IMD  
–4  
2fa – fb  
*1  
PSR T  
Power Supply Noise Rejection Ratio  
Auxiliary Output Gain  
50 mVPP  
0
dB  
dB  
PSR R 50 kHz  
G
1020  
VFO to AUXO  
Set at – 4 dB  
–8 dB  
–1.0  
–5  
0
+1.0  
–3  
AUX  
GV2  
GV3  
GV4  
GV5  
GV6  
GV7  
GV8  
–4  
–9  
–8  
–7  
–12 dB  
–13  
–17  
–21  
–25  
–29  
–12  
–16  
–20  
–24  
–28  
–11  
–15  
–19  
–23  
–27  
Referenced  
to 0 dB  
setting  
VOL Gain Setting Value  
1020  
0
–16 dB  
dB  
–20 dB  
–24 dB  
–28 dB  
*1 Measured inband.  
15/22  
¡ Semiconductor  
MSM7716  
TIMING DIAGRAM  
PCM Data Output Timing  
Transmit Timing  
BCLK  
SYNC  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
tXS  
tSX  
tWSL  
tWSH  
tSD  
tXD1  
tXD2  
tXD3  
PCMOUT  
MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14  
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1  
.
When tSX < 1/2 • Fc, the Delay of the MSD bit is defined as tSD  
.
Receive Timing  
BCLK  
tRS  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
tSR  
tWSL  
tWSH  
SYNC  
tDH  
tDS  
PCMIN  
MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14  
Figure 1 Basic Timing Diagram  
MCU Interface Timing  
DCLK  
DEN  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
tCDL  
tDCL  
tCDH  
tDCH  
tWCL tWCH  
tCDH  
B1  
tCDS  
B3  
CDIN  
B7  
B6  
B5  
B4  
B2  
B0  
Figure 2 MCU Interface Timing Diagram  
16/22  
¡ Semiconductor  
MSM7716  
FUNCTIONAL DESCRIPTION  
Control Data Description  
SW1, SW2 - - Control bits for the transmit speech path switch.  
The AD converter input is selected according to the bit data shown in Table 2.  
Table 2  
State SW2  
SW1  
AD Converter Input  
No signal (muting state)  
Remarks  
T1  
T2  
T3  
T4  
0
0
1
1
0
1
0
1
Input signal to MAIN  
At initial setting  
Input signal to PBIN  
Addition signal of both MAIN and PBIN  
The gain of each input drops about 6 dB  
SW3, SW4 - - Control bits for the receive speech path switch.  
The control should be performed according to Table 3.  
Table 3  
State SW4  
SW3  
AOUT+, AOUT– Output  
AUXO Output  
Remarks  
R1  
R2  
R3  
R4  
0
0
1
1
0
1
0
1
SG  
PWI  
SG  
SG  
SG  
DA  
DA  
At initial setting  
PWI  
DA: DA converter output. SG: signal ground voltage.  
VOL1, VOL2, VOL3- - - Control bits for the receive signal output level.  
By controlling these bits, the output levels of VFO and AUXO can be  
controlled according to Table 4.  
Table 4  
VOL1 VOL2 VOL3  
Receive Signal Gain  
Remarks  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 dB  
–4 dB  
At initial setting  
–8 dB  
–12 dB  
–16 dB  
–20 dB  
–24 dB  
–28 dB  
17/22  
¡ Semiconductor  
MSM7716  
APPLICATION CIRCUIT  
1 kW  
+3 V  
MSM7716  
Microphone  
analog input  
MAIN  
PCMOUT  
PCMIN  
BCLK  
PCM output  
PCM input  
20 kW  
20 kW  
20 kW  
20 kW  
1 mF  
MAO  
Handset  
analog input  
PCM shift clock input  
PBIN  
PBO  
1 mF  
SYNC  
8 kHz SYNC pulse input  
Addition  
signal input  
VFO  
PWI  
20 kW  
20 kW  
1 mF  
PDN  
Power down control input  
"1" = Operation  
20 kW  
"0" = Power down  
AOUT–  
AOUT+  
AUXO  
Analog output*  
Analog inverted  
output*  
Auxiliary output*  
DCLK  
DEN  
0.1 mF  
1 mF  
Controller  
SGC  
AG  
CDIN  
0 V  
+3 V  
DG  
10 mF  
0 to 10 W  
+
VDD  
* The swing of the analog output signal is a maximum of 1.0 V above and below the VDD/2 offset level.  
18/22  
¡ Semiconductor  
MSM7716  
APPLICATION INFORMATION  
Digital pattern for 0 dBm0  
The digital pattern for 0 dBm0 is shown below.  
(SYNC frequency = 8 kHz, signal frequency = 1 kHz)  
S2  
S3  
S1  
S4  
SG  
S5  
S8  
S6  
S7  
Sample No. MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
S8  
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
0
19/22  
¡ Semiconductor  
MSM7716  
NOTES ON USE  
• Toensureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency  
characteristics for the power supply and keep them as close as possible to the device pins.  
• Connect the AG pin and the DG pin as close as possible. Connect to the system ground with  
low impedance.  
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the  
use of IC socket is unavoidable, use the short lead type socket.  
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave  
sources such as power supply transformers surround the device.  
• Keep the voltage on the V pin not lower than –0.3 V even instantaneously to avoid latch-  
DD  
up that may otherwise occur when power is turned on.  
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)  
powersupplytoavoiderroneousoperationandthedegradationofthecharacteristicsofthese  
devices.  
20/22  
¡ Semiconductor  
PACKAGE DIMENSIONS  
TSOPI32-P-814-0.50-1K  
MSM7716  
(Unit : mm)  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
0.27 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
21/22  
¡ Semiconductor  
MSM7716  
(Unit : mm)  
SSOP30-P-56-0.65-K  
Mirror finish  
Package material  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
Epoxy resin  
42 alloy  
Solder plating  
5 mm or more  
0.19 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
22/22  
配单直通车
MSM7715GS-2K产品参数
型号:MSM7715GS-2K
是否Rohs认证: 不符合
生命周期:Obsolete
包装说明:QFP, QFP44,.53X.57,32
Reach Compliance Code:unknown
风险等级:5.92
JESD-30 代码:R-PQFP-G44
JESD-609代码:e0
端子数量:44
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:QFP
封装等效代码:QFP44,.53X.57,32
封装形状:RECTANGULAR
封装形式:FLATPACK
电源:3 V
认证状态:Not Qualified
子类别:Modems
最大压摆率:20 mA
标称供电电压:3 V
表面贴装:YES
技术:CMOS
电信集成电路类型:MODEM
温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.8 mm
端子位置:QUAD
Base Number Matches:1
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