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产品型号MT093的Datasheet PDF文件预览

ISO-CMOS  
8 x 12 Analog Switch Array  
MT093  
ISSUE 1  
January 1990  
Features  
Internal control latches and address decoder  
Ordering Information  
Short set-up and hold times  
MT093AC  
MT093AE  
MT093AP  
40 Pin Ceramic DIP  
40 Pin Plastic DIP  
44 Pin PLCC  
Wide operating voltage: 4.5V to 14.5V  
3.5Vpp analog signal capability  
0° to 70°C  
R
65max. @ V =14V, 25°C  
DD  
ON  
R  
10@ V =14V, 25°C  
DD  
ON  
Description  
Full CMOS switch for low distortion  
The Mitel MT093 is fabricated in MITEL’s ISO-CMOS  
technology providing low power dissipation and high  
reliability. The device contains a 8×12 array of  
crosspoint switches along with a 7 to 96 line decoder  
and latch circuits. Any one of the 96 switches can be  
addressed by selecting the appropriate seven input  
bits. The selected switch can be turned on or off by  
applying a logical one or zero to the DATA input.  
Minimum feedthrough and crosstalk  
Low power consumption ISO-CMOS technology  
Applications  
PBX systems  
Mobile radio  
Test equipment /instrumentation  
Analog/digital multiplexers  
Audio/Video switching  
STROBE  
DATA RESET  
VDD  
VSS  
1
1
AX0  
AX1  
AX2  
8 x 12  
Switch  
Array  
7 to 96  
Decoder  
Xi I/O  
(i=0-11)  
AX3  
Latches  
AY0  
AY1  
96  
96  
AY2  
• • • • • • • • • • • • • • • • • • •  
Yi I/O (i=0-7)  
Figure 1 - Functional Block Diagram  
3-65  
MT093 ISO-CMOS  
1
2
3
4
5
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
Y3  
VDD  
Y2  
DATA  
Y1  
NC  
Y0  
AY2  
RESET  
AX3  
AX0  
NC  
40  
44 43 42 41  
6
5 4 3 2  
1
7
39  
NC  
NC  
X6  
NC  
NC  
X0  
X1  
X2  
X3  
X4  
X5  
NC  
NC  
NC  
8
6
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
9
7
NC  
NC  
X0  
10  
11  
12  
13  
14  
15  
16  
8
X6  
XY  
9
X8  
X7  
X1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
X9  
X8  
X2  
X10  
X9  
X3  
X11  
NC  
NC  
NC  
X10  
X11  
NC  
X4  
X5  
NC  
NC  
AY1  
AY0  
AX2  
AX1  
Y4  
17  
Y7  
18 19 20 21 22 23 24 25 26 27 28  
NC  
Y6  
STROBE  
Y5  
VSS  
40 PIN CERDIP/PLASTIC DIP  
44 PIN PLCC  
Figure 2 - Pin Connections  
Description  
Pin Description  
Pin #*  
Name  
1
2
Y3  
Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.  
Y2 Address Line (Input).  
AY2  
3
RESET Master RESET (Input): this is used to turn off all switches. Active High.  
AX3,AX0 X3 and X0 Address Lines (Inputs).  
4,5  
6,7  
8-13  
NC  
No Connection.  
X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch  
array.  
14  
15  
16  
17  
18  
NC  
Y7  
NC  
Y6  
No Connection.  
Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.  
No Connection.  
Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.  
STROBE STROBE (Input): enables function selected by address and data. Address must be stable  
before STROBE goes high and DATA must be stable on the falling edge of the STROBE.  
Active High.  
19  
20  
Y5  
Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.  
Ground Reference.  
V
SS  
21  
Y4  
Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.  
22, 23  
24, 25  
26, 27  
28 - 33  
AX1,AX2 X1 and X2 Address Lines (Inputs).  
AY0,AY1 Y0 and Y1 Address Lines (Inputs).  
NC  
No Connection.  
X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch  
array.  
34  
35  
36  
37  
38  
NC  
Y0  
NC  
Y1  
No Connection.  
Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.  
No Connection.  
Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.  
DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off  
the selected switch. Active High.  
39  
40  
Y2  
Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.  
V
Positive Power Supply.  
DD  
* Plastic DIP and CERDIP only.  
3-66  
ISO-CMOS MT093  
Functional Description  
Address Decode  
The MT093 is an analog switch matrix with an array  
size of 8 x 12. The switch array is arranged such that  
there are 8 columns by 12 rows. The columns are  
referred to as the Y input/output lines and the rows  
are the X input/output lines. The crosspoint analog  
switch array will interconnect any X line with any Y  
line when turned on and provide a high degree of  
isolation when turned off. The control memory  
consists of a 96 bit write only RAM in which the bits  
are selected by the address input lines (AY0-AY2,  
AX0-AX3). Data is presented to the memory on the  
DATA input line. Data is asynchronously written into  
memory whenever the STROBE input is high and is  
latched on the falling edge of STROBE. A logical “1”  
written into a memory cell turns the corresponding  
crosspoint switch on and a logical “0” turns the  
crosspoint off. Only the crosspoint switches  
corresponding to the addressed memory location are  
altered when data is written into memory. The  
remaining switches retain their previous states. Any  
combination of X and Y lines can be interconnected  
by establishing appropriate patterns in the control  
memory. A logical “1” on the RESET input line will  
asynchronously return all memory locations to logical  
“0” turning off all crosspoint switches.  
The seven address lines along with the STROBE  
input are logically ANDed to form an enable signal  
for the resettable transparent latches. The DATA  
input is buffered and is used as the input to all  
latches. To write to a location, RESET must be low  
while the address and data lines are set up. Then the  
STROBE input is set high and then low causing the  
data to be latched. The data can be changed while  
STROBE is high, however, the corresponding switch  
will turn on and off in accordance with the data. Data  
must be stable on the falling edge of STROBE in  
order for correct data to be written to the latch.  
3-67  
MT093 ISO-CMOS  
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.  
Parameter  
Symbol  
Min  
Max  
Units  
1
Supply Voltage  
V
V
-0.3  
-0.3  
16.0  
V
V
DD  
SS  
V
V
V
+0.3  
DD  
DD  
DD  
2
3
4
5
6
Analog Input Voltage  
Digital Input Voltage  
V
-0.3  
+0.3  
+0.3  
V
V
INA  
V
V
-0.3  
SS  
IN  
Current on any I/O Pin  
Storage Temperature  
I
±15  
mA  
°C  
T
-65  
+150  
S
Package Power Dissipation  
PLASTIC DIP  
CERDIP  
P
P
0.6  
1.0  
W
W
D
D
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.  
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated.  
Characteristics  
Sym  
Min  
Typ  
Max  
Units  
Test Conditions  
1
2
3
Operating Temperature  
Supply Voltage  
T
0
25  
70  
14.5  
3.5  
°C  
V
O
V
4.5  
DD  
Analog Input Voltage  
V
V
V
V
INA  
SS  
SS  
4
Digital Input Voltage  
V
V
V
IN  
DD  
DC Electrical Characteristics- Voltages are with respect to VSS=0V, VDD =14V unless otherwise stated.  
Characteristics  
Sym  
Min  
Typ  
Max  
Units  
Test Conditions  
1
Quiescent Supply Current  
I
1
100  
µA  
All digital inputs at V =V or  
DDQ  
IN  
SS  
V
DD  
7
15  
±1  
0.8  
mA  
µA  
V
All digital inputs at V =2.4V  
IN  
2
3
4
5
Off-state Leakage Current  
Input Logic “0” level  
I
IV - V I = V - V  
Xi Yj DD SS  
OFF  
V
IL  
Input Logic “1” level  
V
2.4  
V
IH  
Input Leakage (digital pins)  
I
10  
µA  
All digital inputs at V = V  
IN SS  
LEAK  
or V  
DD  
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.  
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.  
DC Electrical Characteristics- Switch Resistance - VIDC/VODC is the external DC offset applied at the analog  
I/O pins.  
Characteristics  
Sym  
25°C  
60°C  
70°C  
Units  
Test Conditions  
Typ Max Typ Max Typ Max  
1 On-state  
Resistance  
V
=14V  
R
45  
5
65  
10  
75  
10  
V =0V,  
SS  
DD  
ON  
IV -V I = 0.25V  
Xi Yj  
V
V
=6.75V  
IDC  
=6.5V  
ODC  
2 Difference in on-state  
resistance between two  
switches  
R  
10  
V
V
V
=14V, V =0,  
DD SS  
ON  
=6.75V  
IDC  
ODC  
=6.5V  
IV -V I = 0.25V  
Xi Yj  
3-68  
ISO-CMOS MT093  
AC Electrical Characteristics- Crosspoint Performance-VDC is the external DC offset applied at the analog  
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.  
Characteristics  
Sym  
Min  
Typ  
Max Units  
Test Conditions  
f=1 MHz  
f=1 MHz  
1
2
3
Switch I/O Capacitance  
Feedthrough Capacitance  
C
C
20  
0.2  
45  
pF  
pF  
S
F
Frequency Response  
Channel “ON”  
F
MHz Switch is “ON”; V  
= 2Vpp  
3dB  
INA  
sinewave; R = 1kΩ  
L
20LOG(V  
/V )=-3dB  
OUT Xi  
4
5
Total Harmonic Distortion  
THD  
FDT  
0.05  
-95  
%
Switch is “ON”; V  
INA  
sinewave f= 1kHz; R =1kΩ  
= 2Vpp  
L
Feedthrough  
dB  
All Switches “OFF”; V  
=
INA  
Channel “OFF”  
Feed.=20LOG (V  
2Vpp sinewave f= 1kHz;  
R = 1k.  
/V )  
OUT Xi  
L
6
Crosstalk between any two  
channels for switches Xi-Yi and  
Xj-Yj.  
X
-45  
-90  
-85  
-80  
dB  
dB  
dB  
dB  
ns  
V
=2Vpp sinewave  
INA  
talk  
f= 10MHz; R = 75.  
L
V
=2Vpp sinewave  
INA  
f= 10kHz; R = 600.  
L
Xtalk=20LOG (V /V ).  
Yj Xi  
V
=2Vpp sinewave  
INA  
f= 10kHz; R = 1k.  
L
V
=2Vpp sinewave  
INA  
f= 1kHz; R = 10k.  
L
7
Propagation delay through  
switch  
t
50  
R =1k; C =50pF  
L L  
PS  
† Timing is over recommended temperature range.  
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.  
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.  
AC Electrical Characteristics- Control and I/O Timings- VDC is the external DC offset applied at the analog  
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.  
Characteristics  
Sym  
Min  
Typ  
Max  
Units  
mVpp V =3V+V  
DC  
Test Conditions  
1
Control Input crosstalk to switch  
(for DATA, STROBE, Address)  
CX  
50  
squarewave;  
talk  
IN  
R =1k, R =10k.  
IN  
L
2
3
4
5
6
7
8
9
Digital Input Capacitance  
Switching Frequency  
C
F
10  
pF  
MHz  
ns  
f=1MHz  
DI  
10  
O
Setup Time DATA to STROBE  
Hold Time DATA to STROBE  
Setup Time Address to STROBE  
Hold Time Address to STROBE  
STROBE Pulse Width  
t
20  
20  
20  
20  
40  
80  
R = 1k, C =50pF  
L L  
DS  
t
ns  
R = 1k, C =50pF  
L L  
DH  
t
ns  
R = 1k, C =50pF  
L L  
AS  
t
ns  
R = 1k, C =50pF  
L L  
AH  
t
ns  
R = 1k, C =50pF  
L L  
SPW  
RPW  
RESET Pulse Width  
t
ns  
R = 1k, C =50pF  
L L  
10 STROBE to Switch Status Delay  
11 DATA to Switch Status Delay  
12 RESET to Switch Status Delay  
t
80  
100  
70  
200  
200  
200  
ns  
R = 1k, C =50pF  
L L  
S
t
ns  
R = 1k, C =50pF  
L L  
D
t
ns  
R = 1k, C =50pF  
L L  
R
† Timing is over recommended temperature range.  
Digital Input rise time (tr) and fall time (tf) = 10ns.  
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.  
3-69  
MT093 ISO-CMOS  
tRPW  
50%  
50%  
RESET  
tSPW  
STROBE  
50%  
50%  
50%  
tAS  
ADDRESS  
50%  
50%  
tAH  
DATA  
50%  
tDS  
50%  
tDH  
ON  
SWITCH  
OFF  
tR  
tR  
tS  
tD  
Figure 3 - Control Memory Timing Diagram  
AX0  
AX1  
AX2  
AX3  
AY0  
AY1  
AY2  
Connection  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X0-Y0  
X1-Y0  
X2-Y0  
X3-Y0  
X4-Y0  
X5-Y0  
No Connection  
No Connection  
X6-Y0  
X7-Y0  
X8-Y0  
X9-Y0  
X10-Y0  
X11-Y0  
No Connection  
No Connection  
0
1
0
0
0
1
0
1
1
1
0
0
0
0
X0-Y1  
↓ ↓  
X11-Y1  
X0-Y2  
↓ ↓  
X11-Y2  
X0-Y3  
↓ ↓  
X11-Y3  
X0-Y4  
↓ ↓  
X11-Y4  
X0-Y5  
↓ ↓  
X11-Y5  
X0-Y6  
↓ ↓  
X11-Y6  
X0-Y7  
↓ ↓  
0
1
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
1
1
X11-Y7  
Table 1. Address Decode Truth Table  
This address has no effect on device status.  
3-70  
配单直通车
MT06D0000产品参数
型号:MT06D0000
生命周期:Obsolete
Reach Compliance Code:unknown
风险等级:5.55
其他特性:VSWR MAX AT 2GHZ
连接器类型:RF TNC CONNECTOR
耦合类型:THREADED
DIN 符合性:NO
滤波功能:NO
IEC 符合性:NO
绝缘体材料:DELRIN
MIL 符合性:NO
制造商序列号:TNC
安装方式:STRAIGHT
安装类型:BOARD
最大工作频率:4 GHz
面板安装:NO
端接类型:SOLDER
电压驻波比:1.2
Base Number Matches:1
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