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产品型号MT28F016S5的Datasheet PDF文件预览

ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
FLASH MEMORY  
MT28F016S5  
5V Only, Dual Supply (Smart 5)  
FEATURES  
• Thirty-two 64KB erase blocks  
• Deep Power-Down Mode:  
10µA MAX  
PIN ASSIGNMENT (Top View)  
40-Pin TSOP Type I  
• Smart 5 technology:  
5V ±10% VCC  
5V ±10% VPP application/production  
programming  
12V VPP tolerant compatibility production  
programming  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
CE#  
1
2
3
4
5
6
7
8
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A20  
NC  
WE#  
OE#  
RY/BY#  
DQ7  
DQ6  
DQ5  
DQ4  
• Address access time: 90ns  
• Industry-standard pinouts  
• Inputs and outputs are fully TTL-compatible  
• Automated write and erase algorithm  
• Two-cycle WRITE/ERASE sequence  
9
V
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VCC  
VSS  
VSS  
V
PP  
RP#  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
OPTIONS  
• Timing  
MARKING  
DQ3  
DQ2  
DQ1  
DQ0  
A0  
A1  
A2  
A3  
90ns access  
-9  
• Package  
Plastic 40-pin TSOP Type 1 (10mm x 20mm) VG  
PartNumberExample:  
MT28F016S5VG-9  
GENERAL DESCRIPTION  
The MT28F016S5 is a nonvolatile, electrically block-  
erasable(flash),programmable,read-onlymemorycon-  
taining 2,097,152 bytes (8 bits). Writing or erasing the  
device is done with a 5V VPP voltage, while all opera-  
tions are performed with a 5V VCC. Due to process  
technology advances, 5V VPP is optimal for application  
and production programming. For backward compat-  
ibility with SmartVoltage technology, 12V VPP is sup-  
ported for a maximum of 100 cycles and may be  
connected for up to 100 cumulative hours. The device  
is fabricated with Micron’s advanced CMOS floating-  
gate process.  
The MT28F016S5 is organized into 32 separately  
erasable blocks. ERASEs may be interrupted to allow  
other operations with the ERASE SUSPEND command.  
After the ERASE SUSPEND command is issued, READ  
operations may be executed.  
Operations are executed with commands from an  
industry-standard command set. In addition to status  
register polling, the MT28F016S5 provides a ready/  
busy# (RY/BY#) output to indicate WRITE and ERASE  
completion.  
PleaserefertoMicron’sWebsite(www.micron.com/  
flash/htmls/datasheets.html) for the latest data sheet.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
1
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
FUNCTIONAL BLOCK DIAGRAM  
Input  
Buffer  
I/O  
Control  
Logic  
64KB Memory Block (0)  
Addr.  
Buffer/  
Latch  
64KB Memory Block (1)  
8
64KB Memory Block (2)  
21  
10  
A0-A20  
11  
Addr.  
Power  
(Current)  
Control  
Input  
Data  
Latch  
Counter  
DQ0-DQ7  
64KB Memory Block (29)  
64KB Memory Block (30)  
64KB Memory Block (31)  
8
Command  
Execution  
Logic  
CE#  
OE#  
WE#  
RP#  
State  
Machine  
Y -  
Decoder  
Y - Select Gates  
8
V
CC  
Sense Amplifiers  
Write/Erase-Bit  
VPP  
RY/BY#  
VPP  
Compare and Verify  
Switch/  
Pump  
Status  
Register  
Identification  
Register  
Output  
Buffer  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
2
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
PIN DESCRIPTIONS  
TSOP PIN  
NUMBERS  
SYMBOL  
TYPE  
DESCRIPTION  
38  
WE#  
Input  
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,  
the cycle is either a WRITE to the command execution logic (CEL) or to the  
memory array.  
9
CE#  
RP#  
Input  
Input  
Chip Enable: Activates the device when LOW. When CE# is HIGH, the  
device is disabled and goes into standby power mode.  
12  
Reset/Power-Down: When LOW, RP# clears the status register, sets the  
internal state machine (ISM) to the array read mode and places the device  
in deep power-down mode. All inputs, including CE#, are “Don’t Care,”  
and all outputs are High-Z. RP# must be held at VIH during all other modes  
of operation.  
37  
OE#  
Input  
Input  
Output Enable: Enables data output buffers when LOW. When OE# is  
HIGH, the output buffers are disabled.  
24, 23, 22, 21,  
20, 19, 18, 17,  
16, 15, 14, 13,  
8, 7, 6, 5, 4, 3,  
2, 1, 40  
A0-A20  
Address Inputs: Select a unique, 8-bit byte out of the 2,097,152  
available.  
25-28,  
32-35  
DQ0-DQ7  
RY/BY#  
Input/  
Data I/Os: Data output pins during any READ operation or data input  
Output pins during a WRITE. Used to input commands to the CEL.  
36  
Output Ready/Busy: Indicates the status of the ISM. When RY/BY# = VOL, the ISM is  
busy processing a command. If RY/BY# = VOH, the ISM is ready to accept a  
new command. During deep power-down, device configuration read or  
erase suspend, RY/BY# = VOH. Output is always active.  
11  
VPP  
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until  
completion of the operation, VPP must be at VPPH (5V) (VPP • VCC). VPP =  
“Don’t Care” during all other operations.  
10, 31  
29, 30  
39  
VCC  
VSS  
NC  
Supply Power Supply: +5V ±10%.  
Supply Ground.  
No Connect: This pin may be driven or left unconnected.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
3
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
1
TRUTH TABLE  
FUNCTION  
RP#  
H
CE#  
H
OE#  
X
WE#  
X
ADDRESS  
V
PP  
DQ0-DQ7  
High-Z  
RY/BY#  
Standby  
X
X
X
VOH  
Deep Power-Down/Reset  
READ  
L
X
X
X
X
High-Z  
VOH  
READ  
H
H
L
L
L
H
H
X
X
X
X
Data-Out  
High-Z  
V
OH  
OH  
Output Disable  
H
V
2, 3  
WRITE/ERASE  
ERASE SETUP  
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
X
BA  
X
X
20H  
D0H  
V
OH  
4
ERASE CONFIRM  
VPPH  
V
V
OH Æ VOL  
OH  
WRITE SETUP  
X
10H/40H  
Data-In  
FFH  
V
5
WRITE  
WA  
X
VPPH  
OH Æ VOL  
6
READ ARRAY  
X
VOH  
DEVICE CONFIGURATION  
Manufacturer Compatibility ID  
Device ID  
H
H
L
L
L
L
H
H
000000H  
000001H  
X
X
89H  
A0H  
V
OH  
OH  
V
NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).  
2. VPPH = 5V.  
3. BA = Block Address; WA = Write Address.  
4. Operation must be preceded by ERASE SETUP command.  
5. Operation must be preceded by WRITE SETUP command.  
6. The READ ARRAY command must be issued before reading the array after writing or erasing.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
4
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
FUNCTIONAL DESCRIPTION  
TheMT28F016S5flashmemoryincorporatesanum-  
ber of features that make it ideally suited for system  
firmware or data storage. The memory array is seg-  
mented into individual erase blocks. Each block may be  
erased without affecting data stored in other blocks.  
These memory blocks are read, written and erased by  
issuing commands to the command execution logic  
(CEL). The CEL controls the operation of the internal  
state machine (ISM), which completely controls all  
WRITE, BLOCK ERASE andVERIFYoperations. The ISM  
protects each memory location from over-erasure and  
optimizes each memory location for maximum data  
retention. In addition, the ISM greatly simplifies the  
control necessary for writing the device in-system or in  
an external programmer.  
INTERNAL STATE MACHINE (ISM)  
BLOCK ERASE and WRITE timing are simplified  
with an ISM that controls all erase and write algorithms  
inthememoryarray.TheISMensuresprotectionagainst  
over-erasure and optimizes write margin to each cell.  
During WRITE operations, the ISM automatically  
incrementsandmonitorsWRITEattempts,verifieswrite  
marginoneachmemorycellandupdatestheISMstatus  
register. When a BLOCK ERASE is performed, the ISM  
automatically overwrites the entire addressed block  
(eliminates overerasure), increments and monitors  
ERASE attempts, and sets bits in the ISM status register.  
ISM STATUS REGISTER  
The ISM status register allows an external processor  
to monitor the status of the ISM during WRITE and  
ERASE operations. Two bits of the 8-bit status register  
are set and cleared entirely by the ISM. These two bits  
indicate whether the ISM is busy with an ERASE or  
WRITE task and when an ERASE has been suspended.  
Additional error information is set in three other bits:  
VPP status, erase status and write status. These three bits  
must be cleared by the host system.  
The Functional Description provides detailed infor-  
mation on the operation of the MT28F016S5 and is  
organized into these sections:  
• Overview  
• Memory Architecture  
• Output (READ) Operations  
• Input Operations  
• Command Set  
• ISM Status Register  
• Device Configuration Registers  
• Command Execution  
• Error Handling  
• WRITE/ERASE Cycle Endurance  
• Power Usage  
READY/BUSY# (RY/BY#) OUTPUT  
Inadditiontostatusregisterpolling,theMT28F016S5  
provides an asynchronous RY/BY# output to indicate  
the status of the ISM. RY/BY# is VOH when the state  
machine is inactive and VOL during a WRITE or ERASE  
operation. This output is always active.  
• Power-Up  
COMMAND EXECUTION LOGIC (CEL)  
The CEL receives and interprets commands to the  
device. These commands control the operation of the  
ISM and the read path (i.e., memory array, device  
configuration or status register). Commands may be  
issued to the CEL while the ISM is active. However,  
there are restrictions on what commands are allowed in  
thiscondition. SeetheCommandExecutionsectionfor  
more detail.  
OVERVIEW  
SMART 5 TECHNOLOGY  
Smart 5 technology allows maximum flexibility for  
in-system READ, WRITE and ERASE operations. For 5V-  
only systems, WRITE and ERASE operations may be  
executed with a VPP voltage of 5V. Due to process  
technology advances, 5V VPP is optimal for application  
and production programming. For backward compat-  
ibility with SmartVoltage technology, 12V VPP is sup-  
ported for a maximum of 100 cycles and may be  
connected for up to 100 cumulative hours. However,  
no performance increase is realized. For any operation,  
VCC is at 5V.  
DEEP POWER-DOWN MODE  
To allow for maximum power conservation, the  
MT28F016S5 features a very low current, deep power-  
down mode. To enter this mode, the RP# pin is taken to  
VSS ±0.2V. In this mode, the current draw is a maximum  
of 10µA. Entering deep power-down also clears the  
status register and sets the ISM to the read array mode.  
THIRTY-TWO INDEPENDENTLY ERASABLE  
MEMORY BLOCKS  
The MT28F016S5 is organized into 32 indepen-  
dently erasable memory blocks that allow portions of  
the memory to be erased without affecting the rest of  
the memory data.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
5
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
MEMORY ARCHITECTURE  
The MT28F016S5 memory array architecture is de-  
signed to allow sectors to be erased without disturbing  
the rest of the array. The array is divided into 32  
addressable blocks that are independently erasable.  
When blocks rather than the entire array are erased, the  
total device endurance is enhanced, as is system flex-  
ibility. Only the ERASE functions are block-oriented.  
All READ and WRITE operations are done on a random-  
access basis. Figure 1 illustrates the memory address  
map.  
CE# goes HIGH, whichever occurs first. The DQ pins  
will continue to output new data after each address  
transition as long as OE# and CE# remain LOW.  
After power-up or RESET, the device will automati-  
callybeinthearrayreadmode. Allcommandsandtheir  
operations are covered in the Command Set and Com-  
mand Execution sections.  
STATUS REGISTER  
Performing a READ of the status register requires the  
same input sequencing as a READ of the array except  
that the address inputs are “Don’t Care.” Data from the  
status register is latched on the falling edge of OE# or  
CE#, whichever occurs last. If the contents of the status  
register change during a READ of the status register,  
either OE# or CE# may be toggled while the other is  
held LOW to update the output.  
Following a WRITE or ERASE operation, the device  
automatically enters the status register read mode. In  
addition, a READ during a WRITE or ERASE operation  
will produce the status register contents on DQ0-DQ7.  
When the device is in ERASE SUSPEND mode, a READ  
operationwillproducethestatusregistercontentsuntil  
another command is issued. While the device is in  
certain other modes, READ STATUS REGISTER may be  
given to return to the status register read mode. All  
commands and their operations are covered in the  
Command Set and Command Execution sections.  
OUTPUT (READ) OPERATIONS  
The MT28F016S5 features three different types of  
READs. Depending on the current mode of the device,  
a READ operation will produce data from the memory  
array, status register or one of the device configuration  
registers. In each of these three cases, the WE#, CE# and  
OE# inputs are controlled in a similar manner. Moving  
between modes to perform a specific READ will be  
covered in the Command Execution section.  
MEMORY ARRAY  
To read the memory array, WE# must be HIGH, and  
OE# and CE# must be LOW. Valid data will be output  
on the DQ pins once these conditions have been met  
and a valid address is given. Valid data will remain on  
the DQ pins until the address changes, or until OE# or  
DEVICE CONFIGURATION REGISTERS  
0
64KB  
64KB  
Reading any of the device configuration registers  
requires the same input sequencing as reading the  
status register except that specific addresses must be  
issued. WE# must be HIGH, and OE# and CE# must be  
LOW. To read the manufacturer compatibility ID, ad-  
dresses must be at 000000H, and to read the device ID,  
addresses must be at 000001H.  
While the device is in certain other modes, READ  
DEVICE CONFIGURATION may be given to return to  
the configuration registers read mode. All commands  
and their operations are covered in the Command Set  
and Command Execution sections.  
16Mb  
31  
64KB  
Figure 1  
Memory Address Map  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
6
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
INPUT OPERATIONS  
COMMAND SET  
The DQ pins are used either to input data to the  
array or to input a command to the CEL. A command  
inputissuesan8-bitcommandtotheCELtocontrolthe  
mode of operation of the device. A WRITE is used to  
input data to the memory array. The following section  
describes both types of inputs. More information de-  
scribing how to use the two types of inputs to write or  
erasethedeviceisprovidedintheCommandExecution  
section.  
To simplify writing of the memory blocks, the  
MT28F016S5 incorporates an ISM that controls all  
internal algorithms for the WRITE and ERASE cycles.  
An 8-bit command set is used to control the device.  
Details on how to sequence commands are provided in  
the Command Execution section. Table 1 lists the valid  
commands.  
ISM STATUS REGISTER  
The 8-bit ISM status register (see Table 2) is polled to  
check for WRITE or ERASE completion or any related  
errors. During or following a WRITE, ERASE or ERASE  
SUSPEND, a READ operation will output the status  
register contents on DQ0-DQ7 without prior com-  
mand. While the status register contents are read, the  
outputs will not be updated if there is a change in the  
ISM status unless OE# or CE# is toggled. If the device is  
not in the write, erase, erase suspend, status register or  
read mode, READ STATUS REGISTER (70H) can be  
issued to view the status register contents.  
All of the defined bits are set by the ISM, but only the  
ISM and erase suspend status bits are reset by the ISM.  
The erase, write and VPP status bits must be cleared  
using CLEAR STATUS REGISTER (50H). This allows the  
user to choose when to poll and clear the status register.  
For example, the host system may perform multiple  
WRITE operations before checking the status register  
instead of checking after each individual WRITE. As-  
serting the RP# signal or powering down the device will  
also clear the status register.  
COMMANDS  
To perform a command input, OE# must be HIGH,  
and CE# and WE# must be LOW. Addresses are “Don’t  
Care” but must be held stable, except during an ERASE  
CONFIRM. The 8-bit command is input on DQ0-DQ7  
and is latched on the rising edge of CE# (CE#-con-  
trolled) or WE# (WE#-controlled), whichever occurs  
first.  
MEMORY ARRAY  
A WRITE to the memory array sets the desired bits to  
logic 0s but cannot change a given bit to a logic 1 from  
a logic 0. Setting any bits to a logic 1 requires that the  
entire block be erased. To perform a WRITE, OE# must  
be HIGH, CE# and WE# must be LOW, and VPP must be  
set to VPPH (5V). A0-A20 provide the address to be  
written, whilethedatatobewrittentothearrayisinput  
on the DQ pins. The data and addresses are latched on  
the rising edge of either CE# (CE#-controlled) or WE#  
(WE#-controlled),whicheveroccursfirst.AWRITEmust  
be preceded by a WRITE SETUP command. Details on  
how to input data to the array will be covered in the  
Write Sequence section.  
DEVICE CONFIGURATION REGISTERS  
The device ID and manufacturer compatibility ID  
can be read by issuing READ DEVICE CONFIGURA-  
TION (90H). To read the desired register, a specific  
address must be asserted. See Table 3 for more details on  
the various device configuration registers.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
7
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
Table 1  
Command Set  
COMMAND  
HEX CODE  
DESCRIPTION  
RESERVED  
00H  
FFH  
90H  
This command and all unlisted commands are invalid and  
should not be called. These commands are reserved to allow  
for future feature enhancements.  
READ ARRAY  
Must be issued after any other command cycle before the  
array can be read. It is not necessary to issue this command  
after power-up or RESET.  
READ DEVICE CONFIGURATION  
Allows the device ID and manufacturer ID to be read. Please  
refer to Table 3 for more information on the various device  
configuration registers.  
READ STATUS REGISTER  
CLEAR STATUS REGISTER  
ERASE SETUP  
70H  
50H  
20H  
Allows the status register to be read. Please refer to Table 2  
for more information on the status register bits.  
Clears status register bits 3-5, which cannot be cleared by the  
ISM.  
The first command given in the two-cycle ERASE sequence.  
The ERASE will not be completed unless followed by ERASE  
CONFIRM.  
ERASE CONFIRM  
D0H  
The second command given in the two-cycle ERASE se-  
quence. Must follow an ERASE SETUP to be valid. Also used  
during a WRITE/ERASE SUSPEND to resume the WRITE or  
ERASE.  
WRITE SETUP  
40H or  
10H  
The first command given in the two-cycle WRITE sequence.  
The write data and address are given in the following cycle  
to complete the WRITE.  
ERASE SUSPEND  
B0H  
Requests a halt of the ERASE and puts the device into the  
erase suspend mode. When the device is in this mode, only  
READ STATUS REGISTER, READ ARRAY and ERASE CONFIRM  
(ERASE RESUME) commands may be executed.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
8
©2000, Micron Technology, Inc.  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
Table 2  
Status Register  
STATUS  
BIT #  
STATUS REGISTER BIT  
DESCRIPTION  
SR7  
ISM STATUS  
1 = Ready  
0 = Busy  
The ISMS bit displays the active status of the state machine  
during WRITE or BLOCK ERASE operations. The controlling  
logic polls this bit to determine when the erase and write  
status bits are valid.  
SR6  
SR5  
ERASE SUSPEND STATUS  
1 = ERASE suspended  
0 = ERASE in progress/completed  
Issuing an ERASE SUSPEND places the ISM in the suspend  
mode and sets this and the ISMS bit to “1.” The ESS bit will  
remain “1” until an ERASE CONFIRM is issued.  
ERASE STATUS  
1 = BLOCK ERASE error  
0 = Successful BLOCK ERASE  
ES is set to “1” after the maximum number of ERASE cycles is  
executed by the ISM without a successful verify. ES is only  
cleared by a CLEAR STATUS REGISTER command or by a  
RESET.  
SR4  
SR3  
WRITE STATUS  
1 = WRITE error  
0 = Successful WRITE  
WS is set to “1” after the maximum number of WRITE cycles  
is executed by the ISM without a successful verify. WS is only  
cleared by a CLEAR STATUS REGISTER command or by a  
RESET.  
VPP STATUS  
1 = No VPP voltage detected  
0 = VPP present  
VPPS detects the presence of a VPP voltage. It does not  
monitor VPP continuously, nor does it indicate a valid VPP  
voltage. The VPP pin is sampled for 5V after WRITE or ERASE  
CONFIRM is given. VPPS must be cleared by CLEAR STATUS  
REGISTER or by a RESET.  
SR0-2  
RESERVED  
Reserved for future use.  
Table 3  
Device Configuration  
DEVICE CONFIGURATION  
Manufacturer Compatibility ID  
Device ID  
ADDRESS  
000000H  
000001H  
DATA  
89H  
CONDITION  
Manufacturer compatibility ID read  
Device ID read  
A0H  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
9
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
COMMAND EXECUTION  
Commands are issued to bring the device into  
different operational modes. Each mode allows specific  
operations to be performed. Several modes require a  
sequence of commands to be written before they are  
reached. The following section describes the properties  
of each mode, and Table 4 lists all command sequences  
required to perform the desired operation.  
desired information. The manufacturer compatibility  
ID is read at 000000H, and the device ID is read at  
000001H.  
WRITE SEQUENCE  
Two consecutive cycles are needed to input data to  
the array. WRITE SETUP (40H or 10H) is given in the  
first cycle. The next cycle is the WRITE, during which  
the write address and data are issued and VPP is brought  
to VPPH. The ISM will now begin to write the byte. VPP  
must be held at VPPH until the WRITE is completed (SR7  
= 1 and RY/BY# = VOH).  
While the ISM executes the WRITE, the ISM status  
bit (SR7) will be at “0” and RY/BY# = VOL, and the device  
will not respond to any commands. Any READ opera-  
tion will produce the status register contents on DQ0-  
DQ7. WhentheISMstatusbit(SR7)issettoalogic1and  
RY/BY# = VOH, the WRITE has been completed, and the  
device will go into the status register read mode until  
another command is given.  
READ ARRAY  
The array read mode is the initial state of the device  
upon power-up and is also entered after a RESET. If the  
device is in any other mode, READ ARRAY (FFH) must  
be given to return to the array read mode. Unlike the  
WRITE SETUP command (40H), READ ARRAY does not  
need to be given before each individual read access.  
DEVICE CONFIGURATION  
To read the device ID and manufacturer compatibil-  
ity ID, the READ DEVICE CONFIGURATION (90H)  
command must be issued. While the device is in this  
mode, specific addresses must be issued to read the  
Table 4  
Command Sequences  
BUS  
1ST  
2ND  
CYCLES  
CYCLE  
CYCLE  
COMMANDS  
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA  
NOTES  
READ ARRAY  
1
2
2
1
2
2
2
2
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
X
X
X
X
X
X
X
X
FFH  
90H  
70H  
50H  
20H  
B0H  
40H  
10H  
1
2, 3  
4
READ DEVICE CONFIGURATION  
READ STATUS REGISTER  
CLEAR STATUS REGISTER  
ERASE SETUP/CONFIRM  
ERASE SUSPEND/RESUME  
WRITE SETUP/WRITE  
ALTERNATE WRITE  
READ  
READ  
CA  
X
CD  
SRD  
WRITE  
WRITE  
WRITE  
WRITE  
BA  
X
D0H  
D0H  
WD  
WD  
5, 6  
WA  
WA  
6, 7  
6, 7  
NOTE: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable flash array READ cycles.  
2. CA = Configuration Address: 00000H for manufacturer compatibility ID and 00001H for device ID.  
3. CD = Configuration Data.  
4. SRD = Status Register Data.  
5. BA = Block Address.  
6. Addresses are “Don’t Care” in first cycle but must be held stable.  
7. WA = Address to be written; WD = Data to be written to WA.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
10  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
ERASE SEQUENCE  
Executing an ERASE sequence will set all bits within  
a block to logic 1. The command sequence necessary to  
execute an ERASE is similar to that of a WRITE. To  
provide added security against accidental block era-  
sure, two consecutive command cycles are required to  
initiate an ERASE of a block. In the first cycle, addresses  
are “Don’t Care,” and ERASE SETUP (20H) is given. In  
the second cycle, VPP is brought to VPPH, an address  
within the block to be erased is issued, and ERASE  
CONFIRM (D0H) is given. If a command other than  
ERASECONFIRMisgiven, thewriteanderasestatusbits  
(SR4 and SR5) will be set, and the device will be in the  
read status mode.  
After the ERASE CONFIRM (D0H) is issued, the ISM  
will start the ERASE of the addressed block. Any READ  
operation will output the status register contents on  
DQ0-DQ7. VPP must be held at VPPH until the ERASE is  
completed (SR7 = 1 and RY/BY# = VOH). Once the ERASE  
is completed, the device will be in the status register  
read mode until another command is issued.  
ported for a maximum of 100 cycles and may be  
connected for up to 100 cumulative hours. Operation  
outside these limits may reduce the number of WRITE  
and ERASE cycles that can be performed on the device.  
POWER USAGE  
The MT28F016S5 offers several power-saving fea-  
tures that may be utilized in the array read mode to  
conserve power. Deep power-down mode is enabled by  
bringing RP# to VSS ±0.2V. Current draw (ICC) in this  
mode is a maximum of 10µA. When CE# is HIGH, the  
device will enter standby mode. In this mode, maxi-  
mum ICC current is 100µA. If CE# is brought HIGH  
during a WRITE or ERASE, the ISM will continue to  
operate, and the device will consume the respective  
active power until the WRITE or ERASE is completed.  
POWER-UP  
The likelihood of unwanted WRITE or ERASE opera-  
tions is minimized since two consecutive cycles are  
required to execute either operation. However, to reset  
the ISM and to provide additional protection while VCC  
is ramping, one of the following conditions must be  
met:  
ERASE SUSPENSION  
The only command that may be issued while an  
ERASE is in progress is ERASE SUSPEND. This command  
allows other commands to be executed while pausing  
the ERASE in progress. Once the device has reached the  
suspend mode, the erase suspend status bit (SR6) and  
ISM status bit (SR7) will be set and RY/BY# will transi-  
tion to VOH. The device may now be given a READ  
ARRAY, ERASE RESUME or READ STATUS REGISTER  
command. After READ ARRAY has been issued, any  
location not within the block being erased may be read.  
If ERASE RESUME is issued before SR6 has been set, the  
device will immediately proceed with the ERASE in  
progress. During anERASE SUSPEND, VPP and RP# must  
remain at the same levels used for the ERASE.  
• RP# must be held LOW until VCC is at valid func-  
tional level; or  
• CE# or WE# may be held HIGH and  
RP# must be toggled from VCC-GND-VCC.  
Afterapower-uporRESET, thestatusregisterisreset,  
and the device will enter the array read mode.  
RP#  
Note 1  
VCC  
(5V)  
t
AA  
ERROR HANDLING  
After the ISM status bit (SR7) has been set, VPP (SR3),  
write (SR4) and erase (SR5) status bits may be checked.  
If one or a combination of these four bits has been set,  
an error has occurred. The ISM cannot reset these four  
bits. To clear these bits, CLEAR STATUS REGISTER  
(50H) must be given. Table 6 lists the combination of  
errors.  
Address  
VALID  
VALID  
Data  
t
RWH  
UNDEFINED  
WRITE/ERASE CYCLE ENDURANCE  
The MT28F016S5 is designed and fabricated to meet  
advanced firmware and data storage requirements. To  
ensure this level of reliability, VPP must be at 5V ±10%  
during WRITE or ERASE cycles. For SmartVoltage-  
compatible production programming, 12V VPP is sup-  
NOTE: 1. VCC must be within the valid operating range before RP#  
goes HIGH.  
Figure 2  
Power-Up/Reset Timing Diagram  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
11  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
Table 6  
1
Status Register Error Decode  
STATUS BITS  
SR5  
SR4  
0
SR3  
ERROR DESCRIPTION2  
0
0
0
0
1
1
1
0
1
0
1
0
1
0
No errors  
0
VPP voltage error  
1
WRITE error  
1
WRITE error, VPP voltage not valid  
ERASE error  
0
0
ERASE error, VPP voltage not valid  
Command sequencing error  
1
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.  
2. SR3-SR4 reflect noncumulative results.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
12  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
1
SELF-TIMED WRITE SEQUENCE  
COMPLETE WRITE STATUS-CHECK  
SEQUENCE  
Start (WRITE completed)  
Start  
NO  
NO  
4, 5  
V
PP Error  
WRITE 40H or 10H  
SR3 = 0?  
YES  
V
PP = 5V  
5
V
PP  
V
CC  
SR4 = 0?  
YES  
WRITE Error  
WRITE Byte  
Address/Data  
WRITE Successful  
STATUS REGISTER  
READ  
NO  
SR7 = 1?  
YES  
2
Complete Status  
Check (optional)  
3
WRITE Complete  
NOTE: 1. Sequence may be repeated for additional WRITEs.  
2. Complete status check is not required.  
3. Device will be in status register read mode. To return to the array read mode, the FFH command must be issued.  
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER (50H) should be issued before further  
WRITE or ERASE operations are attempted.  
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
13  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
1
SELF-TIMED BLOCK ERASE SEQUENCE  
COMPLETE BLOCK ERASE  
STATUS-CHECK SEQUENCE  
Start (BLOCK ERASE completed)  
Start  
NO  
5, 6  
WRITE 20H  
VPP Error  
SR3 = 0?  
YES  
VPP = 5V  
VPP VCC  
YES  
NO  
6
SR4, 5 = 1?  
Command Sequence Error  
WRITE D0H,  
Block Address  
SR5 = 0?  
BLOCK ERASE  
YES  
STATUS REGISTER  
or RY/BY# Polling  
ERASE Successful  
NO  
NO  
SR7 = 1?  
YES  
Suspend ERASE?  
YES  
4
2
Suspend  
Sequence  
Complete Status  
Check (optional)  
ERASE Resumed  
3
ERASE Complete  
NOTE: 1. Sequence may be repeated to erase additional blocks.  
2. Complete status check is not required.  
3. To return to the array read mode, the FFH command must be issued.  
4. Refer to the ERASE SUSPEND flowchart for more information.  
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER (50H) should be issued before further  
WRITE or ERASE operations are attempted.  
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
14  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
ERASE SUSPEND SEQUENCE  
Start (ERASE in progress)  
WRITE B0H  
(ERASE SUSPEND)  
V
V
PP = 5V  
PP  
VCC  
STATUS REGISTER  
READ  
NO  
NO  
SR7 = 1?  
YES  
SR6 = 1?  
YES  
ERASE Completed  
WRITE FFH  
(READ ARRAY)  
Done  
NO  
Reading?  
YES  
WRITE D0H  
(ERASE RESUME)  
Resume ERASE  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
15  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
*Stresses greater than those listed under “Absolute  
Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only, and functional  
operation of the device at these or any other conditions  
above those indicated in the operational sections of  
this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may  
affect reliability.  
ABSOLUTE MAXIMUM RATINGS*  
Voltage on VCC Supply  
Relative to VSS ............................. -0.5V to +6V**  
Input Voltage Relative to VSS ................ -0.5V to +6V**  
VPP Voltage Relative to VSS ................. -0.5V to +12.6V†  
Temperature Under Bias ...................... -10°C to +80°C  
Storage Temperature (plastic) ............ -55°C to +125°C  
Power Dissipation ................................................... 1W  
**VCC, input and I/O pins may transition to -2V for  
<20ns and VCC + 2V for <20ns.  
Voltage may pulse to -2V for <20ns and 14V for <20ns.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ  
OPERATING CONDITIONS  
(0°C £ TA £ +70°C)  
PARAMETER/CONDITION  
SYMBOL  
VCC  
MIN  
4.5  
2
MAX  
5.5  
UNITS NOTES  
5V Supply Voltage  
V
V
V
1
1
1
Input High (Logic 1) Voltage, all inputs  
Input Low (Logic 0) Voltage, all inputs  
VIH  
VCC + 0.5  
0.8  
VIL  
-0.5  
DC OPERATING CHARACTERISTICS  
(0°C £ TA £ +70°C)  
PARAMETER/CONDITION  
SYMBOL  
MIN  
MAX UNITS NOTES  
OUTPUT VOLTAGE LEVELS (TTL)  
Output High Voltage (IOH = -2.5mA)  
Output Low Voltage (IOL = 5.8mA)  
VOH1  
2.4  
V
1
1
VOL  
0.45  
V
V
OUTPUT VOLTAGE LEVELS (CMOS)  
Output High Voltage (IOH = -100µA)  
VOH2  
VCC - 0.4  
INPUT LEAKAGE CURRENT  
Any input (0V £ VIN £ VCC);  
All other pins not under test = 0V  
IL  
-1  
1
µA  
µA  
OUTPUT LEAKAGE CURRENT  
IOZ  
-10  
10  
(DOUT is disabled; 0V £ VOUT £ VCC)  
NOTE: 1. All voltages referenced to VSS.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
16  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
CAPACITANCE  
(TA = +25°C; f = 1 MHz)  
PARAMETER/CONDITION  
Input Capacitance  
SYMBOL MAX  
UNITS NOTES  
CI  
8
pF  
pF  
Output Capacitance  
CO  
12  
READ AND STANDBY CURRENT DRAIN  
(0°C £ TA £ +70°C; VCC = +5V ±10%)  
PARAMETER/CONDITION  
SYMBOL TYP  
MAX UNITS NOTES  
READ CURRENT: TTL INPUT LEVELS  
(CE# = VIL; OE# = VIH; f = 8 MHz; Other inputs = VIL or VIH; RP# = VIH)  
ICC1  
ICC2  
ICC3  
ICC4  
8
50  
35  
2
mA  
mA  
mA  
µA  
1, 2  
READ CURRENT: CMOS INPUT LEVELS  
(CE# £ 0.2V; OE# • VCC - 0.2V; f = 8 MHz; Other inputs £ 0.2V  
or • VCC - 0.2V; RP# = VCC - 0.2V)  
5
1, 2  
STANDBY CURRENT: TTL INPUT LEVELS  
VCC power supply standby current  
(CE# = RP# = VIH; Other inputs = VIL or VIH)  
0.2  
65  
STANDBY CURRENT: CMOS INPUT LEVELS  
VCC power supply standby current  
(CE# = RP# = VCC - 0.2V)  
100  
DEEP POWER-DOWN CURRENT: VCC SUPPLY (RP# = VSS ±0.2V)  
STANDBY OR READ CURRENT: VPP SUPPLY (VPP • VCC)  
ICC5  
IPP1  
IPP2  
1
±2  
2
20  
±15  
5
µA  
µA  
µA  
DEEP POWER-DOWN CURRENT: VPP SUPPLY (RP# = VSS ±0.2V)  
NOTE: 1. ICC is dependent on cycle rates.  
2. ICC is dependent on output loading. Specified values are obtained with the outputs open.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
17  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
READ TIMING PARAMETERS  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS  
(0°C £ TA £ +70°C; VCC = +5V ±10%)  
AC CHARACTERISTICS  
-9  
PARAMETER  
READ cycle time  
Access time from CE#  
Access time from OE#  
Access time from address  
RP# HIGH to output valid delay  
OE# or CE# HIGH to output in High-Z  
Output hold time from OE#, CE# or address change  
SYMBOL  
MIN  
90  
MAX  
UNITS NOTES  
ns  
t
RC  
ACE  
AOE  
AA  
t
90  
45  
90  
400  
20  
ns  
ns  
ns  
ns  
ns  
ns  
1
1
t
t
t
RWH  
t
OD  
t
OH  
0
t
t
t
NOTE: 1. OE# may be delayed by ACE minus AOE after CE# falls before ACE is affected.  
AC TEST CONDITIONS  
Input pulse levels ............................................... 0.4V to 2.4V  
Input rise and fall times ................................................ <10ns  
Input timing reference level .............................. 0.8V and 2V  
Output timing reference level........................... 0.8V and 2V  
Output load ................................. 1 TTL gate and CL = 100pF  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
18  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
READ CYCLE  
VIH  
VIL  
A0-A20  
VALID ADDRESS  
t
RC  
t
AA  
VIH  
VIL  
CE#  
t
ACE  
VIH  
VIL  
OE#  
WE#  
VIH  
VIL  
t
OD  
t
t
AOE  
OH  
VIH  
VIL  
VALID DATA  
DQ0-DQ7  
t
RWH  
VIH  
VIL  
RP#  
DON’T CARE  
UNDEFINED  
TIMING PARAMETERS  
-9  
-9  
SYMBOL  
MIN  
MAX UNITS  
SYMBOL  
MIN  
MAX UNITS  
t
t
RC  
90  
ns  
RWH  
400  
20  
ns  
ns  
ns  
t
t
ACE  
90  
45  
90  
ns  
ns  
ns  
OD  
t
t
AOE  
OH  
0
t
AA  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
19  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
RECOMMENDED DC WRITE/ERASE CONDITIONS  
(0°C £ TA £ +70°C; VCC = +5V ±10%)  
PARAMETER/CONDITION  
SYMBOL MIN  
MAX UNITS NOTES  
VPP WRITE/ERASE lockout voltage  
VPP voltage during WRITE/ERASE operation  
VCC WRITE/ERASE lockout voltage  
VPPLK  
VPPH  
VLKO  
4.5  
2
1.5  
5.5  
V
V
V
1
2
WRITE/ERASE CURRENT DRAIN  
(0°C £ TA £ +70°C; VCC = +5V ±10%; VPP = +5V ±10% [Note 2])  
PARAMETER/CONDITION  
SYMBOL MAX UNITS NOTES  
WRITE CURRENT: VCC SUPPLY  
WRITE CURRENT: VPP SUPPLY  
ERASE CURRENT: VCC SUPPLY  
ERASE CURRENT: VPP SUPPLY  
ICC6  
IPP3  
ICC7  
IPP4  
ICC8  
35  
40  
30  
20  
10  
mA  
mA  
mA  
mA  
mA  
3
3
3
3
ERASE SUSPEND CURRENT: VCC SUPPLY  
(ERASE suspended)  
3, 4  
ERASE SUSPEND CURRENT: VPP SUPPLY  
(ERASE suspended)  
IPP5  
200  
µA  
NOTE: 1. Absolute WRITE/ERASE protection when VPP £ VPPLK.  
2. For SmartVoltage-compatible production programming, 12V VPP is supported for a maximum of 100 cycles and may  
be connected for up to 100 cumulative hours.  
3. Sampled, not tested, 100%.  
4. Parameter is specified when device is not accessed. Actual current draw will be ICC8 (5V VCC) plus current of operation  
being executed while the device is in suspend mode.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
20  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND  
RECOMMENDED AC OPERATING CONDITIONS:  
WE# (CE#)-CONTROLLED WRITES  
(0°C £ TA £ +70°C; VCC = +5V ±10%)  
AC CHARACTERISTICS  
PARAMETER  
WRITE cycle time  
WE# (CE#) HIGH pulse width  
WE# (CE#) pulse width  
Address setup time to WE# (CE#) HIGH  
Address hold time from WE# (CE#) HIGH  
Data setup time to WE# (CE#) HIGH  
Data hold time from WE# (CE#) HIGH  
CE# (WE#) setup time to WE# (CE#) LOW  
CE# (WE#) hold time from WE# (CE#) HIGH  
VPP setup time to WE# (CE#) HIGH  
RP# HIGH to WE# (CE#) LOW delay  
WRITE duration  
-9  
MIN  
90  
25  
50  
40  
5
40  
5
0
SYMBOL  
UNITS NOTES  
t
WC  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ms  
ns  
ns  
ns  
ns  
t
t
WPH ( CPH)  
t
t
WP ( CP)  
t
AS  
AH  
DS  
DH  
t
t
t
t
t
CS ( WS)  
t
t
CH ( WH)  
0
t
VPS  
RS  
WED1  
WED2  
WR  
VPH  
RYBY  
WB  
100  
1,000  
6
600  
0
0
90  
200  
t
t
t
BLOCK ERASE duration  
WRITE recovery to READ  
VPP hold time from status data valid, RY/BY# HIGH  
WE# (CE#) HIGH to RY/BY# LOW  
WE# (CE#) HIGH to busy status (SR7 = 0)  
t
t
t
t
WRITE AND ERASE DURATION CHARACTERISTICS  
5V VPP  
PARAMETER  
TYP  
8
MAX  
UNITS NOTES  
WRITE time  
TBD  
TBD  
TBD  
12  
µs  
s
1
BLOCK ERASE time  
BLOCK WRITE time  
ERASE SUSPEND latency to READ  
0.5  
0.5  
9
1
1, 2, 3  
1
s
µs  
NOTE: 1. Typical values measured at T = +25°C.  
A
2. Assumes no system overhead.  
3. Typical WRITE times use checkerboard data pattern.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
21  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
WRITE/ERASE CYCLE  
WE#-CONTROLLED WRITE/ERASE  
VIH  
VIL  
A0-A20  
Note 1  
AIN  
t
t
AH  
t
t
AH  
AS  
AS  
VIH  
VIL  
CE#  
OE#  
t
WR  
t
t
CH  
CS  
VIH  
VIL  
t
WC  
t
t
WP  
t
WPH  
WED1, 2  
VIH  
VIL  
WE#  
t
t
DH  
DH  
DS  
t
t
DS  
VIH  
VIL  
Status  
(SR7=0)  
Status  
(SR7=1)  
CMD  
in  
CMD/  
Data-in  
CMD  
in  
DQ0-DQ7  
t
WB  
VOH  
VOL  
RY/BY#  
RP#  
t
t
RS  
RYBY  
VHH  
VIH  
t
t
VPS  
VPH  
VIL  
[12V VPP  
]
[5V VPP  
]
VPPH2  
VPPH1  
V
PP  
VIL  
WRITE or block  
WRITE SETUP or  
ERASE SETUP  
input  
WRITE or ERASE  
executed, status register  
checked for completion  
Command for next  
operation issued  
address asserted, and  
WRITE data or ERASE  
CONFIRM  
DON’T CARE  
TIMING PARAMETERS  
-9  
-9  
SYMBOL  
MIN UNITS  
SYMBOL  
MIN UNITS  
t
t
t
t
t
t
t
t
t
2
WC  
90  
25  
50  
40  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
VPS  
RS  
100  
1,000  
0
ns  
ns  
ns  
ns  
ns  
µs  
ms  
ns  
t
WPH  
t
2
WP  
VPH  
t
AS  
RYBY  
WB  
90  
t
AH  
200  
6
t
DS  
40  
5
WED1  
WED2  
WR  
t
DH  
600  
0
t
CS  
0
t
CH  
0
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.  
2. Measured with VPP = VPPH = 5V.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
22  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
WRITE/ERASE CYCLE  
CE#-CONTROLLED WRITE/ERASE  
VIH  
VIL  
A0-A20  
WE#  
Note 1  
AIN  
t
t
AH  
t
t
AH  
AS  
AS  
VIH  
VIL  
t
WR  
t
t
WH  
WS  
VIH  
VIL  
t
WC  
OE#  
CE#  
t
t
t
WED1, 2  
CPH  
CP  
VIH  
VIL  
t
t
DH  
DH  
t
t
DS  
DS  
VIH  
VIL  
Status  
(SR7=0)  
Status  
(SR7=1)  
CMD  
in  
CMD/  
Data-in  
CMD  
in  
DQ0-DQ7  
t
WB  
VOH  
RY/BY#  
RP#  
VOL  
VHH  
t
t
RS  
RYBY  
VIH  
VIL  
t
t
VPH  
VPS  
[12V VPP  
[5V VPP  
]
]
VPPH2  
VPPH1  
VPP  
VIL  
WRITE or block  
WRITE or ERASE  
executed, status register  
checked for completion  
address asserted, and  
WRITE data or ERASE  
CONFIRM  
Command for next  
operation issued  
WRITE SETUP or  
ERASE SETUP  
input  
DON’T CARE  
TIMING PARAMETERS  
-9  
-9  
SYMBOL  
MIN UNITS  
SYMBOL  
MIN UNITS  
t
t
t
t
t
t
t
t
t
2
WC  
90  
25  
50  
40  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
VPS  
RS  
100  
1,000  
0
ns  
ns  
ns  
ns  
ns  
µs  
ms  
ns  
t
CPH  
t
2
CP  
VPH  
t
AS  
RYBY  
WB  
90  
t
AH  
90  
t
DS  
40  
5
WED1  
WED2  
WR  
6
t
DH  
600  
0
t
WS  
0
t
WH  
0
NOTE: 1. Address inputs are “Don’t Care” but must be held stable.  
2. Measured with VPP = VPPH = 5V.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
23  
ADVANCE  
2 MEG x 8  
SMART 5 EVEN-SECTORED FLASH MEMORY  
40-PIN PLASTIC TSOP I  
(10mm x 20mm)  
.795 (20.19)  
.780 (19.81)  
.727 (18.47)  
.721 (18.31)  
.0197 (0.50)  
TYP  
.010 (0.25)  
1
40  
PIN #1 INDEX  
.397 (10.08)  
.391 (9.93)  
.010 (0.25)  
.006 (0.15)  
20  
21  
.010 (0.25)  
.004 (0.10)  
.007 (0.18)  
.005 (0.13)  
GAGE  
PLANE  
.047 (1.20)  
MAX  
SEE DETAIL A  
.008 (0.20)  
.002 (0.05)  
.024 (0.60)  
.016 (0.40)  
.0315 (0.80)  
DETAIL A  
MAX  
MIN  
NOTE: 1. All dimensions in inches (millimeters)  
or typical where noted.  
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.  
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900  
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992  
Micron is a registered trademark of Micron Technology, Inc.  
2 Meg x 8 Smart 5 Even-Sectored Flash Memory  
F42.p65 – Rev. 1/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
24  
配单直通车
MT28F008B5VG-8TET产品参数
型号:MT28F008B5VG-8TET
是否无铅:含铅
是否Rohs认证:不符合
生命周期:Obsolete
IHS 制造商:MICRON TECHNOLOGY INC
零件包装代码:TSOP1
包装说明:10 X 20 MM, PLASTIC, TSOP1-40
针数:40
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8542.32.00.51
风险等级:5.85
Is Samacsys:N
最长访问时间:80 ns
其他特性:100,000 ERASE CYCLES; TOP BOOT BLOCK
启动块:TOP
命令用户界面:YES
数据轮询:NO
JESD-30 代码:R-PDSO-G40
JESD-609代码:e0
长度:18.4 mm
内存密度:8388608 bit
内存集成电路类型:FLASH
内存宽度:8
功能数量:1
部门数/规模:1,2,1,7
端子数量:40
字数:1048576 words
字数代码:1000000
工作模式:ASYNCHRONOUS
最高工作温度:85 °C
最低工作温度:-40 °C
组织:1MX8
封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1
封装等效代码:TSSOP40,.8,20
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL
峰值回流温度(摄氏度):235
电源:5 V
编程电压:5 V
认证状态:Not Qualified
座面最大高度:1.2 mm
部门规模:16K,8K,96K,128K
最大待机电流:0.000005 A
子类别:Flash Memories
最大压摆率:0.055 mA
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.5 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
切换位:NO
类型:NOR TYPE
宽度:10 mm
Base Number Matches:1
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