16Gb: x4, x8 TwinDie DDR4 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions
Symbol
Type
Description
A[17:0]
Input
Address inputs: Provide the row address for ACTIVATE commands and the col-
umn address for READ/WRITE commands to select one location out of the memo-
ry array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/
A16, have additional functions; see individual entries in this table). The address
inputs also provide the op-code during the MODE REGISTER SET command. A16 is
used on some 8Gb and 16Gb parts, and A17 is only used on some 16Gb parts.
A10/AP
Input
Auto precharge: A10 is sampled during READ and WRITE commands to deter-
mine whether auto precharge should be performed to the accessed bank after a
READ or WRITE operation (HIGH = auto precharge; LOW = no auto precharge).
A10 is sampled during a PRECHARGE command to determine whether the PRE-
CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by the bank group and bank ad-
dresses.
A12/BC_n
ACT_n
Input
Input
Burst chop: A12/BC_n is sampled during READ and WRITE commands to deter-
mine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW =
burst-chopped). See the Command Truth Table.
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along
with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are trea-
ted as row address inputs for the ACTIVATE command. When ACT_n is HIGH
(along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14
are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals.
See the Command Truth Table.
BA[1:0]
BG[1:0]
Input
Input
Bank address inputs: Define the bank (within a bank group) to which an ACTI-
VATE, READ, WRITE, or PRECHARGE command is being applied. Also determines
which mode register is to be accessed during a MODE REGISTER SET command.
Bank group address inputs: Define the bank group to which a REFRESH, ACTI-
VATE, READ, WRITE, or PRECHARGE command is being applied. Also determines
which mode register is to be accessed during a MODE REGISTER SET command.
BG[1:0] are used in the x4 and x8 configurations.
C0/CKE1,
C1/CS1_n,
C2/ODT1
Input
Stack address inputs: These inputs are used only when devices are stacked;
that is, 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not
used in the x16 configuration). DDR4 will support a traditional dual-die package
(DDP), which uses these three signals for control of the second die (CS1_n, CKE1,
ODT1). DDR4 is not expected to support a traditional quad-die package (QDP).
For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-
load (master/slave) type of configuration where C0, C1, and C2 are used as chip
ID selects in conjunction with a single CS_n, CKE, and ODT.
CK_t,
CK_c
Input
Clock: Differential clock inputs. All address, command, and control input signals
are sampled on the crossing of the positive edge of CK_t and the negative edge
of CK_c.
PDF: 09005aef85fd40a1
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN
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