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产品型号MT40A2G8NRE-083E的Datasheet PDF文件预览

16Gb: x4, x8 TwinDie DDR4 SDRAM  
Description  
TwinDie1.2V DDR4 SDRAM  
MT40A4G4 – 128 Meg x 4 x 16 Banks x 2 Ranks  
MT40A2G8 – 64 Meg x 8 x 16 Banks x 2 Ranks  
Options  
Marking  
Description  
The 16Gb (TwinDie) DDR4 SDRAM uses  
• Configuration  
– 128 Meg x 4 x 16 banks x 2 ranks  
– 64 Meg x 8 x 16 banks x 2 ranks  
• FBGA package (Pb-free)  
– 78-ball FBGA  
(9.5mm x 13mm x 1.2mm) Die Rev :A  
– 78-ball FBGA  
4G4  
2G8  
Micron’s 8Gb DDR4 SDRAM die (essentially two ranks  
of the 8Gb DDR4 SDRAM). Refer to Micron’s 8Gb  
DDR4 SDRAM data sheet for the specifications not in-  
cluded in this document. Specifications for base part  
number MT40A2G4 correlate to TwinDie manufactur-  
ing part number MT40A4G4; specifications for base  
part number MT40A1G8 correlate to TwinDie manu-  
facturing part number MT40A2G8.  
FSE  
NRE  
(8.0mm x 12mm x 1.2mm) Die Rev :B  
• Timing – cycle time1  
– 0.750ns @ CL = 18 (DDR4-2666)  
– 0.833ns @ CL = 16 (DDR4-2400)  
– 0.833ns @ CL = 17 (DDR4-2400)  
– 0.937ns @ CL = 15 (DDR4-2133)  
– 0.937ns @ CL = 16 (DDR4-2133)  
• Self refresh  
-075E  
-083E  
-083  
-093E  
-093  
Features  
• Uses 8Gb Micron die  
Two ranks (includes dual CS#, ODT, and CKE balls)  
• Each rank has 4 groups of 4 internal banks for con-  
current operation  
• VDD = VDDQ = 1.2V (1.14–1.26V)  
• 1.2V VDDQ-terminated I/O  
• JEDEC-standard ball-out  
– Standard  
None  
• Operating temperature  
– Commercial (0°C TC 95°C)  
• Revision  
None  
:A  
:B  
• Low-profile package  
• TC of 0°C to 95°C  
– 0°C to 85°C: 8192 refresh cycles in 64ms  
– 85°C to 95°C: 8192 refresh cycles in 32ms  
1. CL = CAS (READ) latency.  
Note:  
Table 1: Key Timing Parameters  
Data Rate  
Speed Grade  
-075E1  
(MT/s)  
2666  
2400  
2400  
2133  
2133  
Target tRCD-tRP-CL  
tRCD (ns)  
13.5  
tRP (ns)  
13.5  
CL (ns)  
13.5  
18-18-18  
16-16-16  
17-17-17  
15-15-15  
16-16-16  
-083E2  
13.32  
14.16  
14.06  
15  
13.32  
14.16  
14.06  
15  
13.32  
14.16  
14.06  
15  
-0832  
-093E  
-093  
1. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; and 2400, CL = 17.  
2. Backward compatible to 2133, CL = 15 (-093E).  
Notes:  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
© 2015 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Description  
Table 2: Addressing  
Parameter  
4096 Meg x 4  
2048 Meg x 8  
Configuration  
128 Meg x 4 x 16 banks x 2 ranks  
64 Meg x 8 x 16 banks x 2 ranks  
Bank group address  
Bank count per group  
Bank address in bank group  
Row address  
BG[1:0]  
4
BG[1:0]  
4
BA[1:0]  
BA[1:0]  
64K A[15:0]  
1K A[9:0]  
128K A[16:0]  
1K A[9:0]  
Column address  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
2
© 2015 Micron Technology, Inc. All rights reserved.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Ball Assignments and Descriptions  
Ball Assignments and Descriptions  
Figure 1: 78-Ball FBGA Ball Assignments (Top View)  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
A
B
C
D
E
NF, NF/  
TDQS_c  
NF, NF/DM_n/  
DBI_n/TDQS_t  
VDD  
VSSQ  
VSSQ  
VDDQ  
VSS  
VSSQ  
ZQ  
VPP  
VDDQ DQS_c  
DQ0 DQS_t  
DQ1  
VDD  
VDDQ  
VDDQ  
VSSQ DQ4/NC DQ2  
DQ3 DQ5/NC VSSQ  
VSS  
VDDQ DQ6/NC  
DQ7/NC VDDQ  
VSS  
F
F
VDD C2/ODT1 ODT  
VSS C0/CKE1 CKE  
VDD WE_n/A14 ACT_n  
CK_t  
CK_c  
VDD  
G
H
J
G
H
J
CS_n C1/CS1_n RFU/TEN  
CAS_n/A15 RAS_n/A16  
VSS  
VDD  
VSS  
VREFCA  
BG0 A10/AP  
A12/BC_n BG1  
K
L
K
L
VSS  
BA0  
A4  
A0  
A3  
A1  
A9  
BA1  
RESET_n A6  
A5 ALERT_n  
M
N
M
N
VDD  
A8  
A2  
A7  
VPP  
VSS  
A11  
PAR  
A17/NC A13  
VDD  
1. See the FBGA 78-Ball Descriptions table.  
Notes:  
2. Dark balls (with ring) designate balls that are specific to controlling the second die of  
the TwinDie package when compared to a monolithic package.  
3. A comma “,” separates the configuration; a slash “/” defines a selectable function. For  
example: Ball A7 = NF, NF/DM_n/DBI_n/TDQS_t where NF applies to the x4 configuration  
only. NF/DM_n/DBI_n/TDQS_t applies to the x8 configuration only and is selectable be-  
tween NF, DM_n, DBI_n, or TDQS_t via MRS.  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
3
© 2015 Micron Technology, Inc. All rights reserved.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Ball Assignments and Descriptions  
Table 3: FBGA 78-Ball Descriptions  
Symbol  
Type  
Description  
A[17:0]  
Input  
Address inputs: Provide the row address for ACTIVATE commands and the col-  
umn address for READ/WRITE commands to select one location out of the memo-  
ry array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/  
A16, have additional functions; see individual entries in this table). The address  
inputs also provide the op-code during the MODE REGISTER SET command. A16 is  
used on some 8Gb and 16Gb parts, and A17 is only used on some 16Gb parts.  
A10/AP  
Input  
Auto precharge: A10 is sampled during READ and WRITE commands to deter-  
mine whether auto precharge should be performed to the accessed bank after a  
READ or WRITE operation (HIGH = auto precharge; LOW = no auto precharge).  
A10 is sampled during a PRECHARGE command to determine whether the PRE-  
CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one  
bank is to be precharged, the bank is selected by the bank group and bank ad-  
dresses.  
A12/BC_n  
ACT_n  
Input  
Input  
Burst chop: A12/BC_n is sampled during READ and WRITE commands to deter-  
mine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW =  
burst-chopped). See the Command Truth Table.  
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along  
with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are trea-  
ted as row address inputs for the ACTIVATE command. When ACT_n is HIGH  
(along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14  
are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals.  
See the Command Truth Table.  
BA[1:0]  
BG[1:0]  
Input  
Input  
Bank address inputs: Define the bank (within a bank group) to which an ACTI-  
VATE, READ, WRITE, or PRECHARGE command is being applied. Also determines  
which mode register is to be accessed during a MODE REGISTER SET command.  
Bank group address inputs: Define the bank group to which a REFRESH, ACTI-  
VATE, READ, WRITE, or PRECHARGE command is being applied. Also determines  
which mode register is to be accessed during a MODE REGISTER SET command.  
BG[1:0] are used in the x4 and x8 configurations.  
C0/CKE1,  
C1/CS1_n,  
C2/ODT1  
Input  
Stack address inputs: These inputs are used only when devices are stacked;  
that is, 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not  
used in the x16 configuration). DDR4 will support a traditional dual-die package  
(DDP), which uses these three signals for control of the second die (CS1_n, CKE1,  
ODT1). DDR4 is not expected to support a traditional quad-die package (QDP).  
For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-  
load (master/slave) type of configuration where C0, C1, and C2 are used as chip  
ID selects in conjunction with a single CS_n, CKE, and ODT.  
CK_t,  
CK_c  
Input  
Clock: Differential clock inputs. All address, command, and control input signals  
are sampled on the crossing of the positive edge of CK_t and the negative edge  
of CK_c.  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
4
© 2015 Micron Technology, Inc. All rights reserved.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Ball Assignments and Descriptions  
Table 3: FBGA 78-Ball Descriptions (Continued)  
Symbol  
Type  
Description  
CKE  
Input  
Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock  
signals, device input buffers, and output drivers. Taking CKE LOW provides PRE-  
CHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active  
power-down (row active in any bank). CKE is asynchronous for self refresh exit.  
After VREFCA has become stable during the power-on and initialization sequence,  
it must be maintained during all operations (including SELF REFRESH). CKE must  
be maintained HIGH throughout read and write accesses. Input buffers (exclud-  
ing CK_t, CK_c, ODT, RESET_n, and CKE are disabled during power-down. Input  
buffers (excluding CKE and RESET#) are disabled during self refresh.  
CS_n  
Input  
Input  
Chip select: All commands are masked when CS_n is registered HIGH. CS_n pro-  
vides for external rank selection on systems with multiple ranks. CS_n is consid-  
ered part of the command code.  
DM_nS  
Input data mask: DM_n is an input mask signal for write data. Input data is  
masked when DM is sampled LOW coincident with that input data during a write  
access. DM is sampled on both edges of DQS. DM is not supported on x4 configu-  
rations. LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are  
enabled by mode register settings. See the Data Mask (DM) section.  
ODT  
PAR  
Input  
Input  
On-die termination: ODT (registered HIGH) enables termination resistance in-  
ternal to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ,  
DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configu-  
rations (when the TDQS function is enabled via mode register). The ODT pin will  
be ignored if the mode registers are programmed to disable RTT.  
Parity for command and address: This function can be enabled or disabled via  
the mode register. When enabled, the parity signal covers all command and ad-  
dress inputs, including RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/  
BC_n, BA[1:0], BG[1:0], C0/A18, C1/A19, C2/A20. Control pins NOT covered by the  
parity signal are CS_n, CKE, and ODT. Unused address pins that are density- and  
configuration-specific should be treated internally as 0s by the DRAM parity log-  
ic.  
RAS_n/A16,  
CAS_n/A15,  
WE_n/A14  
Input  
Input  
Command inputs: RAS_n/A16 , CAS_n/A15, and WE_n/A14 (along with CS_n and  
ACT_n) define the command and/or address being entered. See the ACT_n de-  
scription in this table.  
RESET_n  
Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and in-  
active when RESET_n is HIGH. RESET_n must be HIGH during normal operation.  
RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of  
VDD; that is, 960 mV for DC HIGH and 240 mV for DC LOW.  
TEN  
Input  
Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN  
must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC  
HIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DC  
LOW).  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
5
© 2015 Micron Technology, Inc. All rights reserved.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Ball Assignments and Descriptions  
Table 3: FBGA 78-Ball Descriptions (Continued)  
Symbol  
Type  
Description  
DQ  
I/O  
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], and DQ[7:0]  
for the x4, and x8, respectively. If write CRC is enabled via mode register, the  
write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1,  
DQ2, and DQ3 may be used to monitor the internal VREF level during test via  
mode register setting MR[4] A[4] = HIGH, training times change when enabled.  
During this mode, RTT value should be set to High-Z. This measurement is for veri-  
fication purposes and is NOT an external voltage supply pin.  
DBI_n  
I/O  
I/O  
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for  
data bus inversion in the x8 configuration. DBI_n is associated with DQ[7:0]. The  
DBI feature is not supported on x4 configurations. DBI can be configured for  
both READ (output) and WRITE (input) operations depending on the mode regis-  
ter settings. The DM, DBI, and TDQS functions are enabled by mode register set-  
tings. See the Data Bus Inversion (DBI) section.  
DQS_t,  
DQS_c  
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with  
READ data, centered-aligned with WRITE data. For the x4 and x8 configurations,  
DQS corresponds to the data on DQ[3:0] and DQ[7:0] respectively. DDR4 SDRAM  
supports a differential data strobe only and does not support a single-ended data  
strobe.  
ALERT_n  
Output  
Output  
Alert output: This signal allows the DRAM to indicate to the system's memory  
controller that a specific alert or event has occurred. Alerts will include the com-  
mand/address parity error and the CRC data error when either of these functions  
is enabled in the mode register.  
TDQS_t,  
TDQS_c  
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only.  
When enabled via the mode register, the DRAM will enable the same RTT termi-  
nation resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.  
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin  
will provide the data mask (DM) function, and the TDQS_c pin is not used. The  
TDQS function must be disabled in the mode register for the x4 configuration.  
The DM function is supported only in x8 configuration.  
VDD  
VDDQ  
VPP  
Supply  
Supply  
Power supply: 1.2V ±0.060V.  
DQ power supply: 1.2V ±0.060V.  
DRAM activating power supply: 2.5V -0.125V / +0.250V.  
Reference voltage for control, command, and address pins.  
Ground.  
Supply  
VREFCA  
VSS  
Supply  
Supply  
VSSQ  
ZQ  
Supply  
DQ ground.  
Reference  
Reference ball for ZQ calibration: This ball is tied to an external 240Ω resistor  
(RZQ), which is tied to VSSQ. Note that this ball is shared by two DRAM devices. As  
a result, ZQ calibration operations need to be carried out separately so that cor-  
rect values are achieved.  
RFU  
NC  
NF  
Reserved for future use.  
No connect: No internal electrical connection is present.  
No function: May have internal connection present, but has no function.  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
6
© 2015 Micron Technology, Inc. All rights reserved.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Functional Description  
Functional Description  
The TwinDie DDR4 SDRAM is a high-speed, CMOS dynamic random access memory  
device internally configured as two 16-bank DDR4 SDRAM devices.  
Although each die is tested individually within the dual-die package, some TwinDie test  
results may vary from a like-die tested within a monolithic die package.  
The DDR4 SDRAM uses a double data rate architecture to achieve high-speed opera-  
tion. The double data rate architecture is an 8n-prefetch architecture with an interface  
designed to transfer two data words per clock cycle at the I/O balls. A single read or  
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-  
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers  
at the I/O balls.  
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for  
use in data capture at the DDR4 SDRAM input receiver. DQS is center-aligned with data  
for WRITEs. The read data is transmitted by the DDR4 SDRAM and edge-aligned to the  
data strobes.  
Read and write accesses to the DDR4 SDRAM are burst-oriented. Accesses start at a se-  
lected location and continue for a programmed number of locations in a programmed  
sequence. Operation begins with the registration of an ACTIVATE command, which is  
then followed by a READ or WRITE command. The address bits registered coincident  
with the ACTIVATE command are used to select the bank and row to be accessed. The  
address bits (including CSn#, BAn, and An) registered coincident with the READ or  
WRITE command are used to select the rank, bank, and starting column location for the  
burst access.  
This data sheet provides a general description, package dimensions, and the package  
ballout. Refer to the Micron monolithic DDR4 data sheet for complete information re-  
garding individual die initialization, register definition, command descriptions, and die  
operation.  
Industrial Temperature  
The industrial temperature (IT) option, if offered, requires that the case temperature  
not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when  
TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Addi-  
tionally, ODT resistance, IDD values, some IDD specifications and the input/output im-  
pedance must be derated when TC is < 0°C or > 95°C. See the DDR4 monolithic data  
sheet for details.  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
7
© 2015 Micron Technology, Inc. All rights reserved.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Functional Block Diagrams  
Functional Block Diagrams  
Figure 2: Functional Block Diagram (128 Meg x 4 x 16 Banks x 2 Ranks)  
Rank 1  
(128 Meg x 4 x 16 banks)  
Rank 0  
(128 Meg x 4 x 16 banks)  
CS0#  
CKE0  
ODT0  
PAR  
TEN  
CS1#  
CKE1  
ODT1  
CK  
A[13:0],  
ACT_n,  
WE_n/A14,  
CAS_n/A15,  
RAS_n/A16,  
BA[1:0],  
CK#  
ZQ  
RESET  
ALERT_n  
DM  
DQ[3:0]  
DQS, DQS#  
BG[1:0]  
Figure 3: Functional Block Diagram (64 Meg x 8 x 16 Banks x 2 Ranks)  
Rank 1  
(64 Meg x 8 x 16 banks)  
Rank 0  
(64 Meg x 8 x 16 banks)  
CS0#  
CKE0  
ODT0  
CS1#  
CKE1  
ODT1  
PAR  
TEN  
RESET  
CK  
CK#  
ZQ  
A[13:0],  
ACT_n,  
WE_n/A14,  
CAS_n/A15,  
RAS_n/A16,  
BA[1:0],  
ALERT_n  
TDQS#  
BG[1:0]  
DQ[7:0]  
DBI/DM/TDQS  
DQS, DQS#  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
8
© 2015 Micron Technology, Inc. All rights reserved.  
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Electrical Specifications – Leakages  
Electrical Specifications – Leakages  
Table 4: Input and Output Leakages  
Symbol  
Parameter  
Min  
Max  
Units  
Notes  
IIN  
Input leakage current  
Any input 0V VIN VDD  
VREF pin 0V VIN 1.1V  
–4  
4
µA  
1
,
(All other pins not under test = 0V)  
IVREFCA  
VREF supply leakage current  
–4  
4
µA  
2
(All other pins not under test = 0V)  
IZQ  
Input leakage on ZQ pin  
–6  
–8  
6
8
µA  
µA  
µA  
µA  
ITEN  
Input leakage on TEN pin  
Output leakage: VOUT = VDDQ  
Output leakage: VOUT = VSSQ  
IOZpd  
IOZpu  
10  
3
–100  
3, 4  
1. Any input 0V < VIN < 1.1V  
2. VREFCA = VDD/2, VDD at valid level.  
3. DQ are disabled.  
Notes:  
4. ODT is disabled with the ODT input HIGH.  
Temperature and Thermal Impedance  
It is imperative that the DDR4 SDRAM device’s temperature specifications, shown in  
the following table, be maintained in order to ensure the junction temperature is in the  
proper operating range to meet data sheet specifications. An important step in main-  
taining the proper junction temperature is using the device’s thermal impedances cor-  
rectly. The thermal impedances listed in Table 6 (page 10) apply to the current die re-  
vision and packages.  
Incorrectly using thermal impedances can produce significant errors. Read Micron  
technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the  
thermal impedance table. For designs that are expected to last several years and require  
the flexibility to use several DRAM die shrinks, consider using final target theta values  
(rather than existing values) to account for increased thermal impedances from the die  
size reduction.  
The DDR4 SDRAM device’s safe junction temperature range can be maintained when  
the TC specification is not exceeded. In applications where the device’s ambient tem-  
perature is too high, use of forced air and/or heat sinks may be required to satisfy the  
case temperature specifications.  
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16Gb: x4, x8 TwinDie DDR4 SDRAM  
Electrical Specifications – Leakages  
Table 5: Thermal Characteristics  
Notes 1–3 apply to entire table  
Parameter  
Symbol  
Value  
0 to 85  
0 to 95  
Units  
°C  
Notes  
Operating temperature  
TC  
°C  
4
1. MAX operating case temperature TC is measured in the center of the package, as shown  
below.  
Notes:  
2. A thermal solution must be designed to ensure that the device does not exceed the  
maximum TC during operation.  
3. Device functionality is not guaranteed if the device exceeds maximum TC during  
operation.  
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs  
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh  
(ASR), if available, must be enabled.  
Figure 4: Temperature Test Point Location  
Test point  
Length (L)  
0.5 (L)  
0.5 (W)  
Width (W)  
Table 6: Thermal Impedance  
Θ JA (°C/W) Θ JA (°C/W) Θ JA (°C/W)  
Airflow =  
Airflow =  
Airflow =  
Package  
Substrate  
0m/s  
1m/s  
2m/s  
Θ JB (°C/W) Θ JC (°C/W) Notes  
78-ball Rev A "FSE"  
Low  
conductivity  
47.9  
28.3  
53.5  
33.2  
36.2  
23.0  
41.5  
27.4  
32.0  
21.3  
37.0  
25.6  
NA  
10.6  
NA  
1.6  
NA  
1.5  
NA  
1
High  
conductivity  
78-ball Rev B "NRE"  
Low  
conductivity  
1
High  
20.2  
conductivity  
1. Thermal resistance data is based on a number of samples from multiple lots and should  
be viewed as a typical number.  
Note:  
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16Gb: x4, x8 TwinDie DDR4 SDRAM  
Electrical Specifications – Leakages  
Figure 5: Thermal Impedance  
60  
53.5  
Low conductivity test board  
50  
40  
30  
20  
10  
0
High conductivity test board  
37.0  
41.5  
33.2  
27.4  
25.6  
20.2  
1.5  
θJA (0 m/s)  
θJA (1 m/s)  
θJA (2 m/s)  
θJB  
θJC  
1. All simulations are conducted per JEDEC standards.  
Note:  
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Electrical Characteristics – AC and DC Output Measurement  
Levels  
Electrical Characteristics – AC and DC Output Measurement Levels  
Single-Ended Outputs  
Table 7: Single-Ended Output Levels  
Parameter  
Symbol  
VOH(DC)  
VOM(DC)  
VOL(DC)  
VOH(AC)  
VOL(AC)  
DDR4-1600 to DDR4-3200  
1.1 × VDDQ  
Unit  
V
DC output high measurement level (for IV curve linearity)  
DC output mid measurement level (for IV curve linearity)  
DC output low measurement level (for IV curve linearity)  
AC output high measurement level (for output slew rate)  
AC output low measurement level (for output slew rate)  
0.8 × VDDQ  
V
0.5 × VDDQ  
V
(0.7 + 0.15) × VDDQ  
(0.7 - 0.15) × VDDQ  
V
V
1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended  
output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load  
Note:  
of 50Ω to VTT = VDDQ  
.
Using the same reference load used for timing measurements, output slew rate for fall-  
ing and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-  
ended signals.  
Table 8: Single-Ended Output Slew Rate Definition  
Measured  
Description  
From  
VOL(AC)  
VOH(AC)  
To  
Defined by  
Single-ended output slew rate for rising edge  
Single-ended output slew rate for falling edge  
VOH(AC)  
VOL(AC)  
[VOH(AC) - VOL(AC)]/ΔTRse  
[VOH(AC) - VOL(AC)]/ΔTFse  
Figure 6: Single-ended Output Slew Rate Definition  
TRse  
VOH(AC)  
VOL(AC)  
TFse  
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Electrical Characteristics – AC and DC Output Measurement  
Levels  
Table 9: Single-Ended Output Slew Rate  
For RON = RZQ/7  
DDR4-1333 / 1866 / 2133 / 2400 /2666  
Parameter  
Symbol  
Min  
Max  
Unit  
Single-ended output slew rate  
SRQse  
2
7
V/ns  
1. SR = slew rate; Q = query output; se = single-ended signals  
Notes:  
2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte  
lane:  
• Case 1 is defined for a single DQ signal within a byte lane that is switching into a cer-  
tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-  
nals in the same byte lane are static (they stay at either HIGH or LOW).  
• Case 2 is defined for a single DQ signal within a byte lane that is switching into a cer-  
tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig-  
nals in the same byte lane are switching into the opposite direction (from LOW-to-  
HIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the  
opposite direction, the standard maximum limit of 7 V/ns applies.  
Differential Outputs  
Table 10: Differential Output Levels  
Parameter  
Symbol  
DDR4-1600 to DDR4-3200  
Unit  
AC differential output high measurement level (for output slew  
rate)  
VOH,diff(AC)  
0.3 × VDDQ  
V
AC differential output low measurement level (for output slew  
rate)  
VOL,diff(AC)  
–0.3 × VDDQ  
V
1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended out-  
put peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of  
50Ω to VTT = VDDQ at each differential output.  
Note:  
Using the same reference load used for timing measurements, output slew rate for fall-  
ing and rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for dif-  
ferential signals.  
Table 11: Differential Output Slew Rate Definition  
Measured  
Description  
From  
VOL,diff(AC)  
VOH,diff(AC)  
To  
VOH,diff(AC)  
VOL,diff(AC)  
Defined by  
Differential output slew rate for rising edge  
Differential output slew rate for falling edge  
[VOH,diff(AC) - VOL,diff(AC)]/ΔTRdiff  
[VOH,diff(AC) - VOL,diff(AC)]/ΔTFdiff  
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Electrical Characteristics – AC and DC Output Measurement  
Levels  
Figure 7: Differential Output Slew Rate Definition  
TRdiff  
VOH,diff(AC)  
VOL,diff(AC)  
TFdiff  
Table 12: Differential Output Slew Rate  
For RON = RZQ/7  
DDR4-1333 / 1866 / 2133 / 2400 / 2666  
Parameter  
Symbol  
Min  
Max  
Unit  
Differential output slew rate  
SRQdiff  
4
14  
V/ns  
1. SR = slew rate; Q = query output; diff = differential signals.  
Note:  
Reference Load for AC Timing and Output Slew Rate  
The effective reference load of 50Ω to VTT = VDDQ and driver impedance of RZQ/7 for  
each output was used in defining the relevant AC timing parameters of the device as  
well as output slew rate measurements.  
RON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC  
timing paraeter values of the device. The maximum DC high level of output signal = 1.0  
× VDDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } × VDDQ = 0.4 ×  
VDDQ  
The nominal reference level of an output signal can be approximated by the following:  
The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } × VDDQ = 0.7 ×  
VDDQ. The actual reference level of output signal might vary with driver RON and refer-  
ence load tolerances. Thus, the actual reference level or midpoint of an output signal is  
at the widest part of the output signal’s eye.  
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Electrical Characteristics – AC and DC Output Measurement  
Levels  
Figure 8: Reference Load For AC Timing and Output Slew Rate  
VDDQ  
VTT = VDDQ  
DQ, DQS_t, DQS_c,  
DM, TDQS_t, TDQS_c  
CK_t, CK_c  
DUT  
VSSQ  
RTT = 50Ω  
Timing reference point  
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16Gb: x4, x8 TwinDie DDR4 SDRAM  
Electrical Specifications – ICDD Parameters  
Electrical Specifications – ICDD Parameters  
Table 13: DDR4 ICDD Specifications and Conditions (Rev. A)  
Note 1 applies to the entire table  
Combined  
Symbol  
Individual  
Die Status  
Bus  
Width  
DDR4-2133  
DDR4-2400  
DDR4-2666  
Units  
ICDD0  
ICDD0  
IDD0 + IDD2P + 3  
ICPP0  
IPP0 + IPP3N  
ICDD1  
IDD1 + IDD2P + 3  
ICDD2N  
IDD2N + IDD2P  
ICDD2NT  
IDD2NT + IDD2P  
ICDD2P  
IDD2P + IDD2P  
ICDD2Q  
IDD2Q + IDD2P  
ICDD3N  
IDD3N + IDD2P  
ICPP3N  
=
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
83  
93  
TBD  
mA  
ICPP0  
=
6
6
108  
80  
90  
60  
75  
85  
6
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
ICDD1  
=
98  
70  
80  
50  
70  
80  
6
ICDD2N  
ICDD2NT  
ICDD2P  
ICDD2Q  
ICDD3N  
ICPP3N  
=
=
=
=
=
=
IPP3N + IPP3N  
ICDD3P  
ICDD4R  
ICDD3P = IDD3P + IDD2P  
x4, x8  
x4  
60  
70  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
mA  
mA  
ICDD4R  
=
163  
178  
163  
178  
250  
178  
183  
178  
193  
255  
IDD4R + IDD2P + 3  
x8  
ICDD4W  
ICDD4W  
=
x4  
mA  
IDD4W + IDD2P + 3  
x8  
ICDD5B  
ICPP5B  
ICDD6N  
ICDD6E  
ICDD5B  
IDD5B + IDD2P  
ICPP5B  
IPP5B + IPP3N  
ICDD6N  
IDD6N + IDD6N  
ICDD6E  
IDD6E + IDD6E  
ICDD6R  
IDD6R + IDD6R  
ICDD6A  
IDD6A + IDD6A  
ICDD6A  
IDD6A + IDD6A  
ICDD6A  
IDD6A + IDD6A  
=
x4, x8  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
=
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
33  
60  
70  
50  
40  
50  
70  
33  
60  
70  
50  
40  
50  
70  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
=
=
2
ICDD6R  
=
ICDD6A (25°C)2  
ICDD6A (45°C)2  
ICDD6A (75°C)2  
=
=
=
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16Gb: x4, x8 TwinDie DDR4 SDRAM  
Electrical Specifications – ICDD Parameters  
Table 13: DDR4 ICDD Specifications and Conditions (Rev. A) (Continued)  
Note 1 applies to the entire table  
Combined  
Symbol  
Individual  
Die Status  
Bus  
Width  
DDR4-2133  
DDR4-2400  
DDR4-2666  
TBD  
Units  
ICDD7  
ICDD7  
=
x4  
x8  
213  
228  
18  
223  
238  
18  
mA  
IDD7 + IDD2P + 3  
TBD  
ICPP7  
ICPP7  
=
x4, x8  
TBD  
mA  
mA  
IPP7 + IPP3N  
ICDD8  
ICDD8 = IDD8 + IDD8  
x4, x8  
40  
40  
TBD  
1. ICDD values reflect the combined current of both individual die. IDDx represents individu-  
al die values.  
Notes:  
2. ICDD6R and ICDD6A values are typical.  
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Electrical Specifications – ICDD Parameters  
Table 14: DDR4 ICDD Specifications and Conditions (Rev. B)  
Note 1 applies to the entire table  
Combined  
Symbol  
Individual  
Die Status  
Bus  
Width  
DDR4-2133  
DDR4-2400  
DDR4-2666  
TBD  
Units  
ICDD0  
ICDD0  
=
x4  
x8  
68  
73  
6
71  
76  
6
mA  
IDD0 + IDD2P + 3  
TBD  
ICPP0  
ICPP0  
IPP0 + IPP3N  
ICDD1  
IDD1 + IDD2P + 3  
=
x4, x8  
TBD  
mA  
mA  
ICDD1  
=
x4  
x8  
80  
85  
58  
83  
88  
59  
TBD  
TBD  
TBD  
ICDD2N  
ICDD2NT  
ICDD2P  
ICDD2Q  
ICDD3N  
ICPP3N  
ICDD2N  
IDD2N + IDD2P  
ICDD2NT  
IDD2NT + IDD2P  
ICDD2P  
IDD2P + IDD2P  
ICDD2Q  
IDD2Q + IDD2P  
ICDD3N  
IDD3N + IDD2P  
ICPP3N  
=
x4, x8  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
=
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
70  
50  
55  
65  
6
75  
50  
55  
68  
6
TBD  
TBD  
TBD  
TBD  
TBD  
=
=
=
=
IPP3N + IPP3N  
ICDD3P  
ICDD3P = IDD3P + IDD2P  
x4, x8  
x8  
55  
57  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
60  
62  
ICDD4R  
ICDD4R  
=
x4  
138  
153  
133  
143  
275  
138  
163  
141  
151  
275  
mA  
mA  
IDD4R + IDD2P + 3  
x8  
ICDD4W  
ICDD4W  
=
x4  
IDD4W + IDD2P + 3  
x8  
ICDD5B  
ICPP5B  
ICDD6N  
ICDD6E  
ICDD5B  
IDD5B + IDD2P  
ICPP5B  
IPP5B + IPP3N  
ICDD6N  
IDD6N + IDD6N  
ICDD6E  
IDD6E + IDD6E  
ICDD6R  
IDD6R + IDD6R  
ICDD6A  
IDD6A + IDD6A  
ICDD6A  
IDD6A + IDD6A  
=
x4, x8  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
=
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
x4, x8  
31  
60  
70  
40  
16  
40  
31  
60  
70  
40  
16  
40  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
=
=
2
ICDD6R  
=
ICDD6A (25°C)2  
ICDD6A (45°C)2  
=
=
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Electrical Specifications – ICDD Parameters  
Table 14: DDR4 ICDD Specifications and Conditions (Rev. B) (Continued)  
Note 1 applies to the entire table  
Combined  
Symbol  
Individual  
Die Status  
Bus  
Width  
DDR4-2133  
DDR4-2400  
DDR4-2666  
Units  
ICDD6A (75°C)2  
ICDD6A  
IDD6A + IDD6A  
ICDD7  
IDD7 + IDD2P + 3  
=
x4, x8  
60  
60  
TBD  
mA  
ICDD7  
=
x4  
x8  
188  
198  
18  
193  
203  
18  
TBD  
TBD  
TBD  
mA  
ICPP7  
ICPP7  
=
x4, x8  
mA  
mA  
IPP7 + IPP3N  
ICDD8  
ICDD8 = IDD8 + IDD8  
x4, x8  
50  
50  
TBD  
1. ICDD values reflect the combined current of both individual die. IDDx represents individu-  
al die values.  
Notes:  
2. ICDD6R and ICDD6A values are typical.  
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Package Dimensions  
Package Dimensions  
Figure 9: 78-Ball FBGA Die Rev. A (package code FSE)  
Seating plane  
0.1 A  
A
78X Ø0.45  
Ball A1 ID  
(covered by SR)  
Dimensions apply  
to solder balls post-  
reflow on Ø0.33 NSMD  
Ball A1 ID  
ball pads.  
9
8
7
3
2 1  
A
B
C
D
E
13 ±0.1  
9.6 CTR  
F
G
H
J
K
L
M
N
0.8 TYP  
1.1 ±0.1  
0.8 TYP  
6.4 CTR  
0.3 ±0.05  
9.5 ±0.1  
1. All dimensions are in millimeters.  
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).  
Notes:  
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16Gb: x4, x8 TwinDie DDR4 SDRAM  
Package Dimensions  
Figure 10: 78-Ball FBGA Die Rev. B (package code NRE)  
0.155  
Seating plane  
0.12 A  
A
1.8 CTR  
nonconductive  
overmold  
78X Ø0.47  
Dimensions apply  
to solder balls post-  
reflow on Ø0.42 SMD  
ball pads.  
Ball A1 ID  
(covered by SR)  
Ball A1 ID  
9
8
7
3
2 1  
A
B
C
D
E
12 ±0.1  
9.6 CTR  
F
G
H
J
K
L
M
N
0.8 TYP  
0.8 TYP  
6.4 CTR  
8 ±0.1  
1.1 ±0.1  
0.34 ±0.05  
1. All dimensions are in millimeters.  
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).  
Notes:  
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000  
www.micron.com/products/support Sales inquiries: 800-932-4992  
Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.  
All other trademarks are the property of their respective owners.  
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.  
Although considered final, these specifications are subject to change, as further product development and data characterization some-  
times occur.  
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配单直通车
MT40A2G4TRF-093E:A产品参数
型号:MT40A2G4TRF-093E:A
生命周期:Obsolete
IHS 制造商:MICRON TECHNOLOGY INC
Reach Compliance Code:unknown
ECCN代码:EAR99
风险等级:5.81
内存集成电路类型:DDR DRAM
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