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产品型号N87C196KB16的概述

芯片N87C196KB16的概述 N87C196KB16是由爱特梅尔（Atmel，现为微芯科技Microchip的一部分）制造的一款16位微控制器。这种微控制器广泛应用于嵌入式系统，尤其是在工业自动化、家电控制、交通管理及医疗设备等领域。N87C196微控制器系列是基于强大的CISC架构，具备高效的计算能力和丰富的外设集成。该系列的设计目标是为嵌入式系统提供强大的处理能力，同时保持较低的成本和功耗。 N87C196KB16具备灵活的编程和强大的输入/输出功能，这使其在不同的应用中表现出色。此外，它的16位数据总线和多种定时器、定时器/counter及串行通讯接口，使得其在多种数据处理场景中具有很高的适应能力。芯片N87C196KB16的详细参数 - CPU: 16位CISC - 时钟频率: 16MHz - 存储器: - ROM: 32KB（可编程只读存储器） - RAM: 1...

产品型号N87C196KB16的Datasheet PDF文件预览

8XC196KB/8XC196KB16

COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER

8 Kbytes of On-Chip ROM/OTP

Available

Dynamically Configurable 8-Bit or

16-Bit Buswidth

232 Byte Register File

Full Duplex Serial Port

28 Interrupt Sources/16 Vectors

1.75 ms 16 x 16 Multiply (16 MHz)

3.0 ms 32/16 Divide (16 MHz)

Powerdown and Idle Modes

Five 8-Bit I/O Ports

High Speed I/O Subsystem

16-Bit Timer

16-Bit Up/Down Counter with Capture

Pulse-Width-Modulated Output

Four 16-Bit Software Timers

10-Bit A/D Converter with Sample/Hold

HOLD/HLDA Bus Protocol

Extended Temperature Available

16-Bit Watchdog Timer

12 MHz and 16 MHz Available

Dedicated 15-Bit Baud Rate Generator

The 8XC196KB is a 16-bit microcontroller available in three different memory varieties: ROMless (80C196KB),

8K ROM (83C196KB) and 8K OTP (One Time ProgrammableÐ87C196KB). The 8XC196KB is a high perform-

ance member of the MCS 96 microcontroller family. The 8XC196KB has the same peripheral set as the

8096BH and has a true superset of the 8096BH instructions. Intel’s CHMOS process provides a high perform-

ance processor along with low power consumption. To further reduce power requirements, the processor can

be placed into Idle or Powerdown Mode.

Bit, byte, word and some 32-bit operations are available on the 80C196KB. With a 16 MHz oscillator a 16-bit

addition takes 0.50 ms, and the instruction times average 0.37 ms to 1.1 ms in typical applications.

Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are

available for pulse or waveform generation. The high-speed output can also generate four software timers or

start an A/D conversion. Events can be based on the timer or up/down counter. Also provided on-chip are an

A/D converter, serial port, watchdog timer and a pulse-width-modulated output signal.

The 8XC196KB has a maximum guaranteed frequency of 12 MHz. The 8XC196KB16 has a maximum guaran-

teed frequency of 16 MHz. All references to the 80C196KB also refer to the 80C196KB16; 83C196KB, Rxxx;

87C196KB and 87C196KB16 unless otherwise noted. The ROM device does not have a speed indicator at the

end of the device name. Instead it has a ROM code number.

With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem-

perature range of 0 C to 70 C. With the extended temperature range option, operational characteristics are

guaranteed over the temperature range of 40 C to 85 C.

80-pin QFP (commercial only). Prefix Designators: T Extend-

Package Designators: N

ed Temperature.

68-pin PLCC, S

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

July 1994

Order Number: 270909-006

8XC196KB/8XC196KB16

270909–1

Figure 1. 8XC196KB Block Diagram

8XC196KB/8XC196KB16

Table 2. 8XC196KB Memory Map

PROCESS INFORMATION

Description

Address

This device is manufactured on P629.0 and 629.1, a

CHMOS III-E process. Additional process and reli-

ability information is available in Intel’s Components

Quality and Reliability Handbook, Order Number

210997.

External Memory or I/O

0FFFFH

04000H

Internal ROM/EPROM or External

Memory (Determined by EA)

3FFFH

2080H

Reserved. Must contain FFH.

(Note 5)

207FH

2040H

Upper Interrupt Vectors

203FH

2030H

ROM/EPROM Security Key

202FH

2020H

Reserved. Must contain FFH.

(Note 5)

201FH

201AH

Reserved. Must Contain 20H

(Note 5)

2019H

270909–2

CCB

2018H

EXAMPLE:

OTPROM, 16 MHz.

For complete package dimensional data, refer to the

Intel Packaging Handbook (Order Number 240800).

N87C196KB16

68-Lead

PLCC

Reserved. Must contain FFH.

(Note 5)

2017H

2014H

Lower Interrupt Vectors

2013H

2000H

NOTE:

1. EPROMs are available as One Time Programmable

(OTPROM) only.

Port 3 and Port 4

1FFFH

1FFEH

Figure 2. The 8XC196KB Nomenclature

External Memory

1FFDH

0100H

Table 1. Thermal Characteristics

Package

232 Bytes Register RAM (Note 1)

CPU SFR’s (Notes 1, 3)

00FFH

0018H

Type

PLCC

QFP

0017H

0000H

35 C/W

70 C/W

13 C/W

4 C/W

NOTES:

1. Code executed in locations 0000H to 00FFH will be

forced external.

2. Reserved memory locations must contain 0FFH unless

noted.

3. Reserved SFR bit locations must contain 0.

4. Refer to 8XC196KB quick reference for SFR descrip-

tions.

All thermal impedance data is approximate for static air

conditions at 1W of power dissipation. Values will change

depending on operation conditions and application. See

the Intel Packaging Handbook (order number 240800) for a

description of Intel’s thermal impedance test methodology.

5. WARNING: Reserved memory locations must not be

written or read. The contents and/or function of these lo-

cations may change with future revisions of the device.

Therefore, a program that relies on one or more of these

locations may not function properly.

8XC196KB/8XC196KB16

270909–3

Figure 3. 68-Pin Package (PLCC Top View)

NOTE:

The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown

above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROMless

(80C196KB) doesn’t use any of the programming pins.

8XC196KB/8XC196KB16

270909–4

NOTE:

N.C. means No Connect (do not connect these pins).

Figure 4. 80-Pin QFP Package

NOTE:

The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown

above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROMless

(80C196KB) doesn’t use any of the programming pins.

8XC196KB/8XC196KB16

PIN DESCRIPTIONS

Symbol

Name and Function

Main supply voltage (5V).

Digital circuit ground (0V). There are multiple V pins, all of them must be connected.

Reference voltage for the A/D converter (5V). V

is also the supply voltage to the analog

REF

portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D

and Port 0 to function.

ANGND

Reference ground for the A/D converter. Must be held at nominally the same potential as

. Connect V and ANGND at chip to avoid noise problems.

Programming voltage. Also timing pin for the return from power down circuit.

Input of the oscillator inverter and of the internal clock generator.

Output of the oscillator inverter.

XTAL1

XTAL2

CLKOUT

Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator

frequency. It has a 50% duty cycle.

RESET

Reset input to and open-drain output from the chip. Input low for at least 4 state times to reset

the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a

10-state-time RESET sequence.

BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus

cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit

cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.

NMI

A positive transition causes a vector through 203EH.

INST

Output high during an external memory read indicates the read is an instruction fetch and

output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated

only during external memory accesses.

Input for memory select (External Access). EA equal to a TTL-high causes memory accesses

to locations 2000H through 3FFFH to be directed to on-chip ROM/OTPROM. EA equal to a

TTL-low causes accesses to these locations to be directed to off-chip memory.

ALE/ADV

Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide

a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes

inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory

accesses.

Read signal output to external memory. RD is activated only during external memory reads.

WR/WRL

Write and Write Low output to external memory, as selected by the CCR. WR will go low for

every external write, while WRL will go low only for external writes where an even byte is

being written. WR/WRL is activated only during external memory writes.

BHE/WRH

READY

Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will

go low for external writes to the high byte of the data bus. WRH will go low for external writes

where an odd byte is being addressed. BHE/WRH is activated only during external memory

writes.

Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of

CLKOUT, the memory controller goes into a wait mode until the next positive transition in

CLKOUT occurs with READY high. When the external memory is not being used, READY has

no effect. Internal control of the number of wait states inserted into a bus cycle (held not

ready) is available in the CCR.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.

Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.

HSO

Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,

HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.

8XC196KB/8XC196KB16

PIN DESCRIPTIONS (Continued)

Symbol

Name and Function

Port 0

8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as

analog inputs to the on-chip A/D converter.

Port 1

Port 2

8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.

8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.

Pins P2.6 and P2.7 are quasi-bidirectional.

Ports 3 and 4

8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the

multiplexed address/data bus, which has strong internal pullups.

HOLD

HLDA

BREQ

Bus Hold input requesting control of the bus. Enabled by setting WSR.7.

Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.

Bus Request output activated when the bus controller has a pending external memory

cycle. Enabled by setting WSR.7.

TxD

RxD

The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In Mode 0 the pin is

used as the serial clock output.

Serial Port Receive pin used for serial port reception. In Mode 0 the pin functions as input or

output data.

EXTINT

T2CLK

A rising edge on the EXTINT pin will generate an external interrupt.

The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.

A rising edge on the T2RST pin will reset Timer2.

T2RST

PWM

The pulse width modulator output.

T2UP-DN

T2CAPTURE

PMODE

The T2UPDN pin controls the direction of Timer2 as an up or down counter.

A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register.

Programming Mode Select. Determines the EPROM programming algorithm that is

performed. PMODE is sampled after a chip reset and should be static while the part is

operating.

SID

Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing

programming verification acknowledgement.

PALE

PROG

PACT

PVAL

PVER

AINC

Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming

Mode. Used to indicate that Ports 3 and 4 contain a command/address.

Programming. Falling edge indicates valid data on PBUS and the beginning of

programming. Rising edge indicates end of programming.

Programming Active. Used in the Auto Programming Mode to indicate when programming

activity is complete.

Program Valid. This signal indicates the success or failure of programming in the Auto

Programming Mode. A zero indicates successful programming.

Program Verification. Used in Slave Programming and Auto CLB Programming Modes.

Signal is low after rising edge of PROG if the programming was not successful.

Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto

Increment will allow reading or writing of sequential EPROM locations without address

transactions across the PBUS for each read or write.

Ports 3

and 4

Address/Command/Data Bus. Used to pass commands, addresses, and data to and from

slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,

addresses and data to slaves. Also used in the Auto Programming Mode as a regular

system bus to access external memory. Should have pullups to V when used in slave

programming mode.

(Programming

Mode)

8XC196KB/8XC196KB16

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

Ambient Temperature

Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55 C to 125 C

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

Voltage On Any Pin to V ÀÀÀÀÀÀÀÀ 0.5V to 7.0V

(1)

Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

NOTE:

1. Power dissipation is based on package heat transfer lim-

itations, not device power consumption.

OPERATING CONDITIONS

(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)

Symbol

Description

Min

Max

Units

Ambient Temperature Under Bias

Digital Supply Voltage

4.50

3.5

5.50

Analog Supply Voltage

REF

OSC

Oscillator Frequency 12 MHz

Oscillator Frequency 16 MHz

MHz

NOTE:

ANGND and V should be nominally at the same potential.

DC CHARACTERISTICS

Symbol

Description

Input Low Voltage

Min

Max

0.8

Units

Test Conditions

0.5

Input High Voltage (All Pins except

XTAL1 and RESET)

0.2 V

0.9

0.5

IH1

IH2

Input High Voltage on XTAL 1

Input High Voltage on RESET

Output Low Voltage

0.7 V

0.5

2.6

0.3

0.45

1.5

200 mA

3.2 mA

7 mA

e b

Output High Voltage

(2)

(Standard Outputs)

0.3

0.7

1.5

200 mA

3.2 mA

7 mA

e b

Output High Voltage

(Quasi-bidirectional Outputs)

0.3

0.7

1.5

10 mA

30 mA

60 mA

OH1

(1)

0.3V

Input Leakage Current

(3)

(Std. Inputs)

Input Leakage Current (Port 0)

1 to 0 Transition Current

(1)

(QBD Pins)

LI1

REF

800

2.0V

(1)

Logical 0 Input Current (QBD Pins)

0.45V

8XC196KB/8XC196KB16

Test Conditions

DC CHARACTERISTICS (Continued)

(7)

Symbol

Description

Min Typ

Max

Units

Logical 0 Input Current in Reset

BHE, WR, P2.0

850

0.45V

2.0V

IL1

IL2

IH1

Logical 0 Input Current in Reset

ALE, RD, INST

Logical 1 Input Current

on NMI Pin

100

Hyst.

Hysteresis on RESET Pin

Active Mode Current in Reset

A/D Converter Reference Current

Idle Mode Current

300

16 MHz

XTAL1

REF

5.5V

REF

IDLE

50K

Powerdown Mode Current

Reset Pullup Resistor

REF

RST

Pin Capacitance (Any Pin to V

)

1.0 MHz

TEST

NOTES: (Notes apply to all specifications)

1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.

2. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,

TXD/P2.0 and RXD (in serial mode 0). The V specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.

3. Standard Inputs include HSI pins, EA, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/

P2.4.

4. Maximum current per pin must be externally limited to the following values if V

below V

is held above 0.45V or V is held

on Output pins: 10 mA

0.7V:

on quasi-bidirectional pins: self limiting

on Standard Output pins: 10 mA

5. Maximum current per bus pin (data and control) during normal operation is 3.2 mA.

6. During normal (non-transient) conditions the following total current limits apply:

Port 1, P2.6

: 29 mA

: 13 mA

is self limiting

: 26 mA

: 11 mA

: 52 mA

: 13 mA

HSO, P2.0, RXD, RESET

P2.5, P2.7, WR, BHE

AD0–AD15

: 52 mA

: 13 mA

RD, ALE, INST–CLKOUT

7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature

and V

5V.

REF

Max

FREQ 8.43

Max

3.88

270909–5

FREQ 2.2

1.65

IDLE

Figure 6. I and I

vs Frequency

IDLE

8XC196KB/8XC196KB16

AC CHARACTERISTICS

Test Conditions: Capacitive load on all pins

12/16 MHz

OSC

100 pF, Rise and fall times

10 ns, F

The system must meet these specifications to work with the 87C196KB:

Symbol

Description

Min

Max

Units

Notes

OSC

Address Valid to READY Setup

NonREADY Time

2 T

AVYV

YLYH

CLYX

LLYX

AVGV

CLGX

AVDV

RLDV

CLDV

RHDZ

RXDX

No upper limit

READY Hold after CLKOUT Low

READY Hold after ALE Low

Address Valid to Buswidth Setup

Buswidth Hold after CLKOUT Low

Address Valid to Input Data Valid

RD Active to Input Data Valid

CLKOUT Low to Input Data Valid

End of RD to Input Data Float

Data Hold after RD Inactive

(Note 1)

OSC

2 T

OSC

2 T

3 T

(Note 2)

OSC

NOTES:

1. If max is exceeded, additional wait states will occur.

2. When using wait states, add 2 T

n where n

number of wait states.

OSC

8XC196KB/8XC196KB16

AC CHARACTERISTICS (Continued)

Test Conditions: Capacitive load on all pins

12/16 MHz

OSC

100 pF, Rise and fall times

10 ns, F

The 87C196KB will meet these specifications:

Symbol

Description

Frequency on XTAL1 12 MHz

Frequency on XTAL1 16 MHz

Min

3.5

Max

Units

MHz

Notes

(Note 2)

12.0

16.0

286

XTAL

OSC

3.5

1/F

12 MHz

16 MHz

83.3

62.5

XTAL

OSC

110

XTAL1 High to CLKOUT High or Low

CLKOUT Cycle Time

XHCH

CLCL

CHCL

CLLH

LLCH

LHLH

LHLL

2 T

OSC

CLKOUT High Period

OSC

CLKOUT Falling Edge to ALE Rising

ALE Falling Edge to CLKOUT Rising

ALE Cycle Time

4 T

(Note 3)

OSC

ALE High Period

OSC

Address Setup to ALE Falling Edge

Address Hold after ALE Falling Edge

ALE Falling Edge to RD Falling Edge

RD Low to CLKOUT Falling Edge

RD Low Period

AVLL

LLAX

LLRL

RLCL

RLRH

RHLH

RLAZ

LLWL

CLWL

QVWH

CHWH

WLWH

WHQX

WHLH

WHBX

RHBX

WHAX

RHAX

(Note 3)

(Note 1)

OSC

RD Rising Edge to ALE Rising Edge

RD Low to Address Float

OSC

ALE Falling Edge to WR Falling Edge

CLKOUT Low to WR Falling Edge

Data Stable to WR Rising Edge

CLKOUT High to WR Rising Edge

WR Low Period

OSC

(Note 3)

(Note 1)

OSC

Data Hold after WR Rising Edge

WR Rising Edge to ALE Rising Edge

BHE, INST HOLD after WR Rising Edge

BHE, INST HOLD after RD Rising Edge

AD8–15 hold after WR Rising Edge

AD8–15 hold after RD Rising Edge

OSC

NOTES:

1. Assuming back-to-back bus cycles.

2. Testing performed at 3.5 MHz, however, the device is static by design and will typically operate below 1 Hz.

3. When using wait states, all 2 T

n where n

number of wait states.

OSC

8XC196KB/8XC196KB16

System Bus Timings

270909–6

8XC196KB/8XC196KB16

READY Timings (One Wait State)

270909–7

Buswidth Bus Timings

270909–8

8XC196KB/8XC196KB16

HOLD/HLDA Timings

Symbol

Description

Min

Max

Units

Notes

HOLD Setup

(Note 1)

HVCH

CLKOUT Low to HLDA Low

CLHAL

CLBRL

HALAZ

HALBZ

CLHAH

CLBRH

HAHAX

HAHAV

HAHBX

HAHBV

CLLH

CLKOUT Low to BREQ Low

HLDA Low to Address Float

HLDA Low to BHE, INST, RD, WR Float

CLKOUT Low to HLDA High

CLKOUT Low to BREQ High

HLDA High to Address No Longer Float

HLDA High to Address Valid

HLDA High to BHE, INST, RD, WR No Longer Float

HLDA High to BHE, INST, RD, WR Valid

CLKOUT Low to ALE High

NOTE:

1. To guarantee recognition at next clock.

Maximum Hold Latency

Bus Cycle Type

Internal Access

Latency

1.5 States

2.5 States

4.5 States

16-Bit External Execution

8-Bit External

270909–9

8XC196KB/8XC196KB16

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

3.5

Max

12.0

Units

MHz

1/T

Oscillator Frequency 12 MHz

Oscillator Frequency 16 MHz

Oscillator Period 12 MHz

Oscillator Period 16 MHz

High Time

XLXL

3.5

83.3

62.5

21.25

286

XLXL

XHXX

XLXX

XLXH

XHXL

Low Time

Rise Time

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

270909–10

An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to

interaction between the amplifier and its feedback capacitance. Once the external signal meets the V and

specifications, the capacitance will not exceed 20 pF.

EXTERNAL CRYSTAL CONNECTIONS

EXTERNAL CLOCK CONNECTIONS

270909–11

NOTE:

Keep oscillator components close to chip and use

270909–12

short, direct traces to XTAL1, XTAL2 and V . When

* Required if open-collector TTL driver used

Not needed if CMOS driver is used.

20 pF. When using

using crystals, C1

20 pF, C2

ceramic resonators, consult manufacturer for recom-

mended circuitry.

AC TESTING INPUT, OUTPUT WAVEFORMS

FLOAT WAVEFORMS

270909–13

AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for

a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic

‘‘1’’ and 0.8V for a Logic ‘‘0’’.

270909–14

For Timing Purposes a Port Pin is no Longer Floating when a

200 mV change from Load Voltage Occurs and Begins to Float

when a 200 mV change from the Loaded V /V Level occurs;

OH OL

15 mA.

OL OH

8XC196KB/8XC196KB16

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its

condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions:

Signals:

- High

- Address

- BHE

- Buswidth

- HOLD

- RD

- Low

- WR/WRH/WRL

- XTAL1

- Valid

BR - BREQ

HA - HLDA

- No Longer Valid

- Floating

- CLKOUT

- DATA IN

- ALE/ADV

- DATA OUT

- READY

AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE

SERIAL PORT TIMINGÐSHIFT REGISTER MODE (MODE 0)

Symbol

Parameter

Min

6 T

Max

Units

Serial Port Clock Period (BRR 8002H)

XLXL

OSC

Serial Port Clock Falling Edge to Rising Edge (BRR 8002H) 4 T

50 ns

50 4 T

XLXH

XLXL

OSC

Serial Port Clock Period (BRR

8001H)

4 T

50 ns

OSC

Serial Port Clock Falling Edge to Rising Edge (BRR

Output Data Setup to Clock Rising Edge

Output Data Hold after Clock Rising Edge

Next Output Data Valid after Clock Rising Edge

Input Data Setup to Clock Rising Edge

Input Data Hold after Clock Rising Edge

Last Clock Rising to Output Float

8001H) 2 T

50 2 T

XLXH

QVXH

XHQX

XHQV

DVXH

XHDX

XHQZ

OSC

2 T

OSC

2 T

OSC

2 T

OSC

WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE

SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE (MODE 0)

270909–18

8XC196KB/8XC196KB16

State times are calculated as follows:

10-BIT A/D CHARACTERISTICS

At a clock speed of 6 MHz or less, the clock prescal-

er should be disabled. This is accomplished by set-

state time

XTAL1

ting IOC2.4

The converter is ratiometric, so the absolute accura-

cy is directly dependent on the accuracy and stability

At higher frequencies (greater than 6 MHz) the clock

of V

. V

must be close to V since it supplies

prescaler should be enabled (IOC2.4

the comparator to settle.

0) to allow

REF REF CC

both the resistor ladder and the digital section of the

converter.

The table below shows two different clock speeds

and their corresponding A/D conversion and sample

times.

See the MCS-96 A/D Converter Quick Reference

for definition of A/D terms.

Example Sample and Conversion Times

Sample Time

at Clock

Conversion

Time at

Clock Speed

(ms)

Conversion

Time

(States)

A/D Clock

Prescaler

Clock Speed

(MHz)

Sample Time

(States)

Speed

(ms)

IOC2.4

1.875

2.667

156.5

89.5

19.6

29.8

OFF

A/D CONVERTER SPECIFICATIONS

Parameter

Resolution

Typical(1)

Minimum

Maximum

Units*

Notes

1024

Levels

Bits

Absolute Error

LSBs

0.25 0.50

Full Scale Error

0.25 0.50

Zero Offset Error

1.5 2.5

Non-Linearity Error

Differential Non-Linearity Error

Channel-to-Channel Matching

Repeatability

0.1

0.25

Temperature Coefficients:

Offset

Full Scale

0.009

LSB/ C

Differential Non-Linearity

LSB/ C

Off Isolation

Feedthrough

2, 3

Power Supply Rejection

Input Series Resistance

DC Input Leakage

750

1.2K

3.0

Sampling Capacitor

NOTES:

*An ‘‘LSB’’, as used here, has a value of approximately 5 mV.

1. Typical values are expected for most devices at 25 C.

2. DC to 100 KHz.

3. Multiplexer Break-Before-Make Guaranteed.

4. Resistance from device pin, through internal MUX, to sample capacitor.

8XC196KB/8XC196KB16

OTPROM SPECIFICATIONS

OTPROM PROGRAMMING OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Units

Ambient Temperature During Programming

Supply Voltages During Programming

Programming Mode Supply Voltage

EPROM Programming Supply Voltage

Digital and Analog Ground

(1)

, V , V

CC PD REF

4.5

5.5

(2)

12.50

13.0

(2)

(3)

, ANGND

Oscillator Frequency 12 MHz

6.0

12.0

16.0

MHz

OSC

Oscillator Frequency 16 MHz

6.0

NOTES:

1. V , V and V

2. V and V must never exceed the maximum voltage for any amount of time or the device may be damaged.

should nominally be at the same voltage during programming.

REF

CC PD

EA PP

3. V and ANGND should nominally be at the same voltage (0V) during programming.

AC OTPROM PROGRAMMING CHARACTERISTICS

Symbol

Description

Reset High to First PALE Low

PALE Pulse Width

Min

1100

Max

Units

OSC

SHLL

LLLH

AVLL

LLAX

LLVL

PLDV

PHDX

DVPL

PLDX

PLPH

PHLL

LHPL

PHPL

PHIL

Address Setup Time

Address Hold Time

PALE Low to PVER Low

PROG Low to Word Dump Valid

Word Dump Data Hold

Data Setup Time

Data Hold Time

PROG Pulse Width

PROG High to Next PALE Low

PALE High to PROG Low

PROG High to Next PROG Low

PROG High to AINC Low

AINC Pulse Width

120

220

120

ILIH

PVER Hold after AINC Low

AINC Low to PROG Low

PROG High to PVER Low

ILVH

ILPL

170

PHVL

8XC196KB/8XC196KB16

DC OTPROM PROGRAMMING CHARACTERISTICS

Symbol

Description

Min

Max

Units

Supply Current (When Programming)

100

NOTE:

Do not apply V until V

damaged.

is stable and within specifications and the oscillator/clock has stabilized or the device may be

OTPROM PROGRAMMING WAVEFORMS

SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

270909–15

SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT

270909–16

8XC196KB/8XC196KB16

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE

AND AUTO INCREMENT

270909–17

8XC196KB/8XC196KB16

The following differences exist between this data

sheet (270909-005) and (270909-004):

FUNCTIONAL DEVIATIONS

Devices marked with an ‘‘E’’, ‘‘F’’ or ‘‘G’’ have the

following errata.

1. I MAX was 650 mA (270909-004). Now I

MAX is 800 mA (270909-005).

2. I was named I (270909-004). Now I

IL2

IL1

1. Missed Interrupt on P0.7, EXTINT

correctly named (270909-005).

3. I

was omitted (270909-004). I

MAX was

MAX is 850 mA (270909-005).

Interrupts occurring on P0.7 could be missed since

the INT PEND EXTINT bit may not be set. See

IL1

added. I

IL1

techbit MC0893.

4. T

and T

(270909-004) were removed.

LLGV

LLYV

These timings are not required in high-speed sys-

tem designs.

2. HSI MODE Divide-by-Eight

5. An errata was added to the known errata section.

There is a possibility to miss an external interrupt

on P0.7 EXTINT.

See Faxback 2192

REVISION HISTORY

The following differences exist between this data

sheet (270909-004) and (270909-003):

This data sheet (270909-006) is valid for devices

with an ‘‘E’’, ‘‘F’’ or ‘‘G’’ at the end of the top side

tracking number. Data sheets are changed as new

device information becomes available. Verify with

your local Intel sales office that you have the latest

version before finalizing a design or ordering devic-

es.

1. The

ROM

(80C196KB),

and

ROMless

(83C196KB) were combined with this data sheet

resulting in no specification differences.

2. The description of the prescalar bit for the A/D

has been enhanced.

MIN is 20 ns (270909-004).

3. T

MIN was

15 ns (270909-003). Now

HAHBV

The following differences exist between this data

sheet (270909-006) and (270909-005):

4. T

MAX was 1 TOSC (270909-003). Now

MAX is 2 TOSC (270909-004). This should

XHQZ

1. Removed ‘‘Word Addressable Only’’ from Port 3

and 4 in Table 2.

have no impact on designs using synchronous

serial mode 0.

2. Removed ICC1, active mode current at 3.5 MHz.

This specification is not longer required.

5. The change indicators for the 80C196KB are

‘‘E’’, ‘‘F’’ and ‘‘G’’. Previously there was only one

change indicator ‘‘E’’. The change indicator is

used for tracking purposes. The change indicator

is the last character in the FPO number. The FPO

number is the second line on the top side of the

device.

3. Removed TLLYV and TLLGV from waveform dia-

grams.

4. The HSI errata and CMPL with R0 were removed

as this is now considered normal operation.

5. The HSI MODE divide-by-eight errata was add-

ed to the known errata section.

8XC196KB/8XC196KB16

The following differences exist between (-003) and

version (-002).

Differences between the -002 and -001 data sheets.

1. The -001 version of this data sheet was valid for

devices marked with a ‘‘C’’ at the end of the top

side tracking number.

1. The 12 MHz and 16 MHz devices were com-

bined in this data sheet. The 87C196KB 12 MHz

only data sheet (272035-001) is now obsolete.

2. Added 64L SDIP and 80L QFP packages.

3. Added IIH1.

2. Changes were made to the format of the data

sheet and the SFR descriptions were removed.

4. Changed T

5. Changed T

Min from

Max from

10 ns to

5 ns.

CHWH

3. The -002 version of this data sheet was valid for

devices marked with a ‘‘B’’ or a ‘‘D’’ at the end

of the top side tracking number.

15 ns.

CHWH

6. Changed T

Min from T

Max from T

Min from T

20 ns to

10 ns to

15 ns to

10 ns to

WLWH

WHQX

WHLH

WHBX

HVCH

OSC

15 ns.

OSC

4. The OSCILLATOR errata was removed.

7. Changed T

OSC

5. An errata was not documented in the -002 data

sheet for devices marked with a ‘‘B’’ or a ‘‘D’’.

This is the DIVIDE DURING HOLD/READY er-

rata. When HOLD or READY is active and DIV/

DIVB is the last instruction in the queue, the di-

vide result may be incorrect.

OSC

15 ns.

8. Changed T

OSC

15 ns.

9. Changed T

OSC

10 ns.

40 ns to Min

6. T

was changed from Min

XCH

20 ns.

10. Changed T

OSC

15 ns.

OSC

7. T

RLCL

4 ns.

was changed from Min

5 ns to Min

11. Changed T

12. Remove T

Min from 85 ns to 55 ns.

Max.

HVCH

e b

9. I was changed from Max

IL1

6 mA to Max

15 ns.

13. Changed T

14. Changed T

15. Changed T

16. Changed T

17. Changed T

Min from

10 ns to

CLHAL

CLBRL

HAHAX

7 mA.

Max from 20 ns to 15 ns.

e b

10. T

was changed from Min

15 ns.

10 ns to

HAHBV

e b

15 ns.

Min

Min from

10 ns to

Max from 20 ns to 15 ns.

15 ns.

Min from

10 ns to

18. Added HSI description to Functional Deviations.

19. Added Oscillator description to Functional Devi-

ations.

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N87C196KB16产品参数

型号:	N87C196KB16
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	LCC
包装说明：	PLASTIC, LCC-68
针数：	68
Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01
风险等级：	5.72
具有ADC：	YES
其他特性：	FOUR SOFTWARE TIMERS; ROM PROTECT; DYNAMIC BUS SIZING
地址总线宽度：	16
位大小：	16
边界扫描：	NO
最大时钟频率：	16 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：	16
格式：	FIXED POINT
集成缓存：	NO
JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0
长度：	24.2 mm
低功率模式：	YES
DMA 通道数量：
外部中断装置数量：	2
I/O 线路数量：	40
串行 I/O 数：	1
端子数量：	68
计时器数量：	1
片上数据RAM宽度：	8
片上程序ROM宽度：	8
最高工作温度：	70 °C
最低工作温度：
PWM 通道：	YES
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ
封装形状：	SQUARE
封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
RAM（字节）：	232
RAM（字数）：	232
ROM（单词）：	8192
ROM可编程性：	OTPROM
座面最大高度：	4.83 mm
速度：	16 MHz
子类别：	Microcontrollers
最大压摆率：	70.51 mA
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	24.2 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

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