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产品型号NBSG53AMNR2的Datasheet PDF文件预览

NBSG53A  
2.5V/3.3VꢀSiGe Selectable  
Differential Clock and Data  
D Flip−Flop/Clock Divider  
with Reset and OLS*  
http://onsemi.com  
MARKING  
The NBSG53A is a multi−function differential D flip−flop (DFF) or  
fixed divide by two (DIV/2) clock generator. This is a part of the  
GigaComm  
family of high performance Silicon Germanium  
DIAGRAM**  
products. A strappable control pin is provided to select between the  
two functions. The device is housed in a low profile 4x4 mm 16−pin  
Flip−Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.  
The NBSG53A is a device with data, clock, OLS, reset, and select  
inputs. Differential inputs incorporate internal 50 W termination  
resistors and accept NECL (Negative ECL), PECL (Positive ECL),  
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to  
program the peak−to−peak output amplitude between 0 and 800 mV  
in five discrete steps. The RESET and SELECT inputs are  
single−ended and can be driven with either LVECL or  
LVCMOS/LVTTL input levels.  
SG  
53A  
LYW  
FCBGA−16  
BA SUFFIX  
CASE 489  
SG53A  
ALYW  
Data is transferred to the outputs on the positive edge of the clock.  
The differential clock inputs of the NBSG53A allow the device to also  
be used as a negative edge triggered device.  
QFN−16  
MN SUFFIX  
CASE 485G  
A = Assembly Location  
L = Wafer Lot  
Maximum Input Clock Frequency (DFF) > 8 GHz Typical  
(See Figures 4, 6, 8, 10, and 11)  
Y = Year  
W = Work Week  
Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical  
(See Figures 5, 7, 9, 10, and 11)  
**For further details, refer to Application  
Note AND8002/D  
210 ps Typical Propagation Delay (OLS = FLOAT)  
45 ps Typical Rise and Fall Times (OLS = FLOAT)  
DIV/2 Mode (Active with Select Low)  
DFF Mode (Active with Select High)  
Board  
Description  
NBSG53ABAEVB NBSG53ABA Evaluation Board  
Selectable Swing PECL Output with Operating Range: V = 2.375 V  
CC  
to 3.465 V with V = 0 V  
EE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 16 of this data sheet.  
Selectable Swing NECL Output with NECL Inputs with  
Operating Range: V = 0 V with V = −2.375 V to −3.465 V  
CC  
EE  
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV  
Peak−to−Peak Output)  
50 W Internal Input Termination Resistors on all Differential Inputs  
*Output Level Select  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
March, 2004 − Rev. 5  
NBSG53A/D  
NBSG53A  
1
2
3
4
V
CC  
R
SEL OLS  
Exposed Pad  
(EP)  
16  
15  
14  
13  
VTD  
D
D
VTD  
A
B
C
VTCLK  
CLK  
V
EE  
1
2
3
4
12  
11  
10  
9
VTCLK  
VTCLK  
R
CLK  
CLK  
V
CC  
Q
Q
Q
Q
V
NBSG53A  
CLK  
V
EE  
VTCLK  
CC  
V
CC  
SEL  
OLS  
D
5
6
7
8
VTD  
D
D
VTD  
Figure 1. BGA−16 Pinout (Top View)  
Table 1. Pin Description  
Figure 2. QFN−16 Pinout (Top View)  
Pin  
BGA  
C2  
QFN  
Name  
VTCLK  
CLK  
I/O  
Description  
1
2
Internal 50 W Termination Pin. See Table 4.  
C1  
ECL, CML,  
LVCMOS,  
LVDS, LVTTL  
Input  
Inverted Differential Input.  
B1  
3
CLK  
ECL, CML,  
LVCMOS,  
LVDS, LVTTL  
Input  
Noninverted Differential Input.  
B2  
A1  
A2  
4
5
6
VTCLK  
VTD  
D
Internal 50 W Termination Pin. See Table 4.  
Internal 50 W termination pin. See Table 4.  
Inverted Differential Input.  
ECL, CML,  
LVCMOS,  
LVDS, LVTTL  
Input  
A3  
7
D
ECL, CML,  
LVCMOS,  
LVDS, LVTTL  
Input  
Noninverted Differential Input.  
A4  
D1,B3  
B4  
8
VTD  
Internal 50 W Termination Pin. See Table 4.  
9,16  
10  
V
CC  
Positive Supply Voltage  
Q
RSECL Output  
Inverted Differential Output. Typically Terminated with 50 W Resistor to  
= V − 2 V.  
V
TT  
CC  
C4  
11  
Q
RSECL Output  
Noninverted Differential Output. Typically Terminated with 50 W Resistor to  
= V − 2 V.  
V
TT  
CC  
C3  
D4  
D3  
12  
13  
14  
V
Negative Supply Voltage  
EE  
OLS*  
Input  
Input Pin for the Output Level Select (OLS). See Table 2.  
SEL  
R
LVECL,  
LVCMOS,  
LVTTL Input  
Select Logic Input. Internal 75 kW to V  
.
EE  
D2  
15  
LVECL,  
LVCMOS,  
LVTTL Input  
Reset D Flip−Flop. Internal 75 kW to V  
.
EE  
N/A  
EP  
Exposed Pad. (Note 1)  
1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on  
CC  
EE  
package bottom (see case drawing) must be attached to a heat−sinking conduit.  
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination volt-  
age, and if no signal is applied then the device will be susceptible to self−oscillation.  
3. When an output level of 400 mV is desired and V − V > 3.0 V, 2KW resistor should be connected from OLS pin to V .  
CC  
EE  
EE  
http://onsemi.com  
2
 
NBSG53A  
V
CC  
OLS  
VTD  
50 W  
50 W  
2
2
2
D
D
Q
D
Flip−Flop  
(DFF)  
R
1
0
Q
Q
2
VTD  
2
2
Q
D
VTCLK  
Flip−Flop  
(DIV/2)  
50 W  
50 W  
2
CLK  
CLK  
R
VTCLK  
R
SEL  
75 kW  
75 kW  
V
EE  
Figure 3. Simplified Logic Diagram  
Table 2. OUTPUT LEVEL SELECT (OLS)  
Table 3. TRUTH TABLE  
OLS  
Q/Q VPP  
800 mV  
200 mV  
600 mV  
0
OLS Sensitivity  
OLS − 75 mV  
OLS $ 150 mV  
OLS $ 100 mV  
OLS $ 75 mV  
OLS + 100 mV  
N/A  
R
H
L
SEL  
x
D
x
CLK  
Q
L
Function  
Reset  
DFF  
V
CC  
x
Z
Z
Z
V
V
V
− 0.4 V  
CC  
− 0.8 V  
CC  
− 1.2 V  
CC  
(Note 4)  
Float  
H
L
H
x
L
L
H
H
Q
DFF  
L
L
DIV/2  
V
EE  
400 mV  
600 mV  
Z = LOW to HIGH Transition  
4. When an output level of 400 mV is desired and  
− V > 3.0 V, 2.0 kW resistor should be connected from  
V
CC  
EE  
OLS to V  
.
EE  
Table 4. INTERFACING OPTIONS  
INTERFACING OPTIONS  
CML  
CONNECTIONS  
Connect VTCLK, VTD and VTCLK, VTD to V  
CC  
LVDS  
Connect VTCLK, VTD and VTCLK, VTD Together  
Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (V  
Standard ECL Termination Techniques  
AC−COUPLED  
)
IHCMR  
RSECL, PECL, NECL  
LVTTL, LVCMOS  
An External Voltage (V  
) should be Applied to the Unused Complementary Differential Input. Nominal  
THR  
V
is 1.5 V for LVTTL and V /2 for LVCMOS Inputs. This Voltage must be within the V  
Specification.  
THR  
CC  
THR  
http://onsemi.com  
3
 
NBSG53A  
Table 5. ATTRIBUTES  
Characteristics  
Positive Operating Voltage Range for V (V = 0 V)  
Value  
2.375 V to 3.465 V  
−2.375 V to −3.465 V  
75 kW  
CC  
EE  
Negative Operating Voltage Range for V (V = 0 V)  
EE  
CC  
Internal Input Pulldown Resistor (R, SEL)  
ESD Protection  
Human Body Model  
Machine Model  
Charged Device Model  
> 1.5 kV  
> 50 V  
> 4 kV  
Moisture Sensitivity (Note 5)  
16−FCBGA  
16−QFN  
Level 3  
Level 1  
Flammability Rating  
Oxygen Index  
UL 94 V−0 @ 0.125 in  
28 to 34  
482  
Transistor Count  
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
5. For additional information, refer to Application Note AND8003/D.  
Table 6. MAXIMUM RATINGS  
Symbol  
Parameter  
Positive Power Supply  
Condition 1  
= 0 V  
Condition 2  
Rating  
Units  
V
CC  
V
EE  
V
I
V
V
3.6  
V
V
EE  
Negative Power Supply  
= 0 V  
−3.6  
CC  
Positive Input  
Negative Input  
V
EE  
V
CC  
= 0 V  
= 0 V  
V v V  
3.6  
−3.6  
V
V
I
I
CC  
EE  
V w V  
V
INPP  
Differential Input Voltage  
|D − D|  
V
CC  
V
CC  
− V  
− V  
w
2.8 V  
2.8 V  
2.8  
|V − V  
CC  
V
V
EE  
EE  
<
|
EE  
I
I
Input Current Through R (50 W Resistor)  
Static  
Surge  
45  
80  
mA  
mA  
IN  
T
Output Current  
Continuous  
Surge  
25  
50  
mA  
mA  
OUT  
T
Operating Temperature Range  
Storage Temperature Range  
16 FCBGA  
16 QFN  
−40 to +70  
−40 to +85  
°C  
A
T
stg  
−65 to +150  
°C  
q
Thermal Resistance (Junction−to−Ambient) 0 LFPM  
16 FCBGA  
16 FCBGA  
16 QFN  
108  
86  
41.6  
35.2  
°C/W  
°C/W  
°C/W  
°C/W  
JA  
JC  
(Note 6)  
500 LFPM  
0 LFPM  
500 LFPM  
16 QFN  
q
Thermal Resistance (Junction−to−Case)  
Wave Solder  
2S2P (Note 6)  
2S2P (Note 7)  
16 FCBGA  
16 QFN  
5.0  
4.0  
°C/W  
°C/W  
T
sol  
< 15 Seconds  
225  
°C  
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit  
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,  
damage may occur and reliability may be affected.  
6. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).  
7. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.  
http://onsemi.com  
4
 
NBSG53A  
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT V = 2.5 V; V = 0 V (Note 8)  
CC  
EE  
−40°C  
Typ  
25°C  
70°C(BGA)/85°C(QFN)**  
Min  
33  
Max  
Min  
33  
Typ  
45  
Max  
57  
Min  
33  
Typ  
45  
Max  
57  
Symbol  
Characteristic  
Negative Power Supply Current  
Output HIGH Voltage (Note 9)  
Output LOW Voltage (Note 9)  
Unit  
mA  
mV  
mV  
I
EE  
45  
57  
V
1460  
1510  
1560  
1490  
1540  
1590  
1515  
1565  
1615  
OH  
OL  
V
(OLS = V  
)
555  
705  
1295  
895  
1505  
1095  
855  
595  
1270  
810  
1490  
1040  
745  
1330  
930  
1540  
1130  
895  
625  
1295  
840  
1510  
1065  
775  
1355  
960  
1560  
1155  
925  
CC  
(OLS = V − 0.4 V) 1235  
1355  
1015  
1555  
1185  
1390  
1050  
1590  
1220  
1415  
1080  
1610  
1245  
CC  
(OLS = V − 0.8 V, OLS = FLOAT)  
775  
(OLS = V − 1.2 V) 1455  
CC  
CC  
(OLS = V  
)
1005  
EE  
V
Output Voltage Amplitude  
mV  
OUTPP  
(OLS = V  
)
715  
125  
525  
0
805  
215  
615  
5
705  
120  
520  
0
795  
210  
610  
0
700  
120  
515  
0
790  
210  
605  
5
CC  
(OLS = V − 0.4 V)  
CC  
(OLS = V − 0.8 V, OLS = FLOAT)  
CC  
(OLS = V − 1.2 V)  
CC  
(OLS = V  
)
325  
415  
320  
410  
320  
410  
EE  
V
V
V
V
V
V
Input HIGH Voltage (Single−Ended)  
V
+
V
V
V
+
V
V
V
1275  
+
V
1000*  
V
CC  
mV  
mV  
mV  
mV  
mV  
V
IH  
EE  
CC  
CC  
EE  
CC  
CC  
EE  
CC  
(Notes 11 and 13)  
CLK, CLK, D, D 1275 1000*  
1275 1000*  
Input LOW Voltage (Single−Ended)  
V
V
1400*  
V
IH  
V
V
1400*  
V
IH  
V
V
CC  
V −  
IH  
150  
IL  
EE  
CC  
EE  
CC  
EE  
(Notes 12 and 13)  
CLK, CLK, D, D  
150  
150  
1400*  
Input High Voltage (Single−Ended)  
IH  
R, SEL 1290  
V
CC  
1355  
V
CC  
1415  
V
CC  
Input Low Voltage (Single−Ended)  
IL  
R, SEL  
V
890  
V
955  
V
EE  
1015  
EE  
EE  
Input Threshold Voltage (Single−Ended)  
(Note 13)  
V
1125  
+
V
CC  
V
1125  
+
V
CC  
V
1125  
+
V
CC  
THR  
IHCMR  
EE  
EE  
EE  
75  
75  
75  
Input HIGH Voltage Common Mode  
Range (Differential Configuration)  
(Note 10)  
1.2  
2.5  
1.2  
2.5  
1.2  
2.5  
R
TIN  
Internal Input Termination Resistor  
45  
50  
55  
45  
50  
55  
45  
50  
55  
W
I
IH  
Input HIGH Current (@V  
)
R, SEL  
CLK, CLK, D, D  
35  
5
100  
50  
35  
5
100  
50  
35  
5
100  
50  
mA  
IH  
I
IL  
Input LOW Current (@V ) R, SEL  
20  
5
100  
50  
20  
5
100  
50  
20  
5
100  
50  
mA  
IL  
CLK, CLK, D, D  
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit  
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared  
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit  
values are applied individually under normal operating conditions and not valid simultaneously.  
8. Input and output parameters vary 1:1 with V . V can vary +0.125 V to −0.965 V.  
CC  
EE  
9. All outputs loaded with 50 W to V − 2.0 V.  
CC  
10.V  
min varies 1:1 with V , V  
max varies 1:1 with V . The V  
range is referenced to the most positive side of the differential  
IHCMR  
EE IHCMR  
CC  
IHCMR  
input signal.  
11. V cannot exceed V . |V − V | < 2600 mV.  
THR  
IH  
CC  
IH  
12.V always w V . |V − V  
| < 2600 mV.  
IL  
EE  
IL  
THR  
13.V  
is the voltage applied to one input when running in single−ended mode.  
THR  
*Typicals used for testing purposes.  
**The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have  
maximum ambient temperature specification of 85°C.  
http://onsemi.com  
5
 
NBSG53A  
Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT V = 3.3 V; V = 0 V (Note 14)  
CC  
EE  
−40°C  
Typ  
25°C  
70°C(BGA)/85°C(QFN)***  
Min  
35  
Max  
59  
Min  
35  
Typ  
47  
Max  
59  
Min  
35  
Typ  
47  
Max  
59  
Symbol  
Characteristic  
Unit  
mA  
mV  
mV  
I
EE  
Negative Power Supply Current  
Output HIGH Voltage (Note 15)  
Output LOW Voltage (Note 15)  
47  
V
2260  
2310  
2360  
2290  
2340  
2390  
2315  
2365  
2415  
OH  
OL  
V
(OLS = V  
)
1320  
1470  
2090  
1670  
2310  
1875  
1620  
2150  
1790  
2360  
1965  
1360  
2065  
1585  
2290  
1820  
1510  
2125  
1705  
2340  
1910  
1660  
2185  
1825  
2390  
2000  
1390  
2090  
1615  
2315  
1850  
1540  
2150  
1735  
2365  
1940  
1690  
2210  
1855  
2415  
2030  
CC  
(OLS = V − 0.4 V) 2030  
CC  
(OLS = V − 0.8 V, OLS = FLOAT) 1550  
CC  
(OLS = V − 1.2 V) 2260  
CC  
**(OLS = V  
)
1785  
EE  
V
Output Amplitude Voltage  
mV  
OUTPP  
(OLS = V  
)
750  
130  
550  
0
840  
220  
640  
0
740  
125  
545  
0
830  
215  
635  
0
735  
125  
540  
0
825  
215  
630  
0
CC  
(OLS = V − 0.4 V)  
CC  
(OLS = V − 0.8 V, OLS = FLOAT)  
CC  
(OLS = V − 1.2 V)  
CC  
**(OLS = V  
)
345  
435  
340  
430  
335  
425  
EE  
V
V
V
V
V
V
Input HIGH Voltage (Single−Ended)  
V
+
V
V
V
+
V
V
V
1275  
+
V
1000*  
V
CC  
mV  
mV  
mV  
mV  
mV  
V
IH  
EE  
CC  
CC  
EE  
CC  
CC  
EE  
CC  
(Notes 17 and 19)  
CLK, CLK, D, D 1275 1000*  
1275 1000*  
Input LOW Voltage (Single−Ended)  
(Notes 18 and 19) CLK, CLK, D, D 2600 1400*  
V
V
V
IH  
V
V
V
IH  
V
2600  
V
1400*  
V −  
IH  
150  
IL  
IH  
CC  
IH  
CC  
IH  
CC  
150  
2600 1400*  
150  
Input High Voltage (Single−Ended)  
R, SEL 2090  
IH  
V
CC  
2155  
V
CC  
2215  
V
CC  
Input Low Voltage (Single−Ended)  
R, SEL  
IL  
V
1690  
V
1755  
V
EE  
1815  
EE  
EE  
Input Threshold Voltage  
(Single−Ended) (Note 19)  
V
1125  
+
V
CC  
V
1125  
+
V
CC  
V
1125  
+
V
CC  
THR  
IHCMR  
EE  
EE  
EE  
75  
75  
75  
Input HIGH Voltage Common Mode  
Range (Differential Configuration)  
(Note 16)  
1.2  
3.3  
1.2  
3.3  
1.2  
3.3  
R
TIN  
Internal Input Termination Resistor  
45  
50  
55  
45  
50  
55  
45  
50  
55  
W
I
IH  
Input HIGH Current (@V  
)
R, SEL  
35  
5
100  
50  
35  
5
100  
50  
35  
5
100  
50  
mA  
IH  
CLK, CLK, D, D  
I
IL  
Input LOW Current (@V ) R, SEL  
20  
5
100  
50  
20  
5
100  
50  
20  
5
100  
50  
mA  
IL  
CLK, CLK, D, D  
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit  
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared  
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification  
limit values are applied individually under normal operating conditions and not valid simultaneously.  
14.Input and output parameters vary 1:1 with V . V can vary +0.925 V to −0.165 V.  
CC  
EE  
15.All outputs loaded with 50 W to V − 2.0 V.  
CC  
16.V  
min varies 1:1 with V , V  
max varies 1:1 with V . The V  
range is referenced to the most positive side of the differential  
IHCMR  
EE IHCMR  
CC  
IHCMR  
input signal.  
17.V cannot exceed V . |V − V | < 2600 mV.  
THR  
IH  
CC  
IH  
18.V always w V . |V − V  
| < 2600 mV.  
IL  
EE  
IL  
THR  
19.V  
is the voltage applied to one input when running in single−ended mode.  
THR  
*Typicals used for testing purposes.  
**When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .  
EE  
CC  
EE  
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have  
maximum ambient temperature specification of 85°C.  
http://onsemi.com  
6
 
NBSG53A  
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT  
V
CC  
= 0 V; V = −3.465 V to −2.375 V (Note 20)  
EE  
−40°C  
Typ  
25°C  
Typ  
47  
70°C(BGA)/85°C(QFN)***  
Min  
35  
Max  
59  
Min  
35  
Max  
59  
Min  
35  
Typ  
47  
Max  
59  
Symbol  
Characteristic  
Unit  
mA  
mV  
mV  
I
EE  
Negative Power Supply Current  
Output HIGH Voltage (Note 21)  
Output LOW Voltage (Note 21)  
47  
V
OH  
V
OL  
−1040  
−990  
−940  
−1010  
−960  
−910  
−985  
−935  
−885  
−3.465 V v V v −3.0 V  
EE  
(OLS = V  
)
−1980 −1830 −1680 −1940 −1790 −1640 −1910 −1760 −1610  
−1090  
(OLS = V − 0.8 V, OLS =FLOAT) −1750 −1630 −1510 −1715 −1595 −1475 −1685 −1565 −1445  
CC  
(OLS = V − 0.4 V) −1270 −1210 −1150 −1235 −1175 −1115 −1210 −1150  
CC  
CC  
(OLS = V − 1.2 V) −1040  
−990  
−940  
−1010  
−960  
−910  
−985  
−935  
−885  
CC  
**(OLS = V  
)
−1515 −1425 −1335 −1480 −1390 −1300 −1450 −1360 −1270  
EE  
−3.0 V < V v −2.375 V  
EE  
(OLS = V  
)
−1945 −1795 −1645 −1905 −1755 −1605 −1875 −1725 −1575  
CC  
(OLS = V − 0.4 V) −1265 −1205 −1145 −1230 −1170 −1110 −1205 −1145  
−1085  
CC  
(OLS = V − 0.8 V, OLS =FLOAT) −1725 −1605 −1485 −1690 −1570 −1450 −1660 −1540 −1420  
CC  
(OLS = V − 1.2 V) −1045  
−995  
−945  
−1010  
−960  
−910  
−990  
−940  
−890  
CC  
(OLS = V  
)
−1495 −1405 −1315 −1460 −1370 −1280 −1435 −1345 −1255  
EE  
V
Output Voltage Amplitude  
mV  
OUTPP  
−3.465 V v V v −3.0 V  
EE  
(OLS = V  
)
750  
130  
550  
0
840  
220  
640  
0
740  
125  
545  
0
830  
215  
635  
0
735  
125  
540  
0
825  
215  
630  
0
CC  
(OLS = V − 0.4 V)  
CC  
(OLS = V − 0.8 V, OLS = FLOAT)  
CC  
(OLS = V − 1.2 V)  
CC  
**(OLS = V  
)
345  
435  
340  
430  
335  
425  
EE  
−3.0 V < V v −2.375 V  
EE  
(OLS = V  
)
715  
125  
525  
0
805  
215  
615  
5
705  
120  
520  
0
795  
210  
610  
0
700  
120  
515  
0
790  
210  
605  
5
CC  
(OLS = V − 0.4 V)  
CC  
(OLS = V − 0.8 V, OLS =FLOAT)  
CC  
(OLS = V − 1.2 V)  
CC  
(OLS = V  
)
325  
415  
320  
410  
320  
410  
EE  
V
V
V
Input HIGH Voltage (Single−Ended)  
(Notes 23 and 25) CLK, CLK, D, D  
V
1275  
+
V
1000*  
V
V
1275  
+
V
1000*  
V
V
1275  
+
V
1000*  
V
CC  
mV  
mV  
mV  
IH  
EE  
CC  
CC  
EE  
CC  
CC  
EE  
CC  
Input LOW Voltage (Single−Ended)  
(Notes 24 and 25) CLK, CLK, D, D  
V
2600  
V
1400*  
V
IH  
V
2600  
V
1400*  
V
IH  
V
2600  
V
1400*  
V −  
IH  
150  
IL  
IH  
CC  
IH  
CC  
IH  
CC  
150  
150  
Input High Voltage  
(Single−Ended)  
IH  
R, SEL −1210  
V
CC  
1145  
V
CC  
−1085  
V
CC  
V
V
Input Low Voltage (Single−Ended)  
mV  
mV  
IL  
R, SEL  
V
−1610  
V
−1545  
V
EE  
−1485  
EE  
EE  
Input Threshold Voltage  
(Single−Ended) (Note 25)  
V
EE  
+
V
CC  
V
EE  
+
V
CC  
V
EE  
+
V
CC  
THR  
1125  
75  
1125  
75  
1125  
75  
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit  
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared  
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification  
limit values are applied individually under normal operating conditions and not valid simultaneously.  
20.Input and output parameters vary 1:1 with V  
.
CC  
21.All outputs loaded with 50 W to V − 2.0 V.  
CC  
22.V  
min varies 1:1 with V , V  
max varies 1:1 with V . The V  
range is referenced to the most positive side of the differential  
IHCMR  
EE IHCMR  
CC  
IHCMR  
input signal.  
23.V cannot exceed V . |V − V | < 2600 mV.  
THR  
IH  
CC  
IH  
24.V always w V . |V − V  
| < 2600 mV.  
IL  
EE  
IL  
THR  
25.V  
is the voltage applied to one input when running in single−ended mode.  
THR  
*Typicals used for testing purposes.  
**When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .  
EE  
CC  
EE  
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have  
maximum ambient temperature specification of 85°C.  
http://onsemi.com  
7
 
NBSG53A  
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT  
V
CC  
= 0 V; V = −3.465 V to −2.375 V (Note 20) (continued)  
EE  
−40°C  
Typ  
+ 1.2  
25°C  
70°C(BGA)/85°C(QFN)***  
Min  
Max  
Min  
Typ  
Max  
Min  
Typ  
+ 1.2  
EE  
Max  
Symbol  
Characteristic  
Unit  
V
Input HIGH Voltage Common  
Mode Range  
V
EE  
0.0  
V
EE  
+ 1.2  
0.0  
V
0.0  
V
IHCMR  
(Differential Configuration)  
(Note 22)  
R
TIN  
Internal Input Termination Resistor  
45  
50  
55  
45  
50  
55  
45  
50  
55  
W
I
I
I
Input HIGH Current (@V  
)
mA  
IH  
IH  
R, SEL  
CLK, CLK, D, D  
35  
5
100  
50  
35  
5
100  
50  
35  
5
100  
50  
Input LOW Current (@V )  
mA  
mA  
IL  
IL  
R, SEL  
20  
5
100  
50  
20  
5
100  
50  
20  
5
100  
50  
CLK, CLK, D, D  
OLS Input Current (See Figure  
12)  
OLS  
300  
100  
5
900  
300  
100  
300  
100  
5
900  
300  
100  
300  
100  
5
900  
300  
100  
(OLS = V  
)
CC  
(OLS = V − 0.4 V)  
CC  
(OLS = V − 0.8 V, OLS =  
FLOAT)  
−300  
−100  
−300  
−1500  
−1000  
−100  
−300  
−1500  
−1000  
−100  
CC  
(OLS = V − 1.2 V) −1500  
−600  
−400  
−600  
−400  
−600  
−400  
CC  
−3.465 V v V v −3.0 V  
EE  
*(OLS = V  
)
)
−1000  
EE  
−3.0 V < V v −2.375 V  
EE  
(OLS = V  
EE  
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit  
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared  
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification  
limit values are applied individually under normal operating conditions and not valid simultaneously.  
20.Input and output parameters vary 1:1 with V  
.
CC  
21.All outputs loaded with 50 W to V − 2.0 V.  
CC  
22.V  
min varies 1:1 with V , V  
max varies 1:1 with V . The V  
range is referenced to the most positive side of the differential  
IHCMR  
EE IHCMR  
CC  
IHCMR  
input signal.  
23.V cannot exceed V . |V − V | < 2600 mV.  
THR  
IH  
CC  
IH  
24.V always w V . |V − V  
| < 2600 mV.  
IL  
EE  
IL  
THR  
25.V  
is the voltage applied to one input when running in single−ended mode.  
THR  
*Typicals used for testing purposes.  
**When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .  
EE  
CC  
EE  
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have  
maximum ambient temperature specification of 85°C.  
http://onsemi.com  
8
 
NBSG53A  
Table 10. AC CHARACTERISTICS for FCBGA−16  
V
CC  
= 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V  
EE CC EE  
−40°C  
25°C  
70°C  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Symbol  
Characteristic  
Unit  
f
Maximum Frequency  
GHz  
max  
(See Figures 4, 6, 8, 10, and 11)  
(See Figures 5, 7, 9, 10, and 11)  
(Note 26)  
DFF  
8
8
8
DIV/2  
10  
10  
10  
Propagation Delay to Output Differential  
t
t
,
ps  
PLH  
PHL  
CLKQ, Q  
(OLS = V  
)
160  
210  
200  
205  
205  
260  
250  
255  
255  
160  
155  
160  
160  
215  
205  
210  
210  
270  
255  
260  
260  
165  
160  
160  
160  
220  
210  
215  
215  
275  
260  
270  
270  
CC  
(OLS = V − 0.4 V) 150  
CC  
(OLS = V − 0.8 V, OLS = FLOAT) 155  
CC  
**(OLS = V  
)
155  
EE  
SELQ, Q  
(OLS = V  
)
165  
220  
210  
215  
210  
275  
260  
270  
260  
170  
160  
165  
160  
225  
210  
220  
215  
280  
260  
275  
270  
170  
160  
165  
165  
225  
210  
220  
220  
280  
260  
275  
275  
CC  
(OLS = V − 0.4 V) 160  
CC  
(OLS = V − 0.8 V, OLS = FLOAT) 160  
CC  
**(OLS = V  
)
160  
EE  
RQ, Q  
(OLS = V ) DIV/2 220  
295  
270  
285  
260  
290  
265  
285  
260  
370  
340  
355  
325  
360  
330  
355  
325  
225  
205  
220  
200  
220  
200  
220  
200  
300  
275  
290  
265  
295  
270  
290  
265  
375  
345  
360  
330  
370  
340  
360  
330  
225  
205  
220  
200  
220  
200  
220  
200  
300  
275  
290  
265  
295  
270  
290  
265  
375  
345  
360  
330  
370  
340  
360  
330  
CC  
(OLS = V ) DFF 200  
CC  
(OLS = V − 0.4 V) DIV/2 215  
CC  
(OLS = V − 0.4 V) DFF 195  
CC  
(OLS = V −0.8 V, OLS = FLOAT) DIV/2  
220  
CC  
CC  
(OLS = V − 0.8 V, OLS = FLOAT) DFF 200  
**(OLS = V ) DIV/2 215  
EE  
**(OLS = V ) DFF 195  
EE  
t
t
Duty Cycle Skew (Notes 27 and 29) DFF  
RMS Random Clock Jitter  
5
20  
5
20  
5
20  
ps  
ps  
SKEW  
JITTER  
f
in  
v 8 GHz  
0.5  
1.5  
0.5  
1.5  
0.5  
1.5  
(See Figures 4 and 6) (Note 26)  
Peak−to−Peak Data Dependent Jitter  
= 8 Gb/s  
f
in  
TBD  
V
Input Voltage Swing/Sensitivity  
(Differential Configuration) (Note 28)  
75  
2600  
75  
2600  
75  
2600  
mV  
ps  
INPP  
t
r
t
f
Output Rise/Fall Times (20% − 80%)  
@ 1 GHz  
Q, Q  
(OLS = V  
)
30  
20  
25  
25  
50  
40  
45  
45  
65  
60  
65  
65  
30  
20  
25  
25  
50  
40  
45  
45  
65  
60  
65  
65  
30  
20  
25  
25  
50  
40  
45  
45  
65  
60  
65  
65  
CC  
(OLS = V − 0.4 V)  
CC  
(OLS = V − 0.8 V, OLS = FLOAT)  
CC  
**(OLS = V  
)
EE  
t
t
t
Setup Time  
Hold Time  
DCLK  
DCLK  
30  
25  
40  
14  
12  
9
30  
25  
40  
10  
7
30  
25  
40  
13  
9
ps  
ps  
ps  
s
h
Reset Recovery  
DFF, DIV/2  
12  
10  
rr  
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit  
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared  
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit  
values are applied individually under normal operating conditions and not valid simultaneously.  
26.Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to  
V
CC  
− 2.0 V. Input edge rates is 40 ps (20% − 80%).  
27.See Figure 14. t  
= |t  
− t  
PHL  
| for a nominal 50% differential clock input waveform.  
SKEW  
PLH  
28.V  
(MAX) cannot exceed V − V (Applicable only when V − V < 2600 mV).  
INPP  
CC EE CC EE  
29.See Figure 10. Duty Cycle % vs. Frequency.  
**When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .  
EE  
CC  
EE  
http://onsemi.com  
9
 
NBSG53A  
Table 11. AC CHARACTERISTICS for QFN−16  
V
CC  
= 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V  
EE CC EE  
−40°C  
25°C  
85°C  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Symbol  
Characteristic  
Unit  
f
Maximum Frequency  
GHz  
max  
(See Figures 4, 6, 8, 10, and 11)  
(See Figures 5, 7, 9, 10, and 11)  
(Note 30)  
DFF  
DIV/2  
8
8
8
10  
10  
10  
t
t
,
Propagation Delay to Output Differential  
ps  
PLH  
PHL  
(Note 34)  
CLKQ, Q  
SELQ, Q  
150  
160  
215  
195  
215  
190  
280  
270  
285  
280  
375  
345  
150  
160  
215  
195  
215  
190  
280  
270  
285  
280  
375  
345  
150  
160  
215  
195  
215  
190  
280  
270  
285  
280  
375  
345  
RQ, Q D /2  
IN  
DFF  
t
t
Duty Cycle Skew (Notes 31 and 33) DFF  
RMS Random Clock Jitter  
5
20  
5
20  
5
20  
ps  
ps  
SKEW  
JITTER  
f
in  
v 8 GHz  
0.5  
1
0.5  
1
0.5  
1
(See Figures 4 and 6) (Note 30)  
Peak−to−Peak Data Dependent Jitter  
= 8 Gb/s  
f
in  
TBD  
TBD  
TBD  
V
Input Voltage Swing/Sensitivity  
(Differential Configuration) (Note 32)  
75  
2600  
75  
2600  
75  
2600  
mV  
ps  
INPP  
t
r
t
f
Output Rise/Fall Times (20% − 80%)  
@ 1 GHz  
Q, Q  
(OLS = V  
)
28  
15  
25  
20  
40  
40  
35  
35  
65  
65  
65  
65  
28  
15  
25  
20  
40  
40  
35  
35  
65  
65  
65  
65  
28  
15  
25  
20  
40  
40  
35  
35  
65  
65  
65  
65  
CC  
(OLS = V − 0.4 V)  
CC  
(OLS = V − 0.8 V, OLS = FLOAT)  
CC  
**(OLS = V  
)
EE  
t
t
t
Setup Time  
Hold Time  
DCLK  
DCLK  
30  
25  
40  
14  
12  
9
30  
25  
40  
10  
7
30  
25  
40  
13  
0
ps  
ps  
ps  
s
h
Reset Recovery  
DFF, DIV/2  
12  
10  
rr  
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit  
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared  
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit  
values are applied individually under normal operating conditions and not valid simultaneously.  
30.Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to  
V
CC  
− 2.0 V. Input edge rates is 40 ps (20% − 80%).  
31.See Figure 14. t  
= |t  
− t  
PHL  
| for a nominal 50% differential clock input waveform.  
SKEW  
PLH  
32.V  
(MAX) cannot exceed V − V (Applicable only when V − V < 2600 mV).  
INPP  
CC EE CC EE  
33.See Figure 10. Duty Cycle % vs. Frequency.  
34.For all OLS Configuration.  
**When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .  
EE  
CC  
EE  
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have  
maximum ambient temperature specification of 85°C.  
http://onsemi.com  
10  
 
NBSG53A  
900  
800  
700  
600  
500  
400  
300  
200  
100  
9
8
7
6
5
4
3
2
1
OLS = V  
CC  
OLS = V − 0.8 V, OLS = FLOAT  
CC  
*OLS = V  
EE  
OLS = V − 0.4 V  
CC  
RMS JITTER  
0
0
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.  
Input Frequency (fin) for DFF Mode (VCC − VEE = 3.3 V @ 255C; Repetitive 1010 Input Data Pattern)  
900  
OLS = V  
CC  
800  
700  
600  
500  
400  
300  
200  
100  
OLS = V − 0.8 V, OLS = FLOAT  
CC  
*OLS = V  
EE  
OLS = V − 0.4 V  
CC  
0
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.  
Input Frequency (fin) for DIV/2 Mode (VCC − VEE = 3.3 V @ 255C)  
*When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .  
EE  
CC  
EE  
http://onsemi.com  
11  
NBSG53A  
900  
800  
700  
600  
500  
400  
300  
200  
100  
9
8
7
6
5
4
3
2
1
OLS = V  
CC  
OLS = V − 0.8 V, OLS = FLOAT  
CC  
*OLS = V  
EE  
OLS = V − 0.4 V  
CC  
RMS JITTER  
0
0
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 6. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.  
Input Frequency (fin) for DFF Mode (VCC − VEE = 2.5 V @ 255C; Repetitive 1010 Input Data Pattern)  
900  
OLS = V  
CC  
800  
700  
600  
500  
400  
300  
200  
100  
*OLS = V − 0.8 V, OLS = FLOAT  
CC  
OLS = V  
EE  
OLS = V − 0.4 V  
CC  
0
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 7. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.  
Input Frequency (fin) for DIV/2 Mode (VCC − VEE = 2.5 V @ 255C)  
*When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .  
EE  
CC  
EE  
http://onsemi.com  
12  
NBSG53A  
1200  
1100  
V
OH  
(Q)  
1000  
900  
V
OH  
(Q)  
800  
700  
600  
500  
400  
300  
200  
100  
0
V
(Q)  
OL  
V
(Q)  
7
OL  
0
1
2
3
4
5
6
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 8. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DFF Mode  
(VCC − VEE = 3.3 V @ 255C and OLS = VCC − 0.8 V, OLS = FLOAT)  
1200  
1100  
V
(Q)  
(Q)  
OH  
1000  
900  
V
OH  
800  
700  
600  
500  
400  
300  
200  
100  
0
V
(Q)  
OL  
V
OL  
(Q)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 9. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DIV/2 Mode  
(VCC − VEE = 3.3 V @ 255C and OLS = VCC − 0.8 V, OLS = FLOAT)  
http://onsemi.com  
13  
NBSG53A  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
DIV/2 Mode  
DFF Mode  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 10. Duty Cycle % vs. Input Frequency (fin)  
(VCC − VEE = 3.3 V @ 255C)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
DIV/2 Mode  
DFF Mode  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
INPUT FREQUENCY (GHz)  
Figure 11. Duty Cycle % vs. Input Frequency (fin)  
(VCC − VEE = 2.5 V @ 705C)  
http://onsemi.com  
14  
NBSG53A  
300  
200  
100  
0
−100  
−200  
−300  
−400  
−500  
−600  
−700  
V
CC  
V
CC  
− 400  
V
CC  
− 800  
V
CC  
− 1200  
V
EE  
V
OLS  
(mV)  
Figure 12. Typical OLS Input Current vs. OLS Input Voltage  
(VCC − VEE = 3.3 V @ 255C)  
1000  
800  
V
CC  
− 75  
V
CC  
− 700  
V
CC  
− 900  
600  
400  
200  
0
V
+ 100  
EE  
V
CC  
− 250  
V
CC  
− 550  
V
CC  
− 1125  
V
CC  
− 1275  
V
CC  
V
CC  
− 400  
V
CC  
− 800  
V
CC  
− 1200  
V
EE  
OLS (mV)  
Figure 13. OLS Operating Area  
http://onsemi.com  
15  
NBSG53A  
CLK  
V
V
= V (CLK) − V (CLK)  
IH IL  
INPP  
CLK  
Q
= V (Q) − V (Q)  
OUTPP  
OH  
OL  
Q
t
PHL  
t
PLH  
Figure 14. AC Reference Measurement  
Z = 50 W  
Q
Q
D
D
o
Receiver  
Device  
Driver  
Device  
Z = 50 W  
o
50 W  
50 W  
V
TT  
V
TT  
= V − 2.0 V  
CC  
Figure 15. Typical Termination for Output Driver and Device Evaluation  
(Refer to Application Note AND8020/D − Termination of ECL Logic Devices)  
ORDERING INFORMATION  
Device  
Package Type  
Shipping  
NBSG53ABA  
4x4 mm  
FCBGA−16  
100 Units / Tray  
500 / Tape & Reel  
123 Units / Rail  
NBSG53ABAR2  
NBSG53AMN  
NBSG53AMNR2  
4x4 mm  
FCBGA−16  
3x3 mm  
QFN−16  
3x3 mm  
QFN−16  
3000 / Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifi-  
cations Brochure, BRD8011/D.  
http://onsemi.com  
16  
NBSG53A  
PACKAGE DIMENSIONS  
FCBGA−16  
BA SUFFIX  
PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE  
CASE 489−01  
ISSUE O  
LASER MARK FOR PIN 1  
IDENTIFICATION IN  
THIS AREA  
−X−  
D
NOTES:  
1. DIMENSIONS ARE IN MILLIMETERS.  
2. INTERPRET DIMENSIONS AND TOLERANCES  
PER ASME Y14.5M, 1994.  
3. DIMENSION b IS MEASURED AT THE MAXIMUM  
SOLDER BALL DIAMETER, PARALLEL TO DATUM  
PLANE Z.  
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE  
SPHERICAL CROWNS OF THE SOLDER BALLS.  
5. PARALLELISM MEASUREMENT SHALL EXCLUDE  
ANY EFFECT OF MARK ON TOP SURFACE OF  
PACKAGE.  
M
−Y−  
E
K
M
MILLIMETERS  
0.20  
DIM MIN  
MAX  
FEDUCIAL FOR PIN A1  
IDENTIFICATION IN THIS AREA  
A
A1  
A2  
b
1.40 MAX  
0.25  
0.35  
3 X e  
4
3
2
1
1.20 REF  
0.30  
0.50  
A
D
4.00 BSC  
3
B
E
4.00 BSC  
1.00 BSC  
0.50 BSC  
e
16 X  
b
C
D
S
M
M
0.15  
0.08  
Z X  
Z
Y
S
VIEW M−M  
5
0.15  
Z
A2  
A
−Z−  
16 X  
A1  
0.10  
Z
4
DETAIL K  
ROTATED 90 CLOCKWISE  
_
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17  
NBSG53A  
PACKAGE DIMENSIONS  
QFN−16  
MN SUFFIX  
CASE 485G−01  
ISSUE O  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
−X−  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION D APPLIES TO PLATED TERMINAL  
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM  
FROM TERMINAL.  
4. COPLANARITY APPLIES TO THE EXPOSED PAD  
AS WELL AS THE TERMINALS.  
A
M
−Y−  
MILLIMETERS  
DIM MIN MAX  
3.00 BSC  
3.00 BSC  
0.80  
INCHES  
MIN MAX  
A
B
C
D
E
F
0.118 BSC  
0.118 BSC  
B
1.00 0.031  
0.039  
0.011  
0.073  
0.073  
0.23  
1.75  
1.75  
0.28 0.009  
1.85 0.069  
1.85 0.069  
N
G
H
J
0.50 BSC  
0.875 0.925  
0.20 REF  
0.020 BSC  
0.034  
0.036  
0.25 (0.010) T  
0.25 (0.010) T  
0.008 REF  
K
L
0.00  
0.35  
0.05 0.000  
0.45 0.014  
0.002  
0.018  
M
N
P
R
1.50 BSC  
1.50 BSC  
0.875 0.925  
0.60 0.80 0.024  
0.059 BSC  
0.059 BSC  
0.034  
0.036  
0.031  
J
R
C
SEATING  
PLANE  
−T−  
0.08 (0.003) T  
K
E
H
G
L
5
8
4
9
F
12  
1
16  
13  
P
D NOTE 3  
M
0.10 (0.004)  
T
X Y  
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make  
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any  
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all  
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be  
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.  
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death  
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC  
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees  
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  
PUBLICATION ORDERING INFORMATION  
Literature Fulfillment:  
JAPAN: ON Semiconductor, Japan Customer Focus Center  
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051  
Phone: 81−3−5773−3850  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: ONlit@hibbertco.com  
ON Semiconductor Website: http://onsemi.com  
For additional information, please contact your local  
Sales Representative.  
N. American Technical Support: 800−282−9855 Toll Free USA/Canada  
NBSG53A/D  
配单直通车
NBSG53AMNR2产品参数
型号:NBSG53AMNR2
是否无铅:不含铅
生命周期:Active
IHS 制造商:ROCHESTER ELECTRONICS LLC
零件包装代码:QFN
包装说明:3 X 3 MM, QFN-16
针数:16
Reach Compliance Code:unknown
风险等级:5.69
Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.465V
系列:53
输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N16
JESD-609代码:e0
长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:NOT SPECIFIED
功能数量:1
反相输出次数:
端子数量:16
实输出次数:1
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:UNSPECIFIED
封装代码:HVQCCN
封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):240
传播延迟(tpd):0.285 ns
认证状态:COMMERCIAL
座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:TIN LEAD
端子形式:NO LEAD
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:30
宽度:3 mm
Base Number Matches:1
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