NCP1200P60G应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

NCP1200

PWM Current−Mode

Controller for Low−Power

Universal Off−Line Supplies

Housed in SOIC−8 or PDIP−8 package, the NCP1200 represents a

major leap toward ultra−compact Switchmode Power Supplies. Due to

a novel concept, the circuit allows the implementation of a complete

offline battery charger or a standby SMPS with few external

components. Furthermore, an integrated output short−circuit

protection lets the designer build an extremely low−cost AC−DC wall

adapter associated with a simplified feedback scheme.

With an internal structure operating at a fixed 40 kHz, 60 kHz or

100 kHz, the controller drives low gate−charge switching devices like

an IGBT or a MOSFET thus requiring a very small operating power.

Due to current−mode control, the NCP1200 drastically simplifies the

design of reliable and cheap offline converters with extremely low

acoustic generation and inherent pulse−by−pulse control.

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MARKING

DIAGRAMS

8

SOIC−8

D SUFFIX

CASE 751

200Dy

ALYW

8

1

8

PDIP−8

P SUFFIX

CASE 626

1200Pxxx

AWL

YYWW

When the current setpoint falls below a given value, e.g. the output

power demand diminishes, the IC automatically enters the skip cycle

mode and provides excellent efficiency at light loads. Because this

occurs at low peak current, no acoustic noise takes place.

1

xxx

y

= Device Code: 40, 60 or 100

= Device Code:

4 for 40

Finally, the IC is self−supplied from the DC rail, eliminating the

need of an auxiliary winding. This feature ensures operation in

presence of low output voltage or shorts.

6 for 60

1 for 100

A

L

= Assembly Location

= Wafer Lot

Features

• No Auxiliary Winding Operation

Y, YY = Year

W, WW = Work Week

• Internal Output Short−Circuit Protection

• Extremely Low No−Load Standby Power

• Current−Mode with Skip−Cycle Capability

• Internal Leading Edge Blanking

• 250 mA Peak Current Source/Sink Capability

• Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz

• Direct Optocoupler Connection

• Built−in Frequency Jittering for Lower EMI

• SPICE Models Available for TRANsient and AC Analysis

• Internal Temperature Shutdown

PIN CONNECTIONS

Adj

FB

1

2

3

4

8

7

6

5

HV

NC

V

CS

CC

GND

Drv

(Top View)

• Pb−Free Packages are Available

ORDERING INFORMATION

Typical Applications

See detailed ordering and shipping information in the package

dimensions section on page 14 of this data sheet.

• AC−DC Adapters

• Offline Battery Chargers

• Auxiliary/Ancillary Power Supplies (USB, Appliances, TVs, etc.)

Semiconductor Components Industries, LLC, 2004

1

Publication Order Number:

December, 2004 − Rev. 13

NCP1200/D

NCP1200

*

6.5 V @ 600 mA

C2

470 mF/10 V

C3

10 mF

400 V

+

D2

1N5819

HV

NC

1

2

3

4

8

7

6

5

Adj

FB

CS

V

CC

M1

MTD1N60E

Rf

GND Drv

470

EMI

Filter

+

C5

R

sense

10 mF

D8

5 V1

Universal Input

*Please refer to the application information section

Figure 1. Typical Application

PIN FUNCTION DESCRIPTION

Pin No. Pin Name

Function

Description

1

2

3

Adj

FB

CS

Adjust the Skipping Peak Current

This pin lets you adjust the level at which the cycle skipping process takes

place.

Sets the Peak Current Setpoint

Current Sense Input

By connecting an Optocoupler to this pin, the peak current setpoint is ad-

justed accordingly to the output power demand.

This pin senses the primary current and routes it to the internal comparator

via an L.E.B.

4

5

6

7

8

GND

Drv

The IC Ground

Driving Pulses

Supplies the IC

No Connection

The driver’s output to an external MOSFET.

V

CC

This pin is connected to an external bulk capacitor of typically 10 mF.

This un−connected pin ensures adequate creepage distance.

Connected to the high−voltage rail, this pin injects a constant current into

NC

HV

Generates the V from the Line

CC

the V bulk capacitor.

CC

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2

NCP1200

8

7

6

5

1

2

3

4

Adj

FB

HV

NC

HV Current

Source

Skip Cycle

Comparator

75.5 k

1.4 V

+

UVLO

Internal

−

High and Low

Internal Regulator

V

CC

29 k

Q Flip−Flop

DCmax = 80%

Set

40, 60 or

100 kHz

Clock

Q

Current

Sense

250 ns

L.E.B.

V

CC

Reset

+

−

8 k

60 k

Ground

Drv

+

−

V

5.2 V

1 V

ref

±110 mA

20 k

Overload?

Fault Duration

Figure 2. Internal Circuit Architecture

MAXIMUM RATINGS

Rating

Symbol

Value

Units

V

Power Supply Voltage

V

R

16

CC

Thermal Resistance Junction−to−Air, PDIP−8 version

Thermal Resistance Junction−to−Air, SOIC version

100

178

°C/W

q

JA

R

Maximum Junction Temperature

Typical Temperature Shutdown

T

150

140

°C

Jmax

−

Storage Temperature Range

T

−60 to +150

°C

kV

V

stg

ESD Capability, HBM Model (All Pins except V and HV)

−

2.0

200

450

500

30

CC

ESD Capability, Machine Model

Maximum Voltage on Pin 8 (HV), pin 6 (V ) Grounded

V

CC

Maximum Voltage on Pin 8 (HV), Pin 6 (V ) Decoupled to Ground with 10 mF

V

CC

Minimum Operating Voltage on Pin 8 (HV)

V

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

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3

NCP1200

ELECTRICAL CHARACTERISTICS (For typical values T = +25°C, for min/max values T = −25°C to +125°C, Max T = 150°C,

J

V

CC

= 11 V unless otherwise noted)

Rating

DYNAMIC SELF−SUPPLY (All Frequency Versions, Otherwise Noted)

Symbol

Min

Typ

Max

Unit

V

Increasing Level at Which the Current Source Turns−off

Decreasing Level at Which the Current Source Turns−on

Decreasing Level at Which the Latchoff Phase Ends

6

V

10.3

8.8

−

11.4

9.8

12.5

11

V

CC

CCOFF

V

CCON

V

6.3

−

V

CClatch

Internal IC Consumption, No Output Load on Pin 5

Internal IC Consumption, 1 nF Output Load on Pin 5, F

I

−

710

880

mA

CC1

CC2

CC3

Note 1

= 40 kHz

= 60 kHz

= 100 kHz

6

−

1.2

1.4

1.9

350

1.4

mA

SW

Note 2

1.6

Note 2

2.2

Note 2

Internal IC Consumption, Latchoff Phase

−

INTERNAL CURRENT SOURCE

High−voltage Current Source, V = 10 V

8

I

2.8

−

4.0

4.9

−

mA

CC

C1

High−voltage Current Source, V = 0 V

CC

C2

DRIVE OUTPUT

Output Voltage Rise−time @ CL = 1 nF, 10−90% of Output Signal

Output Voltage Fall−time @ CL = 1 nF, 10−90% of Output Signal

5

T

−

67

28

40

12

−

ns

W

r

T

f

Source Resistance (drive = 0, Vgate = V

− 1 V)

R

27

5

61

25

CCHMAX

OH

Sink Resistance (drive = 11 V, Vgate = 1 V)

CURRENT COMPARATOR (Pin 5 Un−loaded)

Input Bias Current @ 1 V Input Level on Pin 3

Maximum internal Current Setpoint

R

W

OL

IB

3

I

−

0.8

−

0.02

0.9

−

1.0

−

mA

V

I

Limit

Default Internal Current Setpoint for Skip Cycle Operation

Propagation Delay from Current Detection to Gate OFF State

Leading Edge Blanking Duration

I

350

100

230

mV

ns

Lskip

T

−

160

−

DEL

LEB

T

−

INTERNAL OSCILLATOR (V = 11 V, Pin 5 Loaded by 1 kW)

CC

Oscillation Frequency, 40 kHz Version

Oscillation Frequency, 60 kHz Version

Oscillation Frequency, 100 kHz Version

−

f

36

52

86

−

42

61

48

70

116

−

kHz

Hz/V

%

OSC

103

300

450

620

80

Built−in Frequency Jittering, F

Maximum Duty Cycle

= 40 kHz

= 60 kHz

= 100 kHz

f

SW

jitter

f

−

f

−

Dmax

74

87

FEEDBACK SECTION (V = 11 V, Pin 5 Loaded by 1 kW)

CC

Internal Pullup Resistor

2

−

Rup

−

8.0

4.0

−

kW

Pin 3 to Current Setpoint Division Ratio

SKIP CYCLE GENERATION

Default skip mode level

Iratio

−

1

Vskip

Zout

1.1

−

1.4

25

1.6

−

V

Pin 1 internal output impedance

kW

1. Max value @ T = −25°C.

J

2. Max value @ T = 25°C, please see characterization curves.

J

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4

NCP1200

60

50

40

30

20

10

0

11.70

11.60

11.50

11.40

11.30

11.20

11.10

100 kHz

60 kHz

40 kHz

−25

0

25

50

75

100

125

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 3. HV Pin Leakage Current vs.

Temperature

Figure 4. V_CCOFF vs. Temperature

9.85

9.80

9.75

9.70

9.65

9.60

9.55

9.50

9.45

900

850

800

750

100 kHz

60 kHz

100 kHz

40 kHz

700

650

600

60 kHz

40 kHz

50

−25

0

25

50

75

100

−25

0

25

75

100

TEMPERATURE (°C)

Figure 5. V_CCON vs. Temperature

Figure 6. I_CC1vs. Temperature

2.10

1.90

110

104

100 kHz

98

92

86

80

74

68

62

56

50

44

38

1.70

1.50

1.30

1.10

60 kHz

40 kHz

60 kHz

40 kHz

0.90

−25

0

25

50

75

100

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 7. I_CC2vs. Temperature

Figure 8. Switching Frequency vs. T_J

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5

NCP1200

6.50

6.45

6.40

6.35

6.30

6.25

6.20

460

430

400

370

340

310

280

250

220

190

−25

0

25

50

75

100

125

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 9. V_CCLatchoff vs. Temperature

Figure 10. I_CC3vs. Temperature

60

50

40

30

20

10

0

1.00

0.96

0.92

0.88

0.84

Source

Sink

0.80

−25

0

25

50

75

100

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 11. DRV Source/Sink Resistances

Figure 12. Current Sense Limit vs. Temperature

1.34

1.33

86.0

84.0

1.32

1.31

1.30

1.29

82.0

80.0

78.0

76.0

74.0

1.28

−25

0

25

50

75

100

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 13. V_skipvs. Temperature

Figure 14. Max Duty Cycle vs. Temperature

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6

NCP1200

APPLICATIONS INFORMATION

INTRODUCTION

Dynamic Self−Supply

The NCP1200 implements a standard current mode

architecture where the switch−off time is dictated by the

peak current setpoint. This component represents the ideal

candidate where low part−count is the key parameter,

particularly in low−cost AC−DC adapters, auxiliary

supplies etc. Due to its high−performance High−Voltage

technology, the NCP1200 incorporates all the necessary

components normally needed in UC384X based supplies:

timing components, feedback devices, low−pass filter and

self−supply. This later point emphasizes the fact that ON

Semiconductor’s NCP1200 does NOT need an auxiliary

winding to operate: the product is naturally supplied from

The DSS principle is based on the charge/discharge of the

V

bulk capacitor from a low level up to a higher level. We

CC

can easily describe the current source operation with a bunch

of simple logical equations:

POWER−ON: IF V < V

THEN Current Source

CC

CCOFF

is ON, no output pulses

IF V decreasing > V

OFF, output is pulsing

THEN Current Source is

CC

CCON

IF V increasing < V

CC

CCOFF

ON, output is pulsing

Typical values are: V

= 11.4 V, V

= 9.8 V

CCOFF

CCON

To better understand the operational principle, Figure 15’s

sketch offers the necessary light:

the high−voltage rail and delivers a V to the IC. This

CC

system is called the Dynamic Self−Supply (DSS).

V

= 11.4 V

CCOFF

V

CC

10.6 V Avg.

V

CCON

= 9.8 V

ON

OFF

Current

Source

Output Pulses

50.00M 70.00M

10.00M

30.00M

90.00M

Figure 15. The Charge/Discharge Cycle

Over a 10 mF V_CCCapacitor

The DSS behavior actually depends on the internal IC

consumption and the MOSFET’s gate charge, Qg. If we

select a MOSFET like the MTD1N60E, Qg equals 11 nC

(max). With a maximum switching frequency of 48 kHz (for

the P40 version), the average power necessary to drive the

MOSFET (excluding the driver efficiency and neglecting

various voltage drops) is:

. 0.16 = 256 mW. If for design reasons this contribution is

still too high, several solutions exist to diminish it:

1. Use a MOSFET with lower gate charge Qg

2. Connect pin through a diode (1N4007 typically) to

one of the mains input. The average value on pin 8

2 * V

mains PEAK

becomes

. Our power contribution

p

example drops to: 160 mW.

Fsw @ Qg @ V

with

cc

Fsw = maximum switching frequency

Qg = MOSFET’s gate charge

Dstart

1N4007

V

CC

= V level applied to the gate

GS

To obtain the final driver contribution to the IC

C3

4.7 mF

400 V

+

NCP1200

consumption, simply divide this result by V : Idriver =

CC

HV

NC

1

2

3

4

8

7

6

5

Fsw @ Qg = 530 mA. The total standby power consumption

at no−load will therefore heavily rely on the internal IC

consumption plus the above driving current (altered by the

driver’s efficiency). Suppose that the IC is supplied from a

400 V DC line. To fully supply the integrated circuit, let’s

imagine the 4 mA source is ON during 8 ms and OFF during

50 ms. The IC power contribution is therefore: 400 V . 4 mA

Adj

FB

CS

V

CC

EMI

Filter

GND Drv

Figure 16. A simple diode naturally reduces the

average voltage on pin 8

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7

NCP1200

3. Permanently force the V level above V

with

When FB is above the skip cycle threshold (1.4 V by

CC

CCH

an auxiliary winding. It will automatically

default), the peak current cannot exceed 1 V/Rsense. When

the IC enters the skip cycle mode, the peak current cannot go

below Vpin1 / 4 (Figure 19). The user still has the flexibility

to alter this 1.4 V by either shunting pin 1 to ground through

a resistor or raising it through a resistor up to the desired

level.

disconnect the internal startup source and the IC

will be fully self−supplied from this winding.

Again, the total power drawn from the mains will

significantly decrease. Make sure the auxiliary

voltage never exceeds the 16 V limit.

Skipping Cycle Mode

The NCP1200 automatically skips switching cycles when

the output power demand drops below a given level. This is

accomplished by monitoring the FB pin. In normal

operation, pin 2 imposes a peak current accordingly to the

load value. If the load demand decreases, the internal loop

asks for less peak current. When this setpoint reaches a

determined level, the IC prevents the current from

decreasing further down and starts to blank the output

pulses: the IC enters the so−called skip cycle mode, also

named controlled burst operation. The power transfer now

depends upon the width of the pulse bunches (Figure 18 ).

Suppose we have the following component values:

P1

P2

P3

Figure 18. Output pulses at various power levels

Lp, primary inductance = 1 mH

(X = 5 ms/div) P1<P2<P3

F , switching frequency = 48 kHz

SW

Ip skip = 300 mA (or 350 mV / Rsense)

Max Peak

Current

The theoretical power transfer is therefore:

1

2

@ Lp @ Ip²@ Fsw + 2.2 W

If this IC enters skip cycle mode with a bunch length of

Skip Cycle

Current Limit

10 ms over a recurrent period of 100 ms, then the total power

transfer is: 2.2 . 0.1 = 220 mW.

To better understand how this skip cycle mode takes place,

a look at the operation mode versus the FB level

immediately gives the necessary insight:

FB

4.8 V

3.8 V

Figure 19. The skip cycle takes place at low peak

currents which guarantees noise free operation

Normal Current Mode Operation

1.4 V

Skip Cycle Operation

Ip

min

= 350 mV / R

sense

Figure 17. Feedback Voltage Variations

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8

NCP1200

Power Dissipation

Overload Operation

The NCP1200 is directly supplied from the DC rail

through the internal DSS circuitry. The current flowing

through the DSS is therefore the direct image of the

NCP1200 current consumption. The total power dissipation

can be evaluated using: (V_HVDC* 11 V) @ ICC2. If we

operate the device on a 250 VAC rail, the maximum rectified

voltage can go up to 350 VDC. As a result, the worse case

dissipation occurs on the 100 kHz version which will

dissipate 340 . 1.8 mA@Tj = −25°C = 612 mW (however

this 1.8 mA number will drop at higher operating

In applications where the output current is purposely not

controlled (e.g. wall adapters delivering raw DC level), it is

interesting to implement a true short−circuit protection. A

short−circuit actually forces the output voltage to be at a low

level, preventing a bias current to circulate in the

optocoupler LED. As a result, the FB pin level is pulled up

to 4.1 V, as internally imposed by the IC. The peak current

setpoint goes to the maximum and the supply delivers a

rather high power with all the associated effects. Please note

that this can also happen in case of feedback loss, e.g. a

broken optocoupler. To account for this situation, the

NCP1200 hosts a dedicated overload detection circuitry.

Once activated, this circuitry imposes to deliver pulses in a

burst manner with a low duty cycle. The system recovers

when the fault condition disappears.

temperatures). Please note that in the above example, I

CC2

is based on a 1 nF capacitor loading pin 5. As seen before,

will depend on your MOSFET’s Q : I = I + F

I

CC2

g

CC2

CC1

sw

x Q . Final calculations shall thus account for the total

g

gate−charge Q your MOSFET will exhibit. A DIP8

g

During the startup phase, the peak current is pushed to the

maximum until the output voltage reaches its target and the

feedback loop takes over. This period of time depends on

normal output load conditions and the maximum peak

current allowed by the system. The time−out used by this IC

package offers a junction−to−ambient thermal resistance

of R

100°C/W. The maximum power dissipation can

qJ−A

thus be computed knowing the maximum operating

ambient temperature (e.g. 70°C) together with the

maximum allowable junction temperature (125°C):

T_Jmax* T_Amax

works with the V decoupling capacitor: as soon as the

CC

Pmax +

= 550 mW. As we can see, we do not

V

CC

decreases from the V

level (typically 11.4 V) the

R_RqJ*A

CCOFF

device internally watches for an overload current situation.

If this condition is still present when V is reached, the

controller stops the driving pulses, prevents the self−supply

current source to restart and puts all the circuitry in standby,

reach the worse consumption budget imposed by the 100

kHz version. Two solutions exist to cure this trouble. The

first one consists in adding some copper area around the

CCON

NCP1200 DIP8 footprint. By adding a min−pad area of 80

2

consuming as little as 350 mA typical (I parameter). As

mm of 35 m copper (1 oz.) R

drops to about 75°C/W

CC3

qJ−A

a result, the V level slowly discharges toward 0. When

which allows the use of the 100 kHz version. The other

solutions are:

CC

this level crosses 6.3 V typical, the controller enters a new

startup phase by turning the current source on: V rises

1. Add a series diode with pin 8 (as suggested in the

above lines) to drop the maximum input voltage

down to 222 V ((2 350)/pi) and thus dissipate

less than 400 mW

CC

toward 11.4 V and again delivers output pulses at the

UVLO crossing point. If the fault condition has been

H

removed before UVLO approaches, then the IC continues

L

its normal operation. Otherwise, a new fault cycle takes

place. Figure 20 shows the evolution of the signals in

presence of a fault.

2. Implement a self−supply through an auxiliary

winding to permanently disconnect the self−supply.

SOIC−8 package offers a worse R

compared to that of

qJ−A

the DIP8 package: 178°C/W. Again, adding some copper

area around the PCB footprint will help decrease this

number: 12 mm x 12 mm to drop R

down to 100°C/W

qJ−A

with 35 m copper thickness (1 oz.) or 6.5 mm x 6.5 mm with

70 m copper thickness (2 oz.). One can see, we do not

recommend using the SOIC package for the 100 kHz version

with DSS active as the IC may not be able to sustain the

power (except if you have the adequate place on your PCB).

However, using the solution of the series diode or the

self−supply through the auxiliary winding does not cause

any problem with this frequency version. These options are

thoroughly described in the AND8023/D.

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9

NCP1200

V

CC

Regulation

Occurs Here

11.4 V

Latchoff

Phase

9.8 V

6.3 V

Time

Drv

Driver

Pulses

Time

Internal

Fault

Flag

Fault is

Relaxed

Startup Phase

Fault Occurs Here

Figure 20. If the fault is relaxed during the V_CCnatural fall down sequence, the IC automatically resumes.

If the fault persists when V_CCreached UVLO_L, then the controller cuts everything off until recovery.

Calculating the V Capacitor

As the above section describes, the fall down sequence

Protecting the Controller Against Negative Spikes

As with any controller built upon a CMOS technology, it

is the designer’s duty to avoid the presence of negative

spikes on sensitive pins. Negative signals have the bad habit

to forward bias the controller substrate and induce erratic

behaviors. Sometimes, the injection can be so strong that

internal parasitic SCRs are triggered, engendering

irremediable damages to the IC if they are a low impedance

CC

depends upon the V level: how long does it take for the

CC

V

CC

line to go from 11.4 V to 9.8 V? The required time

depends on the startup sequence of your system, i.e. when

you first apply the power to the IC. The corresponding

transient fault duration due to the output capacitor charging

must be less than the time needed to discharge from 11.4 V

to 9.8 V, otherwise the supply will not properly start. The test

consists in either simulating or measuring in the lab how

much time the system takes to reach the regulation at full

load. Let’s suppose that this time corresponds to 6ms.

path is offered between V and GND. If the current sense

CC

pin is often the seat of such spurious signals, the

high−voltage pin can also be the source of problems in

certain circumstances. During the turn−off sequence, e.g.

when the user unplugs the power supply, the controller is still

Therefore a V

fall time of 10 ms could be well

CC

appropriated in order to not trigger the overload detection

circuitry. If the corresponding IC consumption, including

the MOSFET drive, establishes at 1.5 mA, we can calculate

the required capacitor using the following formula:

DV @ C

fed by its V capacitor and keeps activating the MOSFET

CC

ON and OFF with a peak current limited by Rsense.

Unfortunately, if the quality coefficient Q of the resonating

network formed by Lp and Cbulk is low (e.g. the MOSFET

Rdson + Rsense are small), conditions are met to make the

circuit resonate and thus negatively bias the controller. Since

we are talking about ms pulses, the amount of injected

charge (Q = I x t) immediately latches the controller which

Dt +

, with DV = 2V. Then for a wanted Dt of 10 ms,

i

C equals 8 mF or 10 mF for a standard value. When an

overload condition occurs, the IC blocks its internal

circuitry and its consumption drops to 350 mA typical. This

brutally discharges its V capacitor. If this V capacitor

CC

appends at V = 9.8 V and it remains stuck until V

CC

is of sufficient value, its stored energy damages the

controller. Figure 21 depicts a typical negative shot

reaches 6.5 V: we are in latchoff phase. Again, using the

calculated 10 mF and 350 mA current consumption, this

latchoff phase lasts: 109 ms.

occurring on the HV pin where the brutal V discharge

CC

testifies for latchup.

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10

NCP1200

Figure 21. A negative spike takes place on the Bulk capacitor at the switch−off sequence

Simple and inexpensive cures exist to prevent from

internal parasitic SCR activation. One of them consists in

inserting a resistor in series with the high−voltage pin to

keep the negative current to the lowest when the bulk

becomes negative (Figure 22). Please note that the negative

spike is clamped to –2 x Vf due to the diode bridge. Please

refer to AND8069/D for power dissipation calculations.

Another option (Figure 23) consists in wiring a diode from

to the bulk capacitor to force V to reach UVLOlow

sooner and thus stops the switching activity before the bulk

capacitor gets deeply discharged. For security reasons, two

diodes can be connected in series.

V

CC

3

Rbulk

> 4.7 k

2

3

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

D3

1N4007

+

Cbulk

1

+

CV

+

CV

CC

Figure 22. A simple resistor in series avoids any

latchup in the controller

Figure 23. or a diode forces V_CCto reach

UVLOlow sooner

A Typical Application

inherent short−circuit protection of the NCP1200, you only

need a bunch of components around the IC, keeping the final

cost at an extremely low level. The transformer is available

from different suppliers as detailed on the following page.

Figure 24 depicts a low−cost 3.5 W AC−DC 6.5 V wall

adapter. This is a typical application where the wall−pack

must deliver a raw DC level to a given internally regulated

apparatus: toys, calculators, CD players etc. Due to the

http://onsemi.com

11

NCP1200

R7

Clamping

Network

L5

330 mH

L4

2.2 mH

6.5 V @ 600 mA

R

clamp

+

D3

1N5819

C5

470 mF/

10 V

C10

4.7 mF/

10 V

C3

4.7 mF

400 V

C2

4.7 mF

400 V

+

Clamp

T1

NCP1200

D

clamp

1

2

3

4

HV

Adj

8

7

6

5

Snubber

Optional

Networks

FB

NC

R2

220

CS

V

CC

R

Snubber

GND Drv

M1

C

Snubber

MTD1N60E

Universal

Input

+

R6

2.8

C9

10 mF

L6

330 mH

R9

10

D6

5 V1

IC1

SFH615A−2

Figure 24. A typical AC−DC wall adapter showing the reduced part count due to the NCP1200

T1: Lp = 2.9 mH, Np:Ns = 1:0.08, leakage = 80 mH, E16 core, NCP1200P40

To help designers during the design stage, several manufacturers propose ready−to−use transformers for the above

application, but can also develop devices based on your particular specification:

Eldor Corporation Headquarter

Via Plinio 10,

Atelier Special de Bobinage

125 cours Jean Jaures

22030 Orsenigo

38130 ECHIROLLES FRANCE

Tel.: 33 (0)4 76 23 02 24

(Como) Italia

Tel.: +39−031−636 111

Fax: 33 (0)4 76 22 64 89

Fax : +39−031−636 280

Email: eldor@eldor.it

Email: asb@wanadoo.fr

ref. 1: NCP1200−10 W−UM: 10 W for USB

(Lp = 1.8 mH, 60 kHz, 1:0.1, RM8 pot core)

Coilcraft

www.eldor.it

ref. 1: 2262.0058C: 3.5 W version

(Lp = 2.9 mH, Lleak = 80 mH, E16)

ref. 2: 2262.0059A: 5 W version

(Lp = 1.6 mH, Lleak = 45 mH, E16)

EGSTON GesmbH

1102 Silver Lake Road

Cary, Illinois 60013 USA

Tel: (847) 639−6400

Fax: (847) 639−1469

Grafenbergerstrabe 37

Email: info@coilcraft.com

http://www.coilcraft.com

3730 Eggenburg

Austria

ref. 1: Y8844−A: 3.5 W version

(Lp = 2.9 mH, Lleak = 65 mH, E16)

ref. 2: Y8848−A: 10 W version

(Lp = 1.8 mH, Lleak = 45 mH, 1:01, E core)

Tel.: +43 (2984) 2226−0

Fax : +43 (2984) 2226−61

Email: info@egston.com

http://www.egston.com/english/index.htm

ref. 1: F0095001: 3.5 W version

(Lp = 2.7 mH, Lleak = 30 mH, sandwich configuration, E16)

http://onsemi.com

12

NCP1200

Improving the Output Drive Capability

1

2

3

4

8

7

6

5

The NCP1200 features an asymmetrical output stage used

to soften the EMI signature. Figure 25 depicts the way the

driver is internally made:

2N2222

2N2907

NCP1200

Rd

To Gate

V

CC

Q

2

7

40

Figure 26. Improving Both Turn−On and

Turn−Off Times

1

5

12

1

2

3

4

8

7

6

5

Q\

NCP1200

3

1N4148

To Gate

2N2907

Figure 25. The higher ON resistor slows down

the MOSFET while the lower OFF resistor

ensures fast turn−off.

In some cases, it is possible to expand the output drive

capability by adding either one or two bipolar transistors.

Figures 26, 27, and 28 give solutions whether you need to

improve the turn−on time only, the turn−off time or both. Rd

is there to damp any overshoot resulting from long copper

traces. It can be omitted with short connections. Results

showed a rise fall time improvement by 5X with standard

2N2222/2N2907:

Figure 27. Improving Turn−Off Time Only

1

2

3

4

8

7

NCP1200

2N2222

To Gate

6

5

1N4148

Figure 28. Improving Turn−On Time Only

http://onsemi.com

13

NCP1200

If the leakage inductance is kept low, the MTD1N60E can

withstand accidental avalanche energy, e.g. during a

high−voltage spike superimposed over the mains, without

the help of a clamping network. If this leakage path

permanently forces a drain−source voltage above the

MOSFET BVdss (600 V), a clamping network is mandatory

and must be built around Rclamp and Clamp. Dclamp shall

react extremely fast and can be a MUR160 type. To calculate

the component values, the following formulas will help you:

V

: the clamping ripple, could be around 20 V

Another option lies in implementing a snubber network

ripple

which will damp the leakage oscillations but also provide

more capacitance at the MOSFET’s turn−off. The peak

voltage at which the leakage forces the drain is calculated

by:

L

leak

V

+ Ip @

Ǹ

max

C

lump

R

clamp =

where C

represents the total parasitic capacitance seen

lump

at the MOSFET opening. Typical values for Rsnubber and

Csnubber in this 4W application could respectively be 1.5

kW and 47 pF. Further tweaking is nevertheless necessary to

tune the dissipated power versus standby power.

2 @ V

@ (V

* (V

) Vf sec) @ N)

out

clamp

L

@ Ip²@ Fsw

leak

V

clamp

@ Fsw @ R

C

+

Available Documents

clamp

V

ripple

clamp

“Implementing the NCP1200 in Low−cost AC−DC

Converters”, AND8023/D.

with:

V

: the desired clamping level, must be selected to be

clamp

“Conducted EMI Filter Design for the NCP1200’’,

AND8032/D.

between 40 V to 80 V above the reflected output voltage

when the supply is heavily loaded.

“Ramp Compensation for the NCP1200’’, AND8029/D.

V

+ Vf: the regulated output voltage level + the secondary

out

TRANSient and AC models available to download at:

http://onsemi.com/pub/NCP1200

diode voltage drop

L

leak

: the primary leakage inductance

NCP1200 design spreadsheet available to download at:

http://onsemi.com/pub/NCP1200

N: the Ns:Np conversion ratio

: the switching frequency

F

SW

ORDERING INFORMATION

Device

†

Type

Marking

Package

Shipping

NCP1200P40

1200P40

PDIP−8

50 Units / Rail

NCP1200P40G

1200P40

PDIP−8

50 Units / Rail

(Pb−Free)

F

SW

= 40 kHz

NCP1200D40R2

200D4

SOIC−8

2500 Units /Reel

NCP1200D40R2G

SOIC−8

(Pb−Free)

NCP1200P60

1200P60

PDIP−8

50 Units / Rail

NCP1200P60G

PDIP−8

(Pb−Free)

F

SW

= 60 kHz

NCP1200D60R2

200D6

SOIC−8

2500 Units /Reel

NCP1200D60R2G

SOIC−8

(Pb−Free)

NCP1200P100

1200P100

PDIP−8

50 Units / Rail

NCP1200P100G

PDIP−8

(Pb−Free)

F

SW

= 100 kHz

NCP1200D100R2

NCP1200D100R2G

200D1

SOIC−8

2500 Units / Reel

SOIC−8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

http://onsemi.com

14

NCP1200

PACKAGE DIMENSIONS

SOIC−8

D SUFFIX

CASE 751−07

ISSUE AC

NOTES:

−X−

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

A

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

8

5

4

S

M

B

0.25 (0.010)

Y

1

K

−Y−

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.197

0.157

0.069

0.020

C

N X 45

_

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

SEATING

PLANE

−Z−

0.10 (0.004)

1.27 BSC

0.050 BSC

M

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

J

H

D

8

0

_

M

S

X

0.25 (0.010)

Z

Y

0.25

5.80

0.50 0.010

6.20 0.228

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

4.0

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

15

NCP1200

PACKAGE DIMENSIONS

PDIP−8

P SUFFIX

CASE 626−05

ISSUE L

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

8

5

2. PACKAGE CONTOUR OPTIONAL (ROUND OR

SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−B−

1

4

MILLIMETERS

INCHES

MIN

DIM MIN

MAX

10.16

6.60

4.45

0.51

1.78

MAX

0.400

0.260

0.175

0.020

0.070

A

B

C

D

F

9.40

6.10

3.94

0.38

1.02

0.370

0.240

0.155

0.015

0.040

F

−A−

NOTE 2

L

G

H

J

2.54 BSC

0.100 BSC

0.76

0.20

2.92

1.27

0.30

3.43

0.030

0.008

0.115

0.050

0.012

0.135

K

L

C

7.62 BSC

0.300 BSC

M

N

−−−

0.76

10

_

1.01

−−−

0.030

10

_

0.040

J

−T−

SEATING

PLANE

N

M

D

K

G

H

M

0.13 (0.005)

T

A

B

The product described herein (NCP1200), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There may

be other patents pending.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada

Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

NCP1200/D

http://onsemi.com

16

型号:	NCP1200P60G
Brand Name：	ON Semiconductor
是否无铅：	不含铅
生命周期：	Not Recommended
零件包装代码：	DIP
包装说明：	DIP, DIP8,.3
针数：	8
制造商包装代码：	626-05
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	6.84
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最小输入电压：	11 V
标称输入电压：	11 V
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e3
长度：	9.78 mm
功能数量：	1
端子数量：	8
最大输出电流：	0.25 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	4.45 mm
子类别：	Switching Regulator or Controllers
表面贴装：	NO
切换器配置：	SINGLE
最大切换频率：	70 kHz
技术：	CMOS
端子面层：	Tin (Sn)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	7.62 mm
Base Number Matches：	1

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