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产品型号NCP1579DR2G的概述

NCP1579DR2G芯片概述 NCP1579DR2G是一款由意法半导体（ON Semiconductor）设计和制造的高端DC/DC转换器。该芯片特别适用于在电源设计中实现高效率、高性能的控制，广泛应用于电子产品中的电源管理系统，例如笔记本电脑、平板电脑以及各种便携式设备。这款芯片凭借其高效能、灵活性和多种保护功能，成为了电源工程师的热门选择。 NCP1579DR2G具备多种输出选择，可支持 ±2A到2A的输出电流范围，适应不同负载条件的需求。同时，该芯片实现了高达95%的转换效率，降低了电源损耗，这对于现代电子设备尤其重要，因为这些设备通常需要在电池供电下长时间工作。 NCP1579DR2G详细参数在讨论NCP1579DR2G的具体功能之前，了解其基本参数是必要的。以下是该芯片的一些关键特性： - 输入电压范围：4.5 V至22 V - 输出电压范围：0.8 V至12 V - 输...

产品型号NCP1579DR2G的Datasheet PDF文件预览

NCP1579

Low Voltage Synchronous

Buck Controller

The NCP1579 is a low cost PWM controller designed to operate

from a 5 V or 12 V supply. This device is capable of producing an

output voltage as low as 0.8 V. This 8−pin device provides an optimal

level of integration to reduce size and cost of the power supply. The

NCP1579 provides a 1 A gate driver design and an internally set

275 kHz oscillator. In addition to the 1 A gate drive capability, other

efficiency enhancing features of the gate driver include adaptive

non−overlap circuitry. The device also incorporates an externally

compensated error amplifier and a capacitor programmable soft−start

function. Protection features include programmable short circuit

protection and undervoltage lockout (UVLO). The NCP1579 comes in

an 8−pin SOIC package.

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MARKING DIAGRAM

SOIC−8

D SUFFIX

CASE 751

1579

ALYW

1579 = Specific Device Code

Features

= Assembly Location

= Wafer Lot

• Input Voltage Range from 4.5 to 13.2 V

• 275 kHz Internal Oscillator

• Boost Pin Operates to 30 V

• Voltage Mode PWM Control

• 0.8 V 2.0 % Internal Reference Voltage

• Adjustable Output Voltage

= Year

= Work Week

= Pb−Free Device

PIN CONNECTIONS

• Capacitor Programmable Soft−Start

• Internal 1 A Gate Drivers

BST

PHASE

COMP/DIS

GND

• 80% Max Duty Cycle

• Input Under Voltage Lockout

• Programmable Current Limit

• This is a Pb−Free Device

(Top View)

Applications

• STB

ORDERING INFORMATION

• Blue−Ray DVD

• LCD_TV

†

Device

NCP1579DR2G

Package

Shipping

SOIC−8

2500/Tape & Reel

• DSP & FPGA Power Supply

• DC−DC Regulator Modules

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

Publication Order Number:

September, 2008 − Rev. 0

NCP1579/D

NCP1579

BST

COMP/DIS

GND

OUT

PHASE

Figure 1. Typical Application Diagram

POR

UVLO

VOCTH

SCP

FAULT

LATCH

BST

FAULT

PWM

OUT

0.8 V

REF

)

PHASE

Clock

2 V

Ramp

COMP/DIS

OSC

set

FAULT

GND

Figure 2. Detailed Block Diagram

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NCP1579

PIN FUNCTION DESCRIPTION

Pin No.

Symbol

Description

BST

Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the

desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (C ) between this pin

BST

and the PHASE pin. Typical values for C

range from 0.1 mF to 1 mF. Ensure that C

is placed near the IC.

BST

GND

Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET.

IC ground reference. All control circuits are referenced to this pin.

Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET.

Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF

capacitor to GND. Ensure that this decoupling capacitor is placed near the IC.

This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to

compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or dir-

ectly to V

out

COMP/DIS

PHASE

Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM com-

parator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. The com-

pensation capacitor also acts as a soft−start capacitor. Pull this pin low for disable.

Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top

MOSFET.

ABSOLUTE MAXIMUM RATINGS

Pin Name

Symbol

MAX

MIN

Main Supply Voltage Input

Bootstrap Supply Voltage Input

15 V

−0.3 V

BST

30 V wrt/GND

15 V wrt/PHASE

35 V wrt/GND for < 50

Switching Node (Bootstrap Supply Return)

High−Side Driver Output (Top Gate)

Low−Side Driver Output (Bottom Gate)

PHASE

26 V

−0.7 V

−5.0 V for < 50 ns

30 V wrt/GND

15 V wrt/PHASE

−0.3 V

wrt/PHASE

15 V

−0.3 V

−2.0 V for < 200 ns

Feedback

5.5 V

−0.3 V

COMP/DISABLE

COMP/DIS

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

°C/W

°C

Thermal Resistance, Junction−to−Ambient

Thermal Resistance, Junction−to−Case

Operating Junction Temperature Range

Operating Ambient Temperature Range

Storage Temperature Range

165

0 to 125

0 to 70

−55 to +150

260

°C

stg

°C

Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free

°C

Moisture Sensitivity Level

MSL

−

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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NCP1579

ELECTRICAL CHARACTERISTICS (0_C < T < 70_C; 4.5 V < V < 13.2 V, 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V,

0 V < PHASE < 21 V, C = C = 1.0 nF, for min/max values unless otherwise noted.)

Characteristic

Conditions

Min

4.5

Typ

−

Max

13.2

26.5

Unit

Input Voltage Range

−

Boost Voltage Range

Supply Current

−

Quiescent Supply Current

Boost Quiescent Current

Under Voltage Lockout

UVLO Threshold

= 1.0 V, No Switching, V = 13.2 V

1.0

0.1

−

8.0

1.0

= 1.0 V, No Switching, V = 13.2 V

Rising Edge

3.8

−

4.2

UVLO Hysteresis

−

300

370

440

Switching Regulator

VFB Feedback Voltage,

Control Loop in Regulation

T = 0 to 70°C

784

800

816

Oscillator Frequency

Ramp−Amplitude Voltage

Minimum Duty Cycle

Maximum Duty Cycle

Error Amplifier (GM)

Transconductance

T = 0 to 70°C

233

0.8

275

1.1

−

317

1.4

−

kHz

3.0

−

4.4

mmho

Open Loop DC Gain

−

Output Source Current

Output Sink Current

< 0.8 V

> 0.8 V

120

−

Input Bias Current

Soft−Start

−

0.1

1.0

SS Source Current

Switch Over Threshold

Gate Drivers

< 0.8 V

= 0.8 V

7.0

−

100

−

% of Vref

Upper Gate Source

Upper Gate Sink

Lower Gate Source

Lower Gate Sink

−

1.0

2.0

−

= 12 V, VTG = VBG = 2.0 V

−

TG Falling to BG Rising Delay

BG Falling to TG Rising Delay

Enable Threshold

= 12 V, TG < 2.0 V, BG > 2.0 V

= 12 V, BG < 2.0 V, TG > 2.0 V

−

0.5

−

0.3

0.4

Over−Current Protection

OCSET Current Source

OC Switch−Over Threshold

Fixed OC Threshold

Sourced from BG pin, before SS

−

700

−375

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NCP1579

TYPICAL CHARACTERISTICS (T_A= 25°C unless otherwise noted)

5.0

4.7

4.4

4.1

203

202

201

= 12 V

200

199

198

3.8

3.5

= 5 V

T , JUNCTION TEMPERATURE (°C)

Figure 3. I_CCvs. Temperature

Figure 4. Oscillator Frequency (F_SW) vs.

Temperature

375

365

355

345

335

325

T , JUNCTION TEMPERATURE (°C)

Figure 5. Soft Start Sourcing Current vs.

Temperature

Figure 6. SCP Threshold vs. Temperature

808

806

804

802

800

798

796

794

792

T , JUNCTION TEMPERATURE (°C)

Figure 7. Reference Voltage (V_ref) vs.

Temperature

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NCP1579

DETAILED OPERATING DESCRIPTION

External Enable/Disable

General

The NCP1579 is a PWM controller intended for DC−DC

When the Comp pin voltage falls or is pulled externally

below the 400 mV threshold, it disables the PWM Logic and

the gate drive outputs. In this disabled mode, the operational

transconductance amplifier (EOTA) output source current is

reduced and limited to the Soft−Start mode of 10 mA.

conversion from 5.0 V & 12 V buses. The devices have a 1

A internal gate driver circuit designed to drive N−channel

MOSFETs in a synchronous−rectifier buck topology. The

output voltage of the converter can be precisely regulated

down to 800 mV 2.0% when the V pin is tied to V

OUT

Normal Shutdown Behavior

The switching frequency, is internally set to 275 kHz. A high

gain operational transconductance error amplifier (OTA) is

used.

Normal shutdown occurs when the IC stops switching

because the input supply reaches UVLO threshold. In this

case, switching stops, the internal SS is discharged, and all

GATE pins go low. The switch node enters a high impedance

state and the output capacitors discharge through the load

with no ringing on the output voltage.

Duty Cycle and Maximum Pulse Width Limits

In steady state DC operation, the duty cycle will stabilize

at an operating point defined by the ratio of the input to the

output voltage. The devices can achieve an 80% duty cycle.

There is a built in off−time which ensures that the bootstrap

supply is charged every cycle. Both parts can allow a 12 V

to 0.8 V conversion at 275 kHz.

External Soft−Start

The NCP1579 features an external soft−start function,

which reduces inrush current and overshoot of the output

voltage. Soft−start is achieved by using the internal current

source of 10 mA (typ), which charges the external integrator

capacitor of the transconductance amplifier. Figure 8 is a

Input Voltage Range (V_CCand BST)

The input voltage range for both V and BST is 4.5 V to

13.2 V with respect to GND and PHASE, respectively.

Although BST is rated at 13.2 V with respect to PHASE, it

can also tolerate 26.4 V with respect to GND.

typical soft−start sequence. This sequence begins once V

surpasses its UVLO threshold and OCP programming is

complete. During soft−start, as the Comp Pin rises through

400 mV, the PWM Logic and gate drives are enabled. When

the feedback voltage crosses 800 mV, the EOTA will be

given control to switch to its higher regulation mode output

current of 120 mA.

4.0 V

0.85 V

Comp

0.8 V

550 mV

50 mV

OCP

Program

ming

out

UVLO

POR

NORMAL

Figure 8. Soft−Start Implementation

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NCP1579

UVLO

go through a Power On Reset (POR) cycle to reset the OCP

fault.

Undervoltage Lockout (UVLO) is provided to ensure that

unexpected behavior does not occur when V is too low to

support the internal rails and power the converter. For the

NCP1579, the UVLO is set to permit operation when

converting from a 5.0 input voltage.

Drivers

The NCP1579 includes gate drivers to switch external

N−channel MOSFETs. This allows the devices to address

high−power as well as low−power conversion requirements.

The gate drivers also include adaptive non−overlap

circuitry. The non−overlap circuitry increase efficiency,

which minimizes power dissipation, by minimizing the

body diode conduction time.

Overcurrent Threshold Setting

NCP1579 can easily program an Overcurrent Threshold

ranging from 50 mV to 550 mV, simply by adding a resistor

(RSET) between BG and GND. During a short period of

time following V rising over UVLO threshold, an internal

10 mA current (I

A detailed block diagram of the non−overlap and gate

drive circuitry used in the chip is shown in Figure 9.

) is sourced from BG pin,

OCSET

determining a voltage drop across R

. This voltage

OCSET

drop will be sampled and internally held by the device as

Overcurrent Threshold. The OC setting procedure overall

BST

FAULT

time length is about 6 ms. Connecting a R

resistor

OCSET

between BG and GND, the programmed threshold will be:

@ R

OCSET

(eq. 1)

OCth

DS(on)

PHASE

RSET values range from 5 kW to 55 kW. In case R

OCSET

is not connected, the device switches the OCP threshold to

a fixed 375 mV value: an internal safety clamp on BG is

triggered as soon as BG voltage reaches 700 mV, enabling

the 375 mV fixed threshold and ending OC setting phase.

The current trip threshold tolerance is 25 mV. The accuracy

of the set point is best at the highest set point (550 mV). The

accuracy will decrease as the set point decreases.

2 V

set

Current Limit Protection

In case of a short circuit or overload, the low−side (LS)

FET will conduct large currents. The controller will shut

down the regulator in this situation for protection against

FAULT

GND

Figure 9. Block Diagram

overcurrent. The low−side R

sense is implemented at

DS(on)

the end of each of the LS−FET turn−on duration to sense the

over current trip point. While the LS driver is on, the Phase

voltage is compared to the internally generated OCP trip

voltage. If the phase voltage is lower than OCP trip voltage,

an overcurrent condition occurs and a counter is initiated.

When the counter completes, the PWM logic and both

HS−FET and LS−FET are turned off. The controller has to

Careful selection and layout of external components is

required, to realize the full benefit of the onboard drivers.

The capacitors between V and GND and between BST

and SWN must be placed as close as possible to the IC. The

current paths for the TG and BG connections must be

optimized. A ground plane should be placed on the closest

layer for return currents to GND in order to reduce loop area

and inductance in the gate drive circuit.

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NCP1579

APPLICATION SECTION

Input Capacitor Selection

The above calculation includes the delay from comp

rising to when output voltage starts becomes valid.

To calculate the time of output voltage rising to when it

reaches regulation; DV is the difference between the comp

voltage reaching regulation and 0.88 V.

The input capacitor has to sustain the ripple current

produced during the on time of the upper MOSFET, so it

must have a low ESR to minimize the losses. The RMS value

of this ripple is:

Iin_RMS+ I_OUTD (1 * D) ,

Output Capacitor Selection

The output capacitor is a basic component for the fast

response of the power supply. In fact, during load transient,

for the first few microseconds it supplies the current to the

load. The controller immediately recognizes the load

transient and sets the duty cycle to maximum, but the current

slope is limited by the inductor value.

During a load step transient the output voltage initial

drops due to the current variation inside the capacitor and the

ESR. ((neglecting the effect of the effective series

inductance (ESL)):

where D is the duty cycle, Iin

is the input RMS current,

RMS

& I

is the load current. The equation reaches its

OUT

maximum value with D = 0.5. Loss in the input capacitors

can be calculated with the following equation:

_CIN+ ESR_CIN Iin_RMS

where P

is the power loss in the input capacitors &

CIN

ESR

is the effective series resistance of the input

CIN

capacitance. Due to large dI/dt through the input capacitors,

electrolytic or ceramics should be used. If a tantalum must

be used, it must by surge protected. Otherwise, capacitor

failure could occur.

DV_OUT−ESR+ DI_OUT ESR_COUT

where V

is the voltage deviation of V

due to the

OUT-ESR

OUT

Calculating Input Start-up Current

To calculate the input start up current, the following

equation can be used.

effects of ESR and the ESR

is the total effective series

COUT

resistance of the output capacitors.

A minimum capacitor value is required to sustain the

current during the load transient without discharging it. The

voltage drop due to output capacitor discharge is given by

the following equation:

C_OUT V_OUT

I_inrush

t_SS

where I

is the input current during start-up, C

is the

inrush

OUT

DI_OUT L_OUT

2 C_OUT (V_IN D * V_OUT

total output capacitance, V

is the desired output voltage,

OUT

DV_{OUT−DISCHARGE}

)

and t is the soft start interval.

If the inrush current is higher than the steady state input

current during max load, then the input fuse should be rated

accordingly, if one is used.

where V

due to the effects of discharge, L

value & V is the input voltage.

is the voltage deviation of V

OUT

OUT-DISCHARGE

is the output inductor

OUT

It should be noted that ΔV

OUT-ESR

of these two voltages will determine the maximum deviation

of the output voltage (neglecting the effect of the ESL).

and

OUT-DISCHARGE

Calculating Soft Start Time

To calculate the soft start time, the following equation can

be used.

ΔV

are out of phase with each other, and the larger

(C_p) C_c) * DV

t_ss

I_ss

Inductor Selection

Both mechanical and electrical considerations influence

the selection of an output inductor. From a mechanical

perspective, smaller inductor values generally correspond to

smaller physical size. Since the inductor is often one of the

largest components in the regulation system, a minimum

inductor value is particularly important in space-constrained

applications. From an electrical perspective, the maximum

current slew rate through the output inductor for a buck

regulator is given by:

Where C is the compensation as well as the soft start

capacitor,

C is the additional capacitor that forms the second pole.

I is the soft start current

DV is the comp voltage from zero to until it reaches

regulation

_IN* V_OUT

L_OUT

880 mV

SlewRate_LOUT

This equation implies that larger inductor values limit the

regulator’s ability to slew current through the output

inductor in response to output load transients. Consequently,

output capacitors must supply the load current until the

inductor current reaches the output load current level. This

results in larger values of output capacitance to maintain

Vcomp

Vout

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NCP1579

tight output voltage regulation. In contrast, smaller values of

Figure 10 shows a typical Type II transconductance error

amplifier (EOTA). The compensation network consists of

the internal error amplifier and the impedance networks ZIN

inductance increase the regulator’s maximum achievable

slew rate and decrease the necessary capacitance, at the

expense of higher ripple current. The peak-to-peak ripple

current for NCP1579 is given by the following equation:

(R , R ) and external Z

(R , C and C ). The

c c p

compensation network has to provide a closed loop transfer

function with the highest 0 dB crossing frequency to have

_OUT(1 * D)

Ipk * pk_LOUT

fast response (but always lower than F /8) and the highest

L_OUT 275 kHz

gain in DC conditions to minimize the load regulation. A

stable control loop has a gain crossing with -20 dB/decade

slope and a phase margin greater than 45°. Include

worst-case component variations when determining phase

margin. Loop stability is defined by the compensation

network around the EOTA, the output capacitor, output

inductor and the output divider. Figure 11 shows the open

loop and closed loop gain plots.

where Ipk-pk

is the peak to peak current of the output.

LOUT

From this equation it is clear that the ripple current increases

as L decreases, emphasizing the trade-off between

OUT

dynamic response and ripple current.

Feedback and Compensation

The NCP1579 allows the output of the DC-DC converter

to be adjusted from 0.8 V to 5.0 V via an external resistor

divider network. The controller will try to maintain 0.8 V at

the feedback pin. Thus, if a resistor divider circuit was

Compensation Network Frequency:

The inductor and capacitor form a double pole at the

frequency

placed across the feedback pin to V

, the controller will

OUT

regulate the output voltage proportional to the resistor

divider network in order to maintain 0.8 V at the FB pin.

F_LC

2p L_o C_o

OUT

The ESR of the output capacitor creates a “zero” at the

frequency,

F_ESR

2p ESR C_o

The zero of the compensation network is formed as,

F_Z

2p R_cC_c

The pole of the compensation network is calculated as,

The relationship between the resistor divider network above

and the output voltage is shown in the following equation:

F_p+

2p R_c C_p

V_REF

_OUT* V_REF

R₂+ R₁

Resistor R1 is selected based on a design tradeoff between

efficiency and output voltage accuracy. For high values of

R1 there is less current consumption in the feedback

network, However the trade off is output voltage accuracy

due to the bias current in the error amplifier. The output

voltage error of this bias current can be estimated using the

following equation (neglecting resistor tolerance):

0.1 mA R₁

Error% +

100%

V_REF

Once R1 has been determined, R2 can be calculated.

Figure 11. Gain Plot of the Error Amplifier

Thermal Considerations

The power dissipation of the NCP1579 varies with the

MOSFETs used, V , and the boost voltage (V ). The

BST

average MOSFET gate current typically dominates the

control IC power dissipation. The IC power dissipation is

determined by the formula:

ref

−

_IC+ (I_CC V_CC) ) P_TG) P_BG

Figure 10. Type II Transconductance Error

Amplifier

Where:

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NCP1579

= control IC power dissipation,

= IC measured supply current,

= IC supply voltage,

= top gate driver losses,

= bottom gate driver losses.

NCP1579

The upper (switching) MOSFET gate driver losses are:

_TG+ Q_TG f_SW V_BST

Where:

Figure 12. Components to be Considered for

Layout Specifications

Q = total upper MOSFET gate charge at VBST,

= the switching frequency,

BST

= the BST pin voltage.

The lower (synchronous) MOSFET gate driver losses are:

_BG+ Q_BG f_SW V_CC

Where:

= total lower MOSFET gate charge at V

The junction temperature of the control IC can then be

calculated as:

T_J+ T_A) P_IC q_JA

Where:

T = the junction temperature of the IC,

T = the ambient temperature,

= the junction−to−ambient thermal resistance of the

IC package.

The package thermal resistance can be obtained from the

specifications section of this data sheet and a calculation can

be made to determine the IC junction temperature. However,

it should be noted that the physical layout of the board, the

proximity of other heat sources such as MOSFETs and

inductors, and the amount of metal connected to the IC,

impact the temperature of the device. Use these calculations

as a guide, but measurements should be taken in the actual

application.

Layout Considerations

As in any high frequency switching converter, layout is

very important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding. The figure below shows the critical power

components of the converter. To minimize the voltage

overshoot the interconnecting wires indicated by heavy lines

should be part of ground or power plane in a printed circuit

board. The components shown in the figure below should be

located as close together as possible. Please note that the

capacitors C and C

each represent numerous physical

OUT

capacitors. It is desirable to locate the NCP1579 within 1

inch of the MOSFETs, Q1 and Q2. The circuit traces for the

MOSFETs’ gate and source connections from the NCP1579

must be sized to handle up to 2 A peak current.

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NCP1579

PACKAGE DIMENSIONS

SOIC−8

D SUFFIX

CASE 751−07

ISSUE AJ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

−X−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.25 (0.010)

−Y−

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.197

0.157

0.069

0.020

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

N X 45

SEATING

PLANE

−Z−

1.27 BSC

0.050 BSC

0.10 (0.004)

0.10

0.19

0.40

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

0.020

0.244

0.25

5.80

0.50 0.010

6.20 0.228

0.25 (0.010)

SOLDERING FOOTPRINT*

1.52

0.060

7.0

4.0

0.275

0.155

0.6

0.024

1.270

0.050

inches

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

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Order Literature: http://www.onsemi.com/orderlit

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP1579/D

http://onsemi.com

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NCP1579DR2G产品参数

型号:	NCP1579DR2G
Brand Name：	ON Semiconductor
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
制造商包装代码：	751-07
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	1.53
其他特性：	ALSO OPERATES IN ADJUSTABLE MODE FROM 0.8 TO 5 V
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	13.2 V
最小输入电压：	4.5 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	PUSH-PULL
最大切换频率：	317 kHz
温度等级：	COMMERCIAL
端子面层：	Tin (Sn)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

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