NCP360
In Operation
EN Input
NCP360 provides overvoltage protection for positive
voltage, up to 20ꢀV. A PMOS FET protects the systems
(i.e.: VBUS) connected on the V pin, against positive
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
out
over-voltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Internal PMOS FET
Undervoltage Lockout (UVLO)
NCP360 includes an internal PMOS FET to protect the
systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
To ensure proper operation under any conditions, the
device has a built-in undervoltage lock out (UVLO)
circuit. During V positive going slope, the output remains
R
, during normal operation, will create low losses on
DSon
in
disconnected from input until V voltage is above 3.2ꢀV
in
V pin, characterized by V versus V dropout. (See
out in out
Figure 16).
nominal. The FLAGV output is pulled to low as long as V
in
does not reach UVLO threshold. This circuit has a 50ꢀmV
hysteresis to provide noise immunity to transient condition.
ESD Tests
NCP360 fully support the IEC61000-4-2, level 4 (Input
pin, 1 mF mounted on board).
V
in
(V)
That means, in Air condition, V has a 15ꢀkV ESD
in
protected input. In Contact condition, V has 8ꢀkV ESD
in
20 V
protected input.
Please refer to Fig 19 to see the IEC 61000-4-2
electrostatic discharge waveform.
OVLO
UVLO
0
V
out
OVLO
UVLO
0
Figure 18. Output Characteristic vs. Vin
Overvoltage Lockout (OVLO)
To protect connected systems on V
pin from
out
overvoltage, the device has a built-in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output
remains disabled until the input voltage exceeds OVLO -
Hysteresis.
FLAG output is tied to low until V is higher than
in
OVLO. This circuit has a 100ꢀmV hysteresis to provide
noise immunity to transient conditions.
Figure 19.
PCB Recommendations
FLAG Output
The NCP360 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
NCP360 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded When V level recovers normal condition,
in
FLAG is held high. The pin is an open drain output, thus a
pull up resistor (typically 1 MW- Minimum 10 kW) must
be provided to V . FLAG pin is an open drain output.
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