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产品型号NCP81162MNR2G的概述

NCP81162MNR2G芯片概述 NCP81162MNR2G是一款高性能的驱动器芯片，专为电源管理和高端MOSFET驱动而设计。它广泛应用于各种电源模块和开关电源中，为系统提供了高效的工作模式和可靠的性能。在现代电子设备中，尤其是服务器、计算机和其他工业应用中，电源管理的效率和可靠性显得尤为重要。NCP81162MNR2G正是解决这些问题的一个理想选择。此芯片采用了集成电路设计，具备多种保护机制，能够在高频率下进行工作，同时保持低功耗和高效率。其内部电路设计经过精密优化，可以有效地降低开关损失，从而提升整体系统性能。 NCP81162MNR2G详细参数 NCP81162MNR2G的主要技术参数如下： - 工作电压范围：4.5V到12V - 最大输出电流：驱动能力可达到2A - 工作频率：支持高达1MHz的开关频率 - 输入电压范围：通常在7V至10V之间 - 启动电流：典型值为30...

产品型号NCP81166的Datasheet PDF文件预览

NCP81166, NCP81166A

Synchronous Buck MOSFET

Drivers

The NCP81166/A is a high performance dual MOSFET gate driver

optimized to drive the gates of both high−side and low−side power

MOSFETs in a synchronous buck converter. 2mm x 2mm DFN8

package allows for space−optimized board layout.

http://onsemi.com

Zero current detect feature allows for a high−efficiency solution

even at light load conditions. Pre−OVP feature aids in protecting the

load in the event of a short across the high−side FET. V UVLO

ensures the MOSFETs are off when supply voltages are low. A

bi−directional Enable pin provides a fault signal to the controller

when a pre−OVP or UVLO fault is detected.

DFN8

MN SUFFIX

CASE 506CN

Features

MARKING DIAGRAM

• Space−Efficient 2 mm x 2mm DFN8 Thermally−Enhanced Package

• V Range of 4.5 V to 13.2 V

XXMG

• Integrated Bootstrap Diode

• Pre−OVP Function Protects Load during HS FET Short

♦ NCP81166: 2.25 V SW Trip Threshold

♦ NCP81166A: 1.8 V SW Trip Threshold

• Zero Current Detect Function Provides Power Saving Operation

during Light Load Conditions

XX = Specific Device Code

CE for NCP81166

CH for NCP81166A

= Date Code

= Pb−Free Device

• Bi−directional Enable Feature pulls Enable pin low during pre−OVP

and UVLO Faults

(Note: Microdot may be in either location)

• 5 V tri−state PWM Logic

• Adaptive Anti−Cross−Conduction Circuit Protects against

Cross−Conduction during FET turn−on and turn−off

• Output Disable Control turns off both MOSFETs via Enable pin

• VCC Undervoltage Lockout

ORDERING INFORMATION

†

Device

Package

Shipping

NCP81166MNTBG

DFN8

(Pb−Free)

3000 / Tape &

Reel

• Direct interface to ASP1252, ASP1400 and other compatible PWM

NCP81166AMNTBG

DFN8

(Pb−Free)

3000 / Tape &

Reel

Controllers

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Compliant

Typical Applications

• Power Solutions for Desktop Systems

Semiconductor Components Industries, LLC, 2015

Publication Order Number:

January, 2015 − Rev. 2

NCP81166/D

NCP81166, NCP81166A

PWM

BST

DRVH

GND

VCC

DRVL

(Top View)

Figure 1. Pin Diagram

BST

VCC

DRVH

PWM

Logic

Anti−Cross

Conduction

VCC

DRVL

ZCD

Detection

UVLO

Pre−OV

Fault

Figure 2. Block Diagram

Table 1. Pin Descriptions

Pin No.

Symbol

Description

PWM

Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emu-

lation Enabled, High = High Side FET Enabled.

No connect. There is no electrical connection from this pin to the die. Externally connecting this pin to ground

will not affect the functionality of the part.

Logic input. A logic high to enable the part and a logic low to disable the part. Pin is internally pulled low dur-

ing pre−OVP and UVLO faults.

VCC

DRVL

Power supply input. Connect a bypass capacitor (1 mF) from this pin to ground.

Low side gate drive output. Connect to the gate of low side MOSFET.

Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.

High side gate drive output. Connect to the gate of high side MOSFET.

DRVH

BST

Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and

the SW pin.

GND

Bias and reference ground. All signals are referenced to this node.

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NCP81166, NCP81166A

12V_POWER

TP1

R164

0.0

NTMFS4821N

0.027uF

4.7uF

C3 CE9

4.7uF 390uF

1.02

TP2

R142

0.0

NCP81166/A

TP3

R143

0.0

VREG_SW1_HG

VREG_SW1_OUT

BST HG

PWM SW

EN GND

TP4

PWM

TP5

VCCP

235nH

TP7

DRON

TP6

2.2

Q9 Q10

NTMFS4851N NTMFS4851N

VREG_SW1_LG

VCC LG

PAD

CSN11

CSP11

JP13_ETCH

JP14_ETCH

TP8

1uF

2700pF

Figure 3. Application Circuit

Pin Name

Table 2. ABSOLUTE MAXIMUM RATINGS

Pin Symbol

MAX

MIN

VCC

BST

Main Supply Voltage Input

15 V

−0.3 V

Bootstrap Supply Voltage

35 V wrt/ GND

−0.3 V wrt/SW

40 V ≤ 50 ns wrt/ GND

15 V wrt/ SW

Switching Node

(Bootstrap Supply Return)

35 V

−5 V

40 V ≤ 50 ns

−10 V (200 ns)

DRVH

DRVL

High Side Driver Output

Low Side Driver Output

BST+0.3 V

−0.3 V wrt/SW

−2 V (<200 ns) wrt/SW

VCC+0.3 V

−0.3 V DC

−5 V (<200 ns)

PWM

DRVH and DRVL Control Input

Enable Pin

6.5 V

0 V

−0.3 V

0 V

GND

Ground

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 3. THERMAL INFORMATION (All signals referenced to AGND unless noted otherwise)

Symbol

Parameter

Thermal Characteristic (Note 1)

Value

Unit

°C/W

°C

Operating Junction Temperature Range* (Note 2)

Operating Ambient Temperature Range*

Maximum Storage Temperature Range

Moisture Sensitivity Level

−40 to 150

−10 to +125

−55 to +150

°C

STG

°C

MSL

* The maximum package power dissipation must be observed.

1. I in Cu, 1 oz thickness.

2. Operation at −40°C to −10°C guaranteed by design, not production tested.

http://onsemi.com

NCP81166, NCP81166A

Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < T < +125°C; 4.5 V < V < 13.2 V,

4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)

Parameter Test Conditions

SUPPLY VOLTAGE

Min.

Typ.

Max.

Units

VCC Operation Voltage

Pre−OVP Threshold

4.5

13.2

3.2

2.75

UNDERVOLTAGE LOCKOUT

VCC Start Threshold

3.8

4.35

200

4.5

VCC UVLO Hysteresis

150

250

Output Overvoltage Trip Threshold at

Startup

VCC > Pre−OVP Threshold

NCP81166

NCP81166A

2.1

1.65

2.25

1.80

2.4

1.95

SUPPLY CURRENT

Normal Mode

Icc + Ibst, EN = 5 V, PWM = OSC, Fsw = 100 KHz,

Cload = 3 nF for DRVH, 3 nF for DRVL

Standby Current

Icc + Ibst, EN = GND

0.5

2.0

1.4

0.6

+ I , EN = HIGH, PWM = LOW,

BST

No loading on DRVH & DRVL

Standby Current

+ I , EN = HIGH, PWM = HIGH,

2.0

0.4

BST

No loading on DRVH & DRVL

BOOTSTRAP DIODE

Forward Voltage

= 12 V, forward bias current = 2 mA

0.1

PWM INPUT

PWM Input High

3.4

1.3

PWM Mid−State

2.7

0.7

PWM Input Low

ZCD Blanking Timer

250

HIGH SIDE DRIVER (VCC = 12 V)

Output Impedance, Sourcing Current

Output Impedance, Sinking Current

DRVH Rise Time trDRVH

DRVH Fall Time tfDRVH

DRVH Turn−Off Propagation Delay

VBST − VSW = 12 V

1.9

1.0

3.0

1.7

VCC

= 12 V, 3 nF load, VBST−VSW = 12 V

LOAD

= 3 nF

8.0

tpdl

DRVH

DRVH Turn−On Propagation Delay

tpdh

LOAD

= 3 nF

DRVH

SW Pull Down Resistance

SW to PGND

DRVH Pull Down Resistance

DRVH to SW, BST−SW = 0 V

HIGH SIDE DRIVER (VCC = 5 V)

Output Impedance, Sourcing Current

Output Impedance, Sinking Current

VBST − VSW = 5 V

2.5

1.6

DRVH Rise Time tr

VCC

= 5 V, 3 nF load, VBST − VSW = 5 V

DRVH

DRVH Fall Time tf

DRVH Turn−Off Propagation Delay

tpdl

LOAD

= 3 nF

DRVH

DRVH Turn−On Propagation Delay

tpdh

= 3 nF

LOAD

DRVH

SW Pull Down Resistance

SW to PGND

http://onsemi.com

NCP81166, NCP81166A

Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < T < +125°C; 4.5 V < V < 13.2 V,

4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)

Parameter

Test Conditions

Min.

Typ.

Max.

Units

HIGH SIDE DRIVER (VCC = 5 V)

DRVH Pull Down Resistance

DRVH to SW, BST−SW = 0 V

LOW SIDE DRIVER (VCC = 12 V)

Output Impedance, Sourcing Current

Output Impedance, Sinking Current

2.0

0.7

3.0

1.5

DRVL Rise Time tr

LOAD

= 3 nF

DRVL

DRVL Fall Time tf

DRVL Turn−Off Propagation Delay

tpdl

DRVL

DRVL Turn−On Propagation Delay

tpdh

LOAD

= 3 nF

8.0

DRVL

DRVL Pull Down Resistance

DRVL to PGND, VCC = PGND

LOW SIDE DRIVER (VCC = 5 V)

Output Impedance, Sourcing Current

Output Impedance, Sinking Current

2.5

1.0

DRVL Rise Time tr

LOAD

= 3 nF

DRVL

DRVL Fall Time tf

DRVL Turn−Off Propagation Delay

tpdl

DRVL

DRVL Turn−On Propagation Delay

tpdh

= 3 nF

LOAD

DRVL

DRVL Pull Down Resistance

EN INPUT

DRVL to PGND, VCC = PGND

Input Voltage High

2.0

Input Voltage Low

1.0

Hysteresis

500

Normal Mode Bias Current

Enable Pin Sink Current

Propagation Delay Time

SW Node

−1

SW Node Leakage Current

Zero Cross Detection Threshold Voltage

SW to −20 mV, ramp slowly until BG goes off

(Start in DCM mode) (Note 3)

−6

Table 5. DECODER TRUTH TABLE

PWM INPUT

ZCD

ZCD Reset

DRVL

DRVH

PWM High

Low

High

Low

High

Low

PWM Mid

Positive current through the inductor

Zero current through the inductor

ZCD Reset

PWM Mid

PWM Low

3. Guaranteed by design; not production tested.

http://onsemi.com

NCP81166, NCP81166A

PWM

DRVL

tpdl

DRVL

90%

1 V

10%

tpdh

10%

tpdl

DRVL

DRVH DRVH

DRVH

90%

1 V

10%

tpdh

10%

DRVH−SW

DRVL

Figure 4. Timing Diagram

PWM

DRVH−SW

DRVL

Figure 5. Logic Diagram

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NCP81166, NCP81166A

APPLICATIONS INFORMATION

Description

Pre−Overvoltage Protection

The NCP81166/A gate driver is a single phase MOSFET

driver designed for driving N−channel MOSFETs in a

synchronous buck converter topology. The NCP81166 is

designed to work with the ON Semiconductor’s ASP1252

controller and the NCP81166A is designed to work with

ON Semiconductor’s ASP1400 controller.

The pre−Overvoltage Protection (pre−OVP) feature is

used to protect the load if there is a short across the

high−side FET. When VCC is greater than 2.75 V, the

voltage on SW is monitored. During startup, if SW is

determined to be greater than Output Overvoltage Trip

Threshold, DRVL will be latched high to turn on the

synchronous FET and provide a path from VIN to ground.

This also pulls the EN pin low. To exit this behavior, power

to the driver must be turned off (VCC less than

Low−Side Driver

The low−side driver is designed to drive

ground−referenced low−R N−channel MOSFET. The

DS(on)

UVLO

minus UVLO hysteresis) and then VCC

RISING

voltage supply for the low−side driver is internally

connected to the VCC and GND pins. There is a 45 kW

pull−down resistor connected between DRVL and GND.

powered back on. When VCC rises above UVLO

RISING

and EN is above EN , the gate driver enters normal PWM

operation (DRVH and DRVL respond to the PWM signal)

and the pre−OVP function is disabled.

High−Side Driver

The high−side driver is designed to drive a floating

Bi*Directional EN Signal

low−R

N−channel MOSFET. The gate voltage for the

DS(on)

The Enable pin (EN) is used to disable the DRVH and

DRVL outputs to prevent power transfer. When EN is

high−side driver is developed by a bootstrap circuit

referenced to the SW pin. There is a 45 kW pull−down

resistor connected between DRVH and SW.

above the EN threshold, DRVH and DRVL change their

states according to the PWM input. Fault modes, such as

pre−OVP and UVLO, turn on an internal MOSFET that

pulls the EN pin towards ground. By connecting EN to the

DRON pin of a controller, the controller is alerted when the

driver encounters a fault condition.

The bootstrap circuit is comprised of the integrated diode

and an external bootstrap capacitor. When the

NCP81166/A is starting up, the SW pin is held at ground,

allowing the bootstrap capacitor to charge up to VCC

(minus the diode forward voltage) through the bootstrap

diode. When the PWM input is driven high, the high−side

driver will turn on the high−side MOSFET, using the stored

charge of the bootstrap capacitor. As the high−side

MOSFET turns on, the SW pin rises. When the high−side

MOSFET is fully turned on, SW will settle to VIN and BST

will settle to VIN + VCC (excluding parasitic ringing).

PWM Input and Zero Cross Detect (ZCD)

Switching PWM between logic−high and logic−low

states will allow the driver to operate in continuous

conduction mode as long as VCC is greater than the UVLO

threshold and EN is high. The threshold limits are specified

in the electrical characteristics table in this datasheet.

When PWM is set above PWM , DRVL will first turn

Bootstrap Circuit

The bootstrap circuit relies on an external charge storage

off after a propagation delay of tpdl . To ensure

DRVL

non−overlap between DRVL and DRVH, there is a delay of

tpdh from the time DRVL falls to 1 V, before DRVH

capacitor (C ) and an integrated diode to provide current

BST

DRVH

to the high−side driver. A multi−layer ceramic capacitor

(MLCC) with a value greater than 100 nF should be used

is allowed to turn on.

When PWM falls below PWM , DRVH will first turn

for C

BST

off after a propagation delay of tpdl . To ensure

DRVH

non−overlap between DRVH and DRVL, there is a delay of

tpdh from the time DRVH – SW falls to 1 V, before

DRVL is allowed to turn on.

Power Supply Decoupling

DRVL

The NCP81166/A can source and sink relatively large

currents to the gate pins of the MOSFETs. In order to

maintain a constant and stable supply voltage, a low−ESR

capacitor should be placed near the VCC and GND pins. A

MLCC between 1 mF and 4.7 mF is typically used.

When PWM enters the mid−state voltage range,

PWM

, DRVL goes high after the non−overlap delay,

MID

and stays high for the duration of the ZCD blanking timer

and an 80 ns de−bounce timer. Once these timers expire,

SW is monitored for zero current detection and pulls DRVL

low once zero current is detected.

Undervoltage Lockout

DRVH and DRVL are low until VCC reaches the VCC

UVLO threshold, typically 4.35 V. Once VCC reaches this

threshold, the PWM signal will control DRVH and DRVL.

There is a 200 mV hysteresis on VCC UVLO. There are

pull−down resistors on DRVH, DRVL and SW to prevent

the gates of the MOSFETs from accumulating enough

charge to turn on when the driver is powered off.

Layout Guidelines

Layout for DC−DC converter is very important. The

bootstrap and VCC bypass capacitors should be placed as

close as to the driver IC as possible.

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NCP81166, NCP81166A

Connect the GND flag to local ground plane. The ground

low−side MOSFET, the GND flag should be close to the

low−side FET source pin. The gate drive trace should be

routed to minimize the length, the minimum

recommended width is 20 mils.

plane can provide a good return path for gate drives and

reduce the ground noise. This connection also allows for

good heat dissipation. To minimize the ground loop for the

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NCP81166, NCP81166A

PACKAGE DIMENSIONS

DFN8 2x2, 0.5P

CASE 506CN

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

REFERENCE

DETAIL A

ALTERNATE

CONSTRUCTIONS

0.15

MILLIMETERS

DIM MIN

MAX

1.00

0.05

0.15

0.80

0.00

0.20 REF

TOP VIEW

MOLD CMPD

EXPOSED Cu

DETAIL B

0.20

0.30

0.10

2.00 BSC

1.50

2.00 BSC

0.80

0.50 BSC

0.27 REF

1.70

1.00

0.08

DETAIL B

ALTERNATE

SIDE VIEW

NOTE 4

0.17

−−−

0.38

0.15

SEATING

PLANE

CONSTRUCTION

RECOMMENDED

DETAIL A

8X L

SOLDERING FOOTPRINT*

PACKAGE

OUTLINE

0.50

1.75

1.05

2.30

0.10

C A B

e/2

0.10

NOTE 3

BOTTOM VIEW

0.30

0.50

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

MountingTechniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP81166/D

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