NCV2951ACDR2G中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

LP2950, LP2951, NCV2951

100 mA, Low Power Low

Dropout Voltage Regulator

The LP2950 and LP2951 are micropower voltage regulators that are

specifically designed to maintain proper regulation with an extremely

low input−to−output voltage differential. These devices feature a very

low quiescent bias current of 75 mA and are capable of supplying

output currents in excess of 100 mA. Internal current and thermal

limiting protection is provided.

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TO−92

CASE 29

The LP2951 has three additional features. The first is the Error

Output that can be used to signal external circuitry of an out of

regulation condition, or as a microprocessor power−on reset. The

second feature allows the output voltage to be preset to 5.0 V, 3.3 V or

3.0 V output (depending on the version) or programmed from 1.25 V

to 29 V. It consists of a pinned out resistor divider along with direct

access to the Error Amplifier feedback input. The third feature is

a Shutdown input that allows a logic level signal to turn−off or turn−on

the regulator output.

Pin: 1. Output

2. Ground

3. Input

1

2

3

BENT LEAD

TAPE & REEL

AMMO PACK

1

2

3

STRAIGHT LEAD

BULK PACK

PIN CONNECTIONS

Due to the low input−to−output voltage differential and bias current

specifications, these devices are ideally suited for battery powered

computer, consumer, and industrial equipment where an extension of

useful battery life is desirable. The LP2950 is available in the three

pin case 29 and DPAK packages, and the LP2951 is available in the

eight pin dual−in−line, SOIC−8 and Micro8 surface mount packages.

The ‘A’ suffix devices feature an initial output voltage tolerance

0.5%.

4

Pin: 1. Input

2

1

2. Ground

3. Output

3

1

2

3

DPAK

CASE 369C

(Top View)

Heatsink surface (shown as terminal 4 in

case outline drawing) is connected to Pin 2.

Features

• Low Quiescent Bias Current of 75 mA

• Low Input−to−Output Voltage Differential of 50 mV at 100 mA and

380 mV at 100 mA

SOIC−8

CASE 751

8

1

• 5.0 V, 3.3 V or 3.0 V 0.5% Allows Use as a Regulator or Reference

PDIP−8

CASE 626

• Extremely Tight Line and Load Regulation

• Requires Only a 1.0 mF Output Capacitor for Stability

• Internal Current and Thermal Limiting

8

1

8

Micro8E

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

CASE 846A

1

PIN CONNECTIONS

• These Devices are Pb−Free and RoHS Compliant

1

2

3

4

8

7

6

5

Output

Sense

Input

LP2951 Additional Features

Feedback

• Error Output Signals an Out of Regulation Condition

• Output Programmable from 1.25 V to 29 V

• Logic Level Shutdown Input

Shutdown

GND

V

O

Tap

Error Output

(See Following Page for Device Information.)

(Top View)

ORDERING & MARKING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on pages 14 and 15 of this data sheet.

See general marking information in the device marking

section on page 17 of this data sheet.

1

Publication Order Number:

January, 2018 − Rev. 30

LP2950/D

LP2950, LP2951, NCV2951

DEVICE INFORMATION

Output Voltage

Operating Ambient

Temperature Range

3.0 V

3.3 V

5.0 V

Adjustable

Package

TO−92

LP2950CZ−3.0

LP2950ACZ−3.0

LP2950CZ−3.3

LP2950ACZ−3.3

LP2950CZ−5.0

LP2950ACZ−5.0

Not

T = −40° to +125°C

A

Suffix Z

Available

DPAK

Suffix DT

LP2950CDT−3.0

LP2950ACDT−3.0

LP2950CDT−3.3

LP2950ACDT−3.3

LP2950CDT−5.0

LP2950ACDT−5.0

Not

T = −40° to +125°C

A

Available

SOIC−8

−

NCV2951ACD−3.3R2 NCV2951ACDR2

NCV2951CDR2

T = −40° to +125°C

A

SOIC−8

Suffix D

LP2951CD−3.0

LP2951ACD−3.0

LP2951CD−3.3

LP2951ACD−3.3

LP2951CD

T = −40° to +125°C

A

LP2951ACD

Micro8

Suffix DM

LP2951CDM−3.0

LP2951ACDM−3.0

LP2951CDM−3.3

LP2951ACDM−3.3

LP2951CDM

T = −40° to +125°C

A

LP2951ACDM

DIP−8

Suffix N

LP2951CN−3.0

LP2951ACN−3.0

LP2951CN−3.3

LP2951ACN−3.3

LP2951CN

T = −40° to +125°C

A

LP2951ACN

LP2950Cx−xx / LP2951Cxx−xx

LP2950ACx−xx / LP2951ACxx−xx

1% Output Voltage Precision at T = 25°C

A

0.5% Output Voltage Precision at T = 25°C

A

Input

Output

1

5.0 V/100 mA

3

1.0 mF

Battery or

Unregulated DC

182 k

60 k

Error Amplifier

1.23 V

Reference

LP2950CZ−5.0

GND

2

5.0 V/100 mA

Input

8

Output

Sense

2

1

Battery or

Unregulated DC

1.0 mF

Tap

182 k

60 k

V

6

O

330 k

7

Feedback

Error

Amplifier

Shutdown

From

CMOS/TTL

3

60 k

50 k

75 mV/

60 mV

Error

Output

To CMOS/TTL

5

Error Detection

Comparator

1.23 V

Reference

LP2951CD or CN

GND

4

This device contains 34 active transistors.

Figure 1. Representative Block Diagrams

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2

LP2950, LP2951, NCV2951

MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)

A

Rating

Symbol

Value

30

Unit

Vdc

Input Voltage

V

CC

Peak Transient Input Voltage (t < 300 ms)

V

32

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation

P

D

Internally Limited

W

Case 751(SOIC−8) D Suffix

Thermal Resistance, Junction−to−Ambient

Thermal Resistance, Junction−to−Case

Case 369A (DPAK) DT Suffix (Note 1)

Thermal Resistance, Junction−to−Ambient

Thermal Resistance, Junction−to−Case

Case 29 (TO−226AA/TO−92) Z Suffix

Thermal Resistance, Junction−to−Ambient

Thermal Resistance, Junction−to−Case

Case 626 N Suffix

R

180

45

°C/W

q

JA

R

q

JC

R

92

°C/W

q

JA

JC

6.0

q

R

160

83

°C/W

q

JA

JC

q

Thermal Resistance, Junction−to−Ambient

Case 846A (Micro8) DM Suffix

R

105

°C/W

q

JA

Thermal Resistance, Junction−to−Ambient

240

°C/W

q

JA

fb

Feedback Input Voltage

V

−1.5 to +30

Vdc

Shutdown Input Voltage

V

−0.3 to +30

−40 to +125

+150

Vdc

°C

sd

Error Comparator Output Voltage

Operating Ambient Temperature Range

Maximum Die Junction Temperature Range

Storage Temperature Range

V

err

T

A

T

°C

J

T

stg

−65 to +150

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

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3

LP2950, LP2951, NCV2951

ELECTRICAL CHARACTERISTICS

(V = V + 1.0 V, I = 100 mA, C = 1.0 mF, T = 25°C [Note 3], unless otherwise noted.)

in

O

A

Characteristic

Symbol

Min

Typ

Max

Unit

Output Voltage, 5.0 V Versions

= 6.0 V, I = 100 mA, T = 25°C

V

O

V

O

V

O

V

in

O

A

LP2950C−5.0/LP2951C/NCV2951C*

4.950

4.975

5.000

5.050

5.025

LP2950AC−5.0/LP2951AC/NCV2951AC*

T = −40 to +125°C

A

LP2950C−5.0/LP2951C/NCV2951C*

4.900

4.940

−

5.100

5.060

LP2950AC−5.0/LP2951AC/NCV2951AC*

V

in

= 6.0 to 30 V, I = 100 mA to 100 mA, T = −40 to +125°C

O A

LP2950C−5.0/LP2951C/NCV2951C*

LP2950AC−5.0/LP2951AC/NCV2951AC*

Output Voltage, 3.3 V Versions

= 4.3 V, I = 100 mA, T = 25°C

4.880

4.925

−

5.120

5.075

V

in

O

A

LP2950C−3.3/LP2951C−3.3

3.267

3.284

3.300

3.333

3.317

LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3*

T = −40 to +125°C

A

LP2950C−3.3/LP2951C−3.3

3.234

3.260

−

3.366

3.340

LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3*

V

in

= 4.3 to 30 V, I = 100 mA to 100 mA, T = −40 to +125°C

O A

LP2950C−3.3/LP2951C−3.3

LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3*

Output Voltage, 3.0 V Versions

= 4.0 V, I = 100 mA, T = 25°C

3.221

3.254

−

3.379

3.346

V

in

O

A

LP2950C−3.0/LP2951C−3.0

2.970

2.985

3.000

3.030

3.015

LP2950AC−3.0/LP2951AC−3.0

T = −40 to +125°C

A

LP2950C−3.0/LP2951C−3.0

2.940

2.964

−

3.060

3.036

LP2950AC−3.0/LP2951AC−3.0

V

in

= 4.0 to 30 V, I = 100 mA to 100 mA, T = −40 to +125°C

O A

LP2950C−3.0/LP2951C−3.0

2.928

2.958

−

3.072

3.042

LP2950AC−3.0/LP2951AC−3.0

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. The Junction−to−Ambient Thermal Resistance is determined by PCB copper area per Figure 29.

2. This device series contains ESD protection and exceeds the following tests:

Human Body Model (HBM), 2000 V, Class 2, JESD22 A114−C

Machine Model (MM), 200 V, Class B, JESD22 A115−A

Charged Device Model (CDM), 2000 V, Class IV, JESD22 C101−C

3. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

4. V

is the part number voltage option.

O(nom)

5. Noise tests on the LP2951 are made with a 0.01 mF capacitor connected across Pins 7 and 1.

*NCV prefix is for automotive and other applications requiring site and change control.

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4

LP2950, LP2951, NCV2951

ELECTRICAL CHARACTERISTICS (continued)

(V = V + 1.0 V, I = 100 mA, C = 1.0 mF, T = 25°C [Note 8], unless otherwise noted.)

in

O

A

Characteristic

Symbol

Min

Typ

Max

Unit

Line Regulation (V = V

+1.0 V to 30 V) (Note 9)

Reg

%

in

O(nom)

line

LP2950C−XX/LP2951C/LP2951C−XX/NCV2951C*

LP2950AC−XX/LP2951AC/LP2951AC−XX/NCV2951AC*

−

0.08

0.04

0.20

0.10

Load Regulation (I = 100 mA to 100 mA)

Reg

%

O

load

LP2950C−XX/LP2951C/LP2951C−XX/NCV2951C*

LP2950AC−XX/LP2951AC/LP2951AC−XX/NCV2951AC*

−

0.13

0.05

0.20

0.10

Dropout Voltage

V − V

mV

I

O

I

O

I

O

= 100 mA

−

30

350

80

450

Supply Bias Current

I

CC

I

= 100 mA

−

93

4.0

120

12

mA

O

Dropout Supply Bias Current (V = V

− 0.5 V,

I

CCdropout

−

110

170

mA

in

O(nom)

I

O

= 100 mA) (Note 9)

Current Limit (V Shorted to Ground)

I

−

220

300

mA

%/W

O

Limit

Thermal Regulation

Reg

0.05

0.20

thermal

Output Noise Voltage (10 Hz to 100 kHz) (Note 10)

C = 1.0 mF

C = 100 mF

L

V

n

mVrms

−

126

56

−

L

LP2951A/LP2951AC Only

Reference Voltage (T = 25°C)

LP2951C/LP2951C−XX/NCV2951C*

LP2951AC/LP2951AC−XX/NCV2951AC*

V

ref

V

ref

V

ref

V

A

1.210

1.220

1.235

1.260

1.250

Reference Voltage (T = −40 to +125°C)

A

LP2951C/LP2951C−XX/NCV2951C*

LP2951AC/LP2951AC−XX/NCV2951AC*

1.200

−

1.270

1.260

Reference Voltage (T = −40 to +125°C)

A

I

O

= 100 mA to 100 mA, V = 23 to 30 V

in

LP2951C/LP2951C−XX/NCV2951C*

LP2951AC/LP2951AC−XX/NCV2951AC*

1.185

1.190

−

1.285

1.270

Feedback Pin Bias Current

I

−

15

40

nA

FB

Error Comparator

Output Leakage Current (V = 30 V)

−

0.01

150

45

1.0

250

−

mA

mV

OH

lkg

Output Low Voltage (V = 4.5 V, I = 400 mA)

V

in

OL

thu

Upper Threshold Voltage (V = 6.0 V)

V

40

−

in

Lower Threshold Voltage (V = 6.0 V)

V

60

95

−

in

thl

Hysteresis (V = 6.0 V)

−

15

in

hy

Shutdown Input

Input Logic Voltage

V

shtdn

V

Logic “0” (Regulator “On”)

Logic “1” (Regulator “Off”)

0

2.0

−

0.7

30

Shutdown Pin Input Current

I

mA

shtdn

V

shtdn

V

shtdn

= 2.4 V

= 30 V

−

35

450

50

600

Regulator Output Current in Shutdown Mode

(V = 30 V, V = 2.0 V, V = 0, Pin 6 Connected to Pin 7)

I

off

−

3.0

10

in

shtdn

O

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. The Junction−to−Ambient Thermal Resistance is determined by PCB copper area per Figure 29.

7. ESD data available upon request.

8. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

9. V

is the part number voltage option.

O(nom)

10.Noise tests on the LP2951 are made with a 0.01 mF capacitor connected across Pins 7 and 1.

*NCV prefix is for automotive and other applications requiring site and change control.

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5

LP2950, LP2951, NCV2951

DEFINITIONS

Dropout Voltage − The input/output voltage differential

Output Noise Voltage − The RMS ac voltage at the

output, with constant load and no input ripple, measured

over a specified frequency range.

at which the regulator output no longer maintains regulation

against further reductions in input voltage. Measured when

the output drops 100 mV below its nominal value (which is

measured at 1.0 V differential), dropout voltage is affected

by junction temperature, load current and minimum input

supply requirements.

Line Regulation − The change in output voltage for a

change in input voltage. The measurement is made under

conditions of low dissipation or by using pulse techniques

such that average chip temperature is not significantly

affected.

Load Regulation − The change in output voltage for a

change in load current at constant chip temperature.

Maximum Power Dissipation − The maximum total

device dissipation for which the regulator will operate

within specifications.

Leakage Current − Current drawn through a bipolar

transistor collector−base junction, under a specified

collector voltage, when the transistor is “off”.

Upper Threshold Voltage − Voltage applied to the

comparator input terminal, below the reference voltage

which is applied to the other comparator input terminal,

which causes the comparator output to change state from a

logic “0” to “1”.

Lower Threshold Voltage − Voltage applied to the

comparator input terminal, below the reference voltage

which is applied to the other comparator input terminal,

which causes the comparator output to change state from a

logic “1” to “0”.

Hysteresis − The difference between Lower Threshold

voltage and Upper Threshold voltage.

Bias Current − Current which is used to operate the

regulator chip and is not delivered to the load.

10

1.0

6.0

LP2951C

T = 25°C

5.0

A

4.0

3.0

2.0

1.0

0

R = 50 kW

L

R = 50 W

L

0.1

0.01

0.1

1.0

10

100

0

1.0

2.0

3.0

4.0

5.0

6.0

I , LOAD CURRENT (mA)

L

V , INPUT VOLTAGE (V)

in

Figure 2. Quiescent Current

Figure 3. 5.0 V Dropout Characteristics over

Load

6.0

5.0

4.0

3.0

2.0

5.00

LP2951C

4.99

4.98

4.97

4.96

4.95

25°C

1.0

0

LP2951C

150

125°C

−40°C

-ꢀ50

0

50

100

200

0

1.0

2.0

3.0

4.0

5.0

6.0

T , AMBIENT TEMPERATURE (°C)

A

V , INPUT VOLTAGE (V)

in

Figure 4. Output Voltage versus Temperature

Figure 5. 5.0 V Dropout Characteristics with

R_L= 50 W

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6

LP2950, LP2951, NCV2951

250

200

150

100

50

400

350

T = 25°C

A

300

0.1 mA Load Current

250

200

150

100

50

No Load

0

0.1

0

1.0

10

100

0

5.0

10

15

20

25

I , OUTPUT CURRENT (mA)

O

V , INPUT VOLTAGE (V)

in

Figure 6. Input Current

Figure 7. Dropout Voltage versus Output Current

5.0

4.0

3.0

2.0

1.0

0

550

55

LP2951C

R = 330 k

T = 25°C

A

L

500

450

400

350

300

50

45

40

35

30

V

in

Decreasing

R = 50

L

V

Increasing

in

R = 50 k

L

-ꢀ50

0

50

T, TEMPERATURE (°C)

100

150

4.70

4.74

4.78

4.82

4.86

4.90

V , INPUT VOLTAGE (V)

in

Figure 8. Dropout Voltage versus Temperature

Figure 9. Error Comparator Output

6.0

5.0

4.0

3.0

2.0

1.0

0

4.0

8.0

7.5

7.0

6.5

6.0

5.5

V

in

C = 1.0 mF

L

2.0

C = 10 mF

L

0

V

out

T = 25°C

L

A

I = 10 mA

-ꢀ2.0

-ꢀ4.0

-ꢀ6.0

V

= 8.0 V

= 5.0 V

in

T = 25°C

A

C = 1.0 mF

V

out

Shutdown Input

L

I = 1.0 mA

L

V

O

= 5.0 V

-1.0

-100

0

100

200

300

400

0

100

200

300

400

500

600

700

800

t, TIME (ms)

Figure 10. Line Transient Response

Figure 11. LP2951 Enable Transient

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7

LP2950, LP2951, NCV2951

200

150

100

50

80

C = 1.0 mF

L

400

V

= 5.0 V

I = 400 mA to 75 mA

out

L

60

T = 25°C

A

200

V

out

I = 0.1 mA

L

0

40

-ꢀ200

-ꢀ400

T = 25°C

L

A

C = 1.0 mF

I

Load

20

0

V

= 6.0 V

= 5.0 V

in

V

out

-ꢀ50

0

0.5

1

1.5

2

2.5

3

3.5

4

1.0

1.0 k

f, FREQUENCY (Hz)

10

100

10 k

100 k

t, TIME (ms)

Figure 12. Load Transient Response

Figure 13. Ripple Rejection

1.8

1.6

4.0

3.0

2.0

1.0

0

I = 100 mA

L

T = 25°C

A

C = 1.0 mF

L

V

= 5.0 V

LP2951C

O

1.4

1.2

Output “Off"

Output “On"

C = 100 mF

L

1.0

0.8

100

1.0 k

-ꢀ40 -ꢀ20

0

20

40

60

80 100 120 140 160

10 k

100 k

f, FREQUENCY (Hz)

t, TEMPERATURE (°C)

Figure 14. Output Noise

Figure 15. Shutdown Threshold Voltage

versus Temperature

10000

1000

100

10

100

4.0

2.0

0

V

= 5 V

out

T = 25°C

A

80

60

40

20

0

T = 75°C

A

Unstable Region

Stable Region

100 mF

0.1 mF

-ꢀ2.0

1

Unstable Region for 0.1 mF capacitor only

-ꢀ4.0

-ꢀ6.0

0.1

LP2951CN

5.0

Lower unstable region is for 0.1 mF only.

1 mF and 100 mF show no instability with low ESR values.

0.01

0

10

15

20

25

30

35

40

0

10 20 30 40 50 60 70 80

Output Current (mA)

90 100

V , INPUT VOLTAGE (V)

in

Figure 16. Maximum Rated

Output Current

Figure 17. Output Stability versus Output Capacitor

Change

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8

LP2950, LP2951, NCV2951

APPLICATIONS INFORMATION

Introduction

to the LP2951 is ramped up and down. The ERROR signal

becomes valid (low) at about 1.3 V input. It goes high when

The LP2950/LP2951 regulators are designed with

internal current limiting and thermal shutdown making them

user−friendly. Typical application circuits for the LP2950

and LP2951 are shown in Figures 20 through 28.

These regulators are not internally compensated and thus

require a 1.0 mF (or greater) capacitance between the

LP2950/LP2951 output terminal and ground for stability.

Most types of aluminum, tantalum or multilayer ceramic

will perform adequately. Solid tantalums or appropriate

multilayer ceramic capacitors are recommended for

operation below 25°C.

At lower values of output current, less output capacitance

is required for output stability. The capacitor can be reduced

to 0.33 mF for currents less than 10 mA, or 0.1 mF for currents

below 1.0 mA. Using the 8 pin versions at voltages less than

5.0 V operates the error amplifier at lower values of gain, so

that more output capacitance is needed for stability. For the

worst case operating condition of a 100 mA load at 1.23 V

output (output Pin 1 connected to the feedback Pin 7)

a minimum capacitance of 3.3 mF is recommended.

The LP2950 will remain stable and in regulation when

operated with no output load. When setting the output

voltage of the LP2951 with external resistors, the resistance

values should be chosen to draw a minimum of 1.0 mA.

the input reaches about 5.0 V (V exceeds about 4.75 V).

out

Since the LP2951’s dropout voltage is dependent upon the

load current (refer to the curve in the Typical Performance

Characteristics), the input voltage trip point will vary with

load current. The output voltage trip point does not vary

with load.

The error comparator output is an open collector which

requires an external pullup resistor. This resistor may be

returned to the output or some other voltage within the

system. The resistance value should be chosen to be

consistent with the 400 mA sink capability of the error

comparator. A value between 100 kW and 1.0 MW is

suggested. No pullup resistance is required if this output is

unused.

When operated in the power down mode (V = 0 V),

in

the error comparator output will go high if it has been pulled

up to an external supply (the output transistor is in high

impedance state). To avoid this invalid response, the error

comparator output should be pulled up to V

(see

out

Figure 18).

5.0 V

4.70 V

4.75 V

Output

Voltage

A

bypass capacitor is recommended across the

LP2950/LP2951 input to ground if more than 4 inches of

wire connects the input to either a battery or power supply

filter capacitor.

Input capacitance at the LP2951 Feedback Pin 7 can

create a pole, causing instability if high value external

resistors are used to set the output voltage. Adding a 100 pF

capacitor between the Output Pin 1 and the Feedback Pin 7

and increasing the output filter capacitor to at least 3.3 mF

will stabilize the feedback loop.

Pullup

to Ext

Not

Valid

Not

Valid

ERROR

Pullup

to V

out

4.75 V + V

dropout

4.70 V + V

dropout

Input

Voltage

1.3 V

Error Detection Comparator

The comparator switches to a positive logic low whenever

the LP2951 output voltage falls more than approximately

5.0% out of regulation. This value is the comparator’s

designed−in offset voltage of 60 mV divided by the 1.235 V

internal reference. As shown in the representative block

diagram. This trip level remains 5.0% below normal

regardless of the value of regulated output voltage. For

example, the error flag trip level is 4.75 V for a normal 5.0 V

regulated output, or 9.50 V for a 10 V output voltage.

Figure 2 is a timing diagram which shows the ERROR

signal and the regulated output voltage as the input voltage

Figure 18. ERROR Output Timing

Programming the Output Voltage (LP2951)

The LP2951CX may be pin−strapped for the nominal

fixed output voltage using its internal voltage divider by

tying Pin 1 (output) to Pin 2 (sense) and Pin 7 (feedback) to

Pin 6 (5.0 V tap). Alternatively, it may be programmed for

any output voltage between its 1.235 reference voltage and

its 30 V maximum rating. An external pair of resistors is

required, as shown in Figure 19.

www.onsemi.com

9

LP2950, LP2951, NCV2951

V

in

for reducing noise on the 3 lead LP2950. However,

increasing the capacitor from 1.0 mF to 220 mF only

decreases the noise from 430 mV to 160 mVrms for a 100 kHz

bandwidth at the 5.0 V output.

Noise can be reduced fourfold by a bypass capacitor

across R1, since it reduces the high frequency gain from 4

to unity. Pick

100 k

5

8

V

in

1

Error

Output

V

out

Error

V

out

1.23 to 30 V

2

NC

SNS

1

C

[

R1

Shutdown

Input

3

Bypass

6

2pR1 x 200 Hz

0.01 mF

SD

V T

O

3.3 mF

or about 0.01 mF. When doing this, the output capacitor must

be increased to 3.3 mF to maintain stability. These changes

reduce the output noise from 430 mV to 126 mVrms for a

100 kHz bandwidth at 5.0 V output. With bypass capacitor

added, noise no longer scales with output voltage so that

improvements are more dramatic at higher output voltages.

GND FB

4

7

R

2

Figure 19. Adjustable Regulator

Unregulated

Input

MTB23P06E

The complete equation for the output voltage is:

1.0 mF

10 k

0.01 mF

(

)

V

+ V

1 ) R1ńR2 ) I

R1

out

ref

FB

V

out

5.0 V 1.0%

0 to 1.0 A

where V is the nominal 1.235 V reference voltage and I

ref

FB

8

is the feedback pin bias current, nominally −20 nA. The

minimum recommended load current of 1.0 mA forces an

upper limit of 1.2 MW on the value of R2, if the regulator

V

in

1

2

5

3

Error

Output

V

Error

out

SNS

LP2951CN

must work with no load. I will produce a 2% typical error

FB

in V which may be eliminated at room temperature by

out

6

Shutdown

Input

SD

V

O

T

220 mF

adjusting R1. For better accuracy, choosing R2 = 100 k

reduces this error to 0.17% while increasing the resistor

program current to 12 mA. Since the LP2951 typically draws

75 mA at no load with Pin 2 open circuited, the extra 12 mA

of current drawn is often a worthwhile tradeoff for

eliminating the need to set output voltage in test.

GND FB

4

7

0.002 mF

1.0 M

2.0 k

Output Noise

In many applications it is desirable to reduce the noise

present at the output. Reducing the regulator bandwidth by

increasing the size of the output capacitor is the only method

Figure 20. 1.0 A Regulator with 1.2 V Dropout

www.onsemi.com

10

LP2950, LP2951, NCV2951

TYPICAL APPLICATIONS

+V = 2.0 to 30 V

I

L

I = 1.23/R

L

Load

Unregulated Input

6.0 to 10 Vdc

8

0.1 mF

8

V

in

1

2

Error

Output

V

5

3

1N4001

330 pF

4.2 V ꢀ0.025 V

in

V

1

2

out

Error

5

Error

V

NC

out

SNS

LP2951CN

SD

2.0 M

1.0%

NC

SNS

LP2951CN

0.1 mF

Shutdown

Input

6

3

6

V

O

T

SD

V

T

O

806 k

1.0%

GND FB

4

Lithium Ion

Rechargeable

Cell

GND FB

4

2.2 mF

7

50 k

1.0 mF

R

GND

Figure 21. Lithium Ion Battery Cell Charger

Figure 22. Low Drift Current Sink

+V

in

+V

in

CMOS

Gate

*Sleep

Input

8

470 k

V

in

1

2

5

3

V

out

Error

2N3906

470 k

Reset

8

47 k

Error

V

out

V

2N3906

NC

in

SNS

LP2951CN

1

2

5

V

out

Error

Output

6

R1

R2

SD

V T

O

NC

SNS

LP2951CN

200 k

100 k

Normally

Closed

GND FB

4

1.0 mF

Shutdown

Input

3

6

3.3 mF

SD

V T

O

7

100 pF

GND FB

4

7

Error flag occurs when V is too

in

100 k

low to maintain V , or if V is re-

out

duced by excessive load current.

Figure 23. Latch Off When Error Flag Occurs

Figure 24. 5.0 V Regulator with 2.5 V Sleep Function

www.onsemi.com

11

LP2950, LP2951, NCV2951

+V

V

in

8

D2

in

1

Memory

V+

5

3

V

out

Error

D1

1.0 mF

2

6

20

3.6 V

NiCad

SNS

LP2951CN

#1

NC

SD

V

O

T

GND FB

4

7

Early Warning

27 k

All diodes are 1N4148.

D3

Reset

Early Warning flag on low input voltage.

Main output latches off at lower input voltages.

Battery backup on auxiliary output.

mP

2.7 M

D4

V

DD

Q1

2N3906

8

330 k

V

in

1

5

3

Operation: Regulator #1’s V is programmed one

diode drop above 5.0 V. Its error flag becomes active

V

out

Error

Main

Output

2

6

when V < 5.7 V. When V drops below 5.3 V, the

in

SNS

error flag of regulator #2 becomes active and via Q1

LP2951CN

#2

latches the main output “off”. When V again exceeds

1.0 mF

in

SD

V

O

T

5.7 V, regulator #1 is back in regulation and the early

warning signal rises, unlatching regulator #2 via D3.

GND FB

4

7

Figure 25. Regulator with Early Warning and Auxiliary Output

+V

in

Current Limit

Section

0.05

470

680

2N3906

1000 mF

2N3906

MJE2955

.33 mF

10 k

4.7 M

8

V

in

1

2

Error

Flag

5

3

V

out

Error

V

out

@ 2.0 A

NC 47

NC

SNS

LP2951CN

220

6

4.7 mF

Tant

SD

V

O

T

100 mF

R1

GND FB

4

20 k

.01 mF

7

R2

0.033 mF

V

out

= 1.25V (1.0 + R1/R2)

For 5.0 V output, use internal resistors. Wire Pin 6 to 7,

and wire Pin 2 to +V Bus.

out

Figure 26. 2.0 A Low Dropout Regulator

www.onsemi.com

12

LP2950, LP2951, NCV2951

+5.0 V

4.7 k

Output*

1

2

5

4

20 mA

NC

8

V

in

1

4

5

3

V

out

Error

2

NC

SNS

LP2951CN

* High for

I < 3.5 mA

6

L

NC

SD

V

O

T

1N4001

0.1 mF

Gnd FB

4

7

1N457

360

Figure 27. Open Circuit Detector for 4.0 to 20 mA Current Loop

31.6 k

6.0 V Lead-Acid

Battery

100 k

2N3906

8

V

in

1

2

5

3

V

Main V+

NC

out

Error

1

MC34164P−5

2

SNS

LP2951CN

Memory V+

3

1.0 mF

6

20

SD

V

O

T

NC

NiCad Backup

Battery

Gnd FB

4

7

NC

Figure 28. Low Battery Disconnect

100

90

80

70

60

50

40

2.4

2.0

1.6

1.2

0.8

0.4

0

P

for T = 50°C

A

D(max)

Free Air

Mounted

Vertically

2.0 oz. Copper

L

Minimum

Size Pad

L

R

q

JA

0

5.0

10

15

20

25

30

L, LENGTH OF COPPER (mm)

Figure 29. DPAK Thermal Resistance and Maximum

Power Dissipation versus PCB Copper Length

www.onsemi.com

13

LP2950, LP2951, NCV2951

ORDERING INFORMATION (LP2950)

Output Voltage

†

(Volts)

Part Number

LP2950CZ−3.0G

Tolerance (%)

Package

Shipping

3.0

1.0

TO−92

(Pb−Free)

2000 Units / Bag

2000 Units / Tape & Reel

2000 Units / Bag

LP2950CZ−3.0RAG

LP2950ACZ−3.0G

LP2950ACZ−3.0RAG

LP2950CZ−3.3G

3.0

3.3

5.0

3.0

3.3

5.0

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

TO−92

(Pb−Free)

TO−92

(Pb−Free)

TO−92

(Pb−Free)

2000 Units / Tape & Reel

2000 Units / Bag

TO−92

(Pb−Free)

LP2950CZ−3.3RAG

LP2950ACZ−3.3G

LP2950ACZ−3.3RAG

LP2950CZ−5.0G

TO−92

(Pb−Free)

2000 Units / Tape & Reel

2000 Units / Bag

TO−92

(Pb−Free)

TO−92

(Pb−Free)

2000 Units / Tape & Reel

2000 Units / Bag

TO−92

(Pb−Free)

LP2950CZ−5.0RAG

LP2950CZ−5.0RPG

LP2950ACZ−5.0G

LP2950ACZ−5.0RAG

LP2950CDT−3.0G

LP2950CDT−3.0RKG

LP2950ACDT−3.0G

LP2950ACDT−3RKG

LP2950CDT−3.3G

LP2950CDT−3.3RKG

LP2950ACDT−3.3RG

LP2950CDT−5.0G

LP2950CDT−5.0RKG

LP2950ACDT−5.0G

LP2950ACDT−5RKG

TO−92

(Pb−Free)

2000 Units / Tape & Reel

2000 Units / Ammo Pack

2000 Units / Bag

TO−92

(Pb−Free)

TO−92

(Pb−Free)

TO−92

(Pb−Free)

2000 Units / Tape & Reel

75 Units / Rail

DPAK

(Pb−Free)

DPAK

(Pb−Free)

2500 Units / Tape & Reel

75 Units / Rail

DPAK

(Pb−Free)

DPAK

(Pb−Free)

2500 Units / Tape & Reel

75 Units / Rail

DPAK

(Pb−Free)

DPAK

(Pb−Free)

2500 Units / Tape & Reel

75 Units / Rail

DPAK

(Pb−Free)

DPAK

(Pb−Free)

DPAK

(Pb−Free)

2500 Units / Tape & Reel

75 Units / Rail

DPAK

(Pb−Free)

DPAK

2500 Units / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

14

LP2950, LP2951, NCV2951

ORDERING INFORMATION (LP2951)

Output Voltage

†

(Volts)

Part Number

LP2951CD−3.0G

Tolerance (%)

Package

Shipping

3.0

1.0

SOIC−8

(Pb−Free)

98 Units / Rail

2500 Units / Tape & Reel

98 Units / Rail

LP2951CD−3.0R2G

LP2951ACD−3.0G

LP2951ACD−3.0R2G

LP2951CD−3.3G

LP2951CD−3.3R2G

LP2951ACD−3.3G

LP2951ACD−3.3R2G

LP2951CDG

3.0

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

1.0

0.5

SOIC−8

(Pb−Free)

SOIC−8

(Pb−Free)

3.0

SOIC−8

(Pb−Free)

2500 Units / Tape & Reel

98 Units / Rail

3.3

SOIC−8

(Pb−Free)

3.3

SOIC−8

(Pb−Free)

2500 Units / Tape & Reel

98 Units / Rail

3.3

SOIC−8

(Pb−Free)

3.3

SOIC−8

(Pb−Free)

2500 Units / Tape & Reel

98 Units / Rail

5.0 or Adj.

3.0

SOIC−8

(Pb−Free)

LP2951CDR2G

SOIC−8

(Pb−Free)

2500 Units / Tape & Reel

98 Units / Rail

LP2951ACDG

SOIC−8

(Pb−Free)

LP2951ACDR2G

LP2951CDM−3.0R2G

LP2951ACDM−3.0RG

LP2951CDM−3.3R2G

LP2951ACDM−3.3RG

LP2951CDMR2G

LP2951ACDMR2G

LP2951ACN−3.0G

LP2951CN−3.3G

LP2951ACN−3.3G

LP2951CNG

SOIC−8

(Pb−Free)

2500 Units / Tape & Reel

4000 Units / Tape & Reel

50 Units / Rail

Micro8

(Pb−Free)

3.0

Micro8

(Pb−Free)

3.3

Micro8

(Pb−Free)

3.3

Micro8

(Pb−Free)

5.0 or Adj.

3.0

Micro8

(Pb−Free)

Micro8

(Pb−Free)

PDIP−8

(Pb−Free)

3.3

PDIP−8

(Pb−Free)

50 Units / Rail

3.3

PDIP−8

(Pb−Free)

50 Units / Rail

5.0 or Adj.

PDIP−8

(Pb−Free)

50 Units / Rail

LP2951ACNG

PDIP−8

50 Units / Rail

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

15

LP2950, LP2951, NCV2951

ORDERING INFORMATION (NCV2951)

Output Voltage

†

(Volts)

Part Number

Tolerance (%)

Package

Shipping

NCV2951ACD3.3R2G*

3.3

0.5

SOIC−8

(Pb−Free)

2500 Units / Tape & Reel

4000 Units / Tape & Reel

NCV2951ACDR2G*

NCV2951CDR2G*

NCV2951ACDMR2G*

5.0 or Adj.

0.5

1.0

0.5

SOIC−8

(Pb−Free)

SOIC−8

(Pb−Free)

Micro8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

www.onsemi.com

16

LP2950, LP2951, NCV2951

MARKING DIAGRAMS

TO−92

CASE 029

DPAK

CASE 369C

2950

2950A

CZ−xx

ALYWG

G

50−yG

ALYWW

50−yyG

ALYWW

50A−yG

ALYWW

50AyyG

ALYWW

CZ−xx

ALYWG

G

SOIC−8

CASE 751

8

1

8

1

8

*

51z

ALYW

G

51z−33

ALYW

G

51z−3

ALYW

G

1

PDIP−8

Micro8

CASE 626

CASE 846A

8

1

8

1

8

1

8

51CN

AWL

YYWWG

51ACN

AWL

YYWWG

51CN−xx

AWL

YYWWG

51ACN−xx

AWL

YYWWG

PAyy

P−yy

AYWG

G

AYWG

G

1

xx

y

= 3.0, 3.3, or 5.0

= 3 or 5

yy

z

= 30, 33, or 50

= A or C

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G

= Pb−Free Package

G

(Note: Microdot may be in either location)

*This marking diagram also applies to NCV2951.

www.onsemi.com

17

LP2950, LP2951, NCV2951

PACKAGE DIMENSIONS

TO−226AA/TO−92

Z SUFFIX

CASE 29−11

ISSUE AM

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.

A

STRAIGHT LEAD

BULK PACK

B

R

4. LEAD DIMENSION IS UNCONTROLLED IN P AND

BEYOND DIMENSION K MINIMUM.

P

L

INCHES

DIM MIN MAX

MILLIMETERS

SEATING

PLANE

K

MIN

4.45

4.32

3.18

0.407

1.15

2.42

0.39

12.70

6.35

2.04

---

MAX

5.20

5.33

4.19

0.533

1.39

2.66

0.50

---

A

B

C

D

G

H

J

0.175

0.170

0.125

0.016

0.045

0.095

0.015

0.500

0.250

0.080

---

0.205

0.210

0.165

0.021

0.055

0.105

0.020

---

D

X X

G

J

H

V

K

L

---

N

P

R

V

0.105

0.100

---

2.66

2.54

---

C

SECTION X−X

0.115

0.135

2.93

3.43

1

N

---

N

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. CONTOUR OF PACKAGE BEYOND

DIMENSION R IS UNCONTROLLED.

A

BENT LEAD

TAPE & REEL

AMMO PACK

B

R

4. LEAD DIMENSION IS UNCONTROLLED IN P

AND BEYOND DIMENSION K MINIMUM.

P

T

SEATING

PLANE

MILLIMETERS

DIM MIN

MAX

5.20

5.33

4.19

0.54

2.80

0.50

---

K

A

B

C

D

G

J

4.45

4.32

3.18

0.40

2.40

0.39

12.70

2.04

1.50

2.93

3.43

D

X X

G

K

N

P

R

V

J

2.66

4.00

---

V

C

---

SECTION X−X

1

N

www.onsemi.com

18

LP2950, LP2951, NCV2951

PACKAGE DIMENSIONS

DPAK (SINGLE GAUGE)

CASE 369C

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-

MENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL

NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM

PLANE H.

A

D

E

C

c2

A

b3

B

4

2

L3

L4

Z

DETAIL A

H

1

3

7. OPTIONAL MOLD FEATURE.

INCHES

DIM MIN MAX

0.086 0.094

A1 0.000 0.005

0.025 0.035

MILLIMETERS

NOTE 7

MIN

2.18

0.00

0.63

0.72

4.57

0.46

5.97

6.35

2.29 BSC

9.40 10.41

1.40 1.78

2.90 REF

0.51 BSC

0.89 1.27

MAX

2.38

0.13

0.89

1.14

5.46

0.61

6.22

6.73

c

b2

e

BOTTOM VIEW

A

SIDE VIEW

b

b2 0.028 0.045

b3 0.180 0.215

M

0.005 (0.13)

C

TOP VIEW

c

0.018 0.024

c2 0.018 0.024

Z

D

E

e

0.235 0.245

0.250 0.265

0.090 BSC

H

GAUGE

PLANE

SEATING

PLANE

H

L

L1

L2

0.370 0.410

0.055 0.070

0.114 REF

L2

C

0.020 BSC

L3 0.035 0.050

L

BOTTOM VIEW

A1

L4

Z

−−− 0.040

0.155 −−−

−−−

3.93

1.01

−−−

L1

ALTERNATE

CONSTRUCTIONS

DETAIL A

ROTATED 905 CW

SOLDERING FOOTPRINT*

6.20

0.244

3.00

0.118

2.58

0.102

5.80

0.228

1.60

0.063

6.17

0.243

mm

inches

ǒ

Ǔ

SCALE 3:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

19

LP2950, LP2951, NCV2951

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

B

0.25 (0.010)

Y

1

K

−Y−

MILLIMETERS

DIM MIN MAX

INCHES

G

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

1.27 BSC

0.050 BSC

−Z−

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

0.10 (0.004)

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

SOLDERING FOOTPRINT*

1.52

0.060

7.0

4.0

0.275

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

20

LP2950, LP2951, NCV2951

PACKAGE DIMENSIONS

PDIP−8

CASE 626−05

ISSUE P

SCALE 1:1

NOTES:

D

A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

E

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-

AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.

4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE

NOT TO EXCEED 0.10 INCH.

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM

PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR

TO DATUM C.

H

8

5

4

E1

1

6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE

LEADS UNCONSTRAINED.

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE

LEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE

CORNERS).

NOTE 8

c

b2

B

END VIEW

WITH LEADS CONSTRAINED

NOTE 5

TOP VIEW

INCHES

DIM MIN MAX

−−−−

A1 0.015

MILLIMETERS

A2

MIN

−−−

0.38

2.92

0.35

MAX

5.33

−−−

4.95

0.56

e/2

A

0.210

−−−−

A

NOTE 3

A2 0.115 0.195

L

b

b2

C

0.014 0.022

0.060 TYP

0.008 0.014

0.355 0.400

1.52 TYP

0.20

9.02

0.13

7.62

6.10

0.36

10.16

−−−

8.26

7.11

D

SEATING

PLANE

D1 0.005

0.300 0.325

E1 0.240 0.280

−−−−

A1

D1

E

C

M

e

eB

L

0.100 BSC

−−−− 0.430

0.115 0.150

−−−− 10°

2.54 BSC

−−−

2.92

−−−

10.92

3.81

10 °

e

eB

8X

b

END VIEW

M

NOTE 6

M

B

0.010

C A

SIDE VIEW

www.onsemi.com

21

LP2950, LP2951, NCV2951

PACKAGE DIMENSIONS

Micro8t

CASE 846A−02

ISSUE J

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.

H

E

MILLIMETERS

INCHES

NOM

−−

0.003

0.013

0.007

0.118

DIM

A

A1

b

c

D

MIN

−−

NOM

−−

MAX

MIN

−−

MAX

0.043

0.006

0.016

0.009

0.122

PIN 1 ID

e

1.10

0.15

0.40

0.23

3.10

b 8 PL

0.05

0.25

0.13

2.90

0.08

0.002

0.010

0.005

0.114

0.33

M

S

0.08 (0.003)

T

B

A

0.18

3.00

E

3.00

0.118

e

L

H

E

0.65 BSC

0.55

4.90

0.026 BSC

0.021

0.193

SEATING

PLANE

0.40

4.75

0.70

5.05

0.016

0.187

0.028

0.199

−T−

A

0.038 (0.0015)

L

A1

c

RECOMMENDED

SOLDERING FOOTPRINT*

8X

0.48

0.80

5.25

0.65

PITCH

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Micro8 is a trademark of International Rectifier.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage

may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer

is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of

any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and

do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized

for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices

intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and

hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was

negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright

laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

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Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

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For additional information, please contact your local

Sales Representative

◊

LP2950/D

www.onsemi.com

22

型号:	NCV2951ACDR2G
Brand Name：	ON Semiconductor
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
制造商包装代码：	751-07
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.44
可调性：	FIXED/ADJUSTABLE
最大回动电压 1：	0.45 V
标称回动电压 1：	0.35 V
最大绝对输入电压：	30 V
最大差分输入-输出电压：	28.75 V
最小差分输入-输出电压：	1 V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
最大电网调整率：	0.005%
最大负载调整率：	0.005%
湿度敏感等级：	1
功能数量：	1
输出次数：	1
端子数量：	8
工作温度TJ-Max：	150 °C
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流 1：	0.1 A
最大输出电压 1：	29 V
最小输出电压 1：	1.25 V
标称输出电压 1：	5 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TR
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
调节器类型：	FIXED/ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR
筛选级别：	AEC-Q100
座面最大高度：	1.75 mm
子类别：	Other Regulators
表面贴装：	YES
技术：	BIPOLAR
端子面层：	Tin (Sn)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
最大电压容差：	1.5%
宽度：	3.9 mm
Base Number Matches：	1

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