NCV4269D1应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

NCV4269

5.0 V Micropower 150 mA

LDO Linear Regulator with

DELAY, Adjustable RESET,

and Sense Output

The NCV4269 is a 5.0 V precision micropower voltage regulator

with an output current capability of 150 mA.

The output voltage is accurate within 2.0% with a maximum

dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature

drawing only 240 mA with a 1.0 mA load. This part is ideal for any and

all battery operated microprocessor equipment.

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MARKING DIAGRAMS

8

4269

ALYW

1

Microprocessor control logic includes an active reset output RO

with delay and a SI/SO monitor which can be used to provide an early

warning signal to the microprocessor of a potential impending reset

signal. The use of the SI/SO monitor allows the microprocessor to

finish any signal processing before the reset shuts the microprocessor

down.

The active Reset circuit operates correctly at an output voltage as

low as 1.0 V. The Reset function is activated during the power up

sequence or during normal operation if the output voltage drops

outside the regulation limits.

SO−8

D SUFFIX

CASE 751

1

14

NCV4269

AWLYWW

1

The reset threshold voltage can be decreased by the connection of an

SO−14

D SUFFIX

CASE 751A

external resistor divider to the R

lead. The regulator is protected

ADJ

against reverse battery, short circuit, and thermal overload conditions.

The device can withstand load dump transients making it suitable for

use in automotive environments. The device has also been optimized

for EMC conditions.

20

Features

20

• 5.0 V 2.0% Output

• Low 240 mA Quiescent Current

NCV4269

AWLYYWW

1

• Active Reset Output Low Down to V = 1.0 V

Q

SO−20L

DW SUFFIX

CASE 751D

• Adjustable Reset Threshold

1

• 150 mA Output Current Capability

• Fault Protection

♦ +45 V Peak Transient Voltage

♦ −40 V Reverse Voltage

♦ Short Circuit

A

= Assembly Location

= Year

WL, L = Wafer Lot

YY, Y

WW, W = Work Week

♦ Thermal Overload

• Early Warning through SI/SO Leads

• Internally Fused Leads in SO−14 and SO−20L Packages

• Integrated Pullup Resistor at Logic Outputs (To Use External

Resistors, Select the NCV4279)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

• Very Low Dropout Voltage

• Electrical Parameters Guaranteed Over Entire Temperature Range

• NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes



Semiconductor Components Industries, LLC, 2004

1

Publication Order Number:

November, 2004 − Rev. 5

NCV4269/D

NCV4269

I

Q

Error

Amplifier

Current and

Reference

and Trim

R

SO

Saturation

Control

R

RO

D

or

Reference

SO

R

ADJ

+

−

SI

GND

Figure 1. Block Diagram

PIN CONNECTIONS

1

20

R

SI

ADJ

D

NC

1

14

I

R

ADJ

SI

1

8

NC

D

I

Q

GND

NC

Q

GND

RO

GND

Q

SI

SO

GND

R

ADJ

RO

D

GND

NC

RO

SO

SO−8

SO−14

SO−20L

PACKAGE PIN DESCRIPTION

Package Pin Number

SO−8

SO−14

SO−20L

Pin Symbol

Function

Reset Threshold Adjust; if not used to connect to GND.

3

4

5

1

2

1

2

R

ADJ

D

Reset Delay; To Set Time Delay, Connect to GND with Capacitor

Ground

3, 4, 5, 6,

10, 11, 12

4, 5, 6, 7, 14,

15, 16, 17

GND

−

3, 8, 9, 13, 18

10

NC

RO

No connection to these pins from the IC.

6

7

Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor to

Q. Leave Open if Not Used.

7

8

11

SO

Sense Output; This Open−Collector Output is Internally Pulled Up by

20 kW pullup resistor to Q. If not used, keep open.

8

1

2

9

12

19

20

Q

I

5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.

Input; Connect to GND Directly at the IC with a Ceramic Capacitor.

Sense Input; If not used, Connect to Q.

13

14

SI

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2

NCV4269

MAXIMUM RATINGS (T = −40°C to 150°C)

J

Parameter

Symbol

Min

Max

Unit

Input to Regulator

V

I

−40

45

V

I

Internally Limited Internally Limited

Sense Input

V

SI

−40

−1

45

1

V

mA

SI

I

Reset Threshold Adjust

Reset Delay

V

−0.3

−10

7

V

RADJ

I

10

mA

V

I

−0.3

7

V

D

Internally Limited Internally Limited

D

Ground

I

50

−

mA

V

q

Reset Output

V

RO

−0.3

7

I

Internally Limited Internally Limited

Sense Output

V

−0.3

7

V

SO

I

Internally Limited Internally Limited

Regulated Output

V

Q

−0.5

−10

7.0

−

V

mA

Q

I

Junction Temperature

Storage Temperature

T

STG

−

−50

150

°C

J

T

Input Voltage Operating Range

Junction Temperature Operating Range

V

J

−

−40

45

150

V

°C

I

T

Junction−to−Ambient Thermal Resistance

SO−8

SO−14

R

−

200

70

k/W

q

JA

JP

SO−20L

70

Junction−to−Pin 4, all GND Pins Grounded.

SO−14

SO−20L

R

q

−

30

k/W

Lead Temperature Soldering and MSL

Parameter

Symbol

MSL

Value

MSL, 20−Lead LS Temperature 260°C Peak (Note 3)

MSL, 20−Lead, LS Temperature 230°C Peak (Note 4)

MSL, 8−Lead, 14−Lead, LS Temperature 260°C Peak (Note 3)

3

1

MSL

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

1. This device series incorporates ESD protection and exceeds the following ratings:

Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114.

Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115.

2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78.

3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.

4. +5°C/−0°C, 30 Sec Max−at−Peak, 60 − 150 Sec above 183°C.

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3

NCV4269

ELECTRICAL CHARACTERISTICS (T = −40°C ≤ T ≤ 125°C, V = 13.5 V unless otherwise specified)

J

I

Characteristic

REGULATOR

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Voltage

Current Limit

V

1 mA v I v 100 mA 6 V v V v 16 V

4.90

150

−

5.00

200

240

250

2.0

5.10

500

250

450

3.0

0.5

20

V

Q

I

−

mA

V

Q

Current Consumption; I = I – I

I

Q

= 1 mA, RO, SO High

= 10 mA, RO, SO High

= 50 mA, RO, SO High

q

I

Q

q

Current Consumption; I = I – I

I

−

q

I

Q

Current Consumption; I = I – I

−

q

I

Dropout Voltage

Load Regulation

Line Regulation

V

V = 5 V, I = 100 mA

−

0.25

10

dr

I

Q

D

I

= 5 mA to 100 mA

−

mV

VQ

Q

V = 6 V to 26 V I = 1 mA

−

10

30

I

Q

RESET GENERATOR

Reset Switching Threshold

V

−

4.50

1.26

10

−

4.65

1.35

20

4.80

1.44

40

V

RT

Reset Adjust Switching Threshold

Reset Pullup Resistance

Reset Output Saturation Voltage

Upper Delay Switching Threshold

Lower Delay Switching Threshold

Saturation Voltage on Delay Capacitor

Charge Current

V

> 3.5 V

Q

RAD,JTH

R

−

kW

V

SO,INT

V

< V , R

0.1

1.8

0.45

−

0.4

2.2

0.60

0.1

9.5

−

RO,SAT

Q

RT RO, INT

V

−

1.4

0.3

−

V

UD

V

−

V

LD

V

< V

RT

V

D,SAT

Q

I

V

= 1 V

D

3.0

17

−

6.5

28

mA

ms

D

Delay Time L ³ H

t

C

D

C

D

= 100 nF

d

Delay Time H ³ L

t

1.0

−

t

INPUT VOLTAGE SENSE

Sense Threshold High

V , High

−

1.24

1.16

−

1.31

1.20

0.1

1.38

1.28

0.4

V

SI

Sense Threshold Low

V , Low

SI

Sense Output Saturation Voltage

Sense Resistor Pullup

V

, Low

SO

V

< 1.20 V; V > 3 V; R

V

SI

Q

SO

R

SO,INT

−

10

20

40

kW

mA

Sense Input Current

I

−1.0

0.1

1.0

SI

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4

NCV4269

I

Q

I

Q

C

I

C

Q

22 mF

RADJ1

1000 mF

470 nF

I

RADJ

SI

RADJ

V

Q

D

GND

RO

SO

V

I

V

SO

D

q

RO

V

SI

V

RADJ

V

D

C

D

RADJ2

100 nF

Figure 2. Measuring Circuit

V

I

t

< t

RR

V

Q

V

RT

t

dV

dt

I

D

C

D

V

+

D

V

UD

V

LD

t

RR

t

d

V

RO

V

ROSAT

t

Power−on−Reset

Thermal

Shutdown

Voltage Dip

at Input

Undervoltage

Secondary Overload

Spike at Output

Figure 3. Reset Timing Diagram

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5

NCV4269

Sense Input Voltage

V

SLHIGH

V

SLLOW

t

Sense Output Voltage

t

PDSOLH

PDSOHL

HIGH

LOW

t

Figure 4. Sense Timing Diagram

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6

NCV4269

APPLICATION DESCRIPTION

OUTPUT REGULATOR

If the reset adjust option is not needed, the R

ADJ

The output is controlled by a precision trimmed reference.

The PNP output has base drive quiescent current control for

regulation while the input voltage is low, preventing over

saturation. Current limit and voltage monitors complement

the regulator design to give safe operating signals to the

processor and control circuits.

should be connected to GND causing the reset threshold to

go to its default value (typically 4.65 V).

RESET DELAY (D)

The reset delay circuit provides a delay (programmable by

capacitor C ) on the reset output lead RO. The delay lead D

D

provides charge current I (typically 6.5 mA) to the external

D

RESET OUTPUT (RO)

A reset signal, Reset Output, RO, (low voltage) is

delay capacitor C during the following times:

D

1. During Powerup (once the regulation threshold has

been exceeded).

2. After a reset event has occurred and the device is

back in regulation. The delay capacitor is set to

generated as the IC powers up. After the output voltage V

Q

increases above the reset threshold voltage V , the delay

RT

timer D is started. When the voltage on the delay timer V

D

passes V , the reset signal RO goes high. A discharge of

UD

discharge when the regulation (V , reset

RT

the delay timer V is started when V drops and stays below

D

Q

threshold voltage) has been violated. When the

the reset threshold voltage V . When the voltage of the

RT

delay capacitor discharges to V , the reset signal

LD

delay timer V drops below the lower threshold voltage V

D

LD

RO pulls low.

the reset output voltage V is brought low to reset the

RO

SETTING THE DELAY TIME

processor.

The delay time is set by the delay capacitor C and the

D

The reset output RO is an open collector NPN transistor

with an internal 20 kW pullup resistor connected to the

output Q, controlled by a low voltage detection circuit. The

circuit is functionally independent of the rest of the IC,

charge current I . The time is measured by the delay

D

capacitor voltage charging from the low level of V

to

DSAT

the higher level V . The time delay follows the equation:

UD

(eq. 2)

t

d

+ [C (V

* V

)]ńI

DSAT D

thereby guaranteeing that RO is valid for V as low as 1.0 V.

D

UD

Q

Example:

Using C = 100 nF.

RESET ADJUST (R_ADJ

The reset threshold V can be decreased from a typical

)

D

RT

Use the typical value for V

= 0.1 V.

value of 4.65 V to as low as 3.5 V by using an external

voltage divider connected from the Q lead to the pin RADJ,

as shown in Figure 5. The resistor divider keeps the voltage

DSAT

Use the typical value for V = 1.8 V.

UD

Use the typical value for Delay Charge Current I = 6.5 mA.

D

above the V

(typical 1.35 V) for the desired input

RADJ,TH

(eq. 3)

+ [100 nF(1.8 * 0.1 V)]ń6.5 mA + 26.2 ms

t

d

voltages, and overrides the internal threshold detector.

Adjust the voltage divider according to the following

relationship:

V

RT

+ V

@ (R

) R )ńR

ADJ2 ADJ2

(eq. 1)

RADJ, TH

ADJ1

V

I

BAT

Q

V

DD

C **

10 mF

R

Q

ADJ1

C *

0.1 mF

I

R

ADJ

ADJ2

NCV4269

R

SI1

D

SI

SI2

C

D

RO

I/O

SO

I/O

GND

*C required if regulator is located far from the power supply filter.

I

** C required for Stability. Cap must operate at minimum temperature expected.

Q

Figure 5. Application Diagram

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7

NCV4269

SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE

MONITOR

instability. The aluminum electrolytic capacitor is the least

expensive solution, but, if the circuit operates at low

temperatures (−25°C to −40°C), both the value and ESR of

the capacitor will vary considerably. The capacitor

manufacturer’s data sheet usually provides this information.

An on−chip comparator is available to provide early

warning to the microprocessor of a possible reset signal. The

output is from an open collector driver with an internal

20 kW pull up resistor to output Q. The reset signal typically

turns the microprocessor off instantaneously. This can cause

unpredictable results with the microprocessor. The signal

received from the SO pin will allow the microprocessor time

to complete its present task before shutting down. This

function is performed by a comparator referenced to the

band gap voltage. The actual trip point can be programmed

externally using a resistor divider to the input monitor SI

The value for the output capacitor C shown in Figure 5

Q

should work for most applications; however, it is not

necessarily the optimized solution. Stability is guaranteed at

values C = 10 mF and an ESR = 10 W within the operating

Q

temperature range. Actual limits are shown in a graph in the

typical data section.

CALCULATING POWER DISSIPATION IN A SINGLE

OUTPUT LINEAR REGULATOR

The maximum power dissipation for a single output

regulator (Figure 5) is:

(Figure 5). The values for R and R are selected for a

SI1

SI2

typical threshold of 1.20 V on the SI Pin.

SIGNAL OUTPUT

Figure 6 shows the SO Monitor timing waveforms as a

result of the circuit depicted in Figure 5. As the output

P

+ [V

I(max)

) V

]I

) V

I

(eq. 4)

D(max)

Q(min) Q(max)

I(max) q

where:

V

I(max)

is the maximum input voltage,

voltage (V ) falls, the monitor threshold (V

), is

Q

SILOW

V

Q(min)

is the minimum output voltage,

crossed. This causes the voltage on the SO output to go low

sending a warning signal to the microprocessor that a reset

I

is the maximum output current for the application,

Q(max)

and I is the quiescent current the regulator consumes at

signal may occur in a short period of time. T

is the

q

WARNING

I

.

time the microprocessor has to complete the function it is

currently working on and get ready for the reset

shutdown signal.

Q(max)

Once the value of P

is known, the maximum

D(max)

permissible value of R

can be calculated:

qJA

= (150°C – T ) / P

D

R

q

JA

(eq. 5)

A

V

Q

The value of R

can then be compared with those in the

qJA

package section of the data sheet. Those packages with

R

’s less than the calculated value in equation 2 will keep

qJA

SI

the die temperature below 150°C. In some cases, none of the

packages will be sufficient to dissipate the heat generated by

the IC, and an external heatsink will be required. The current

V

SILOW

flow

and

voltages

are

shown

in

the

V

RO

Measurement Circuit Diagram.

HEATSINKS

A heatsink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

SO

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed to

T

WARNING

Figure 6. SO Warning Waveform Time Diagram

determine the value of R

:

qJA

R

qJA

+ R

) R ) R

qCS qSA

(eq. 6)

qJC

STABILITY CONSIDERATIONS

The input capacitor C in Figure 5 is necessary for

where:

I

compensating input line reactance. Possible oscillations

caused by input inductance and input capacitance can be

damped by using a resistor of approximately 1.0 W in series

R

= the junction−to−case thermal resistance,

qJC

= the case−to−heat sink thermal resistance, and

= the heat sink−to−ambient thermal resistance.

appears in the package section of the data sheet. Like

qCS

qSA

R

with C

I.

qJC

The output or compensation capacitor helps determine

three main characteristics of a linear regulator: startup delay,

load transient response and loop stability.

The capacitor value and type should be based on cost,

availability, size and temperature constraints. A tantalum or

aluminum electrolytic capacitor is best, since a film or

ceramic capacitor with almost zero ESR can cause

R

, it too is a function of package type. R

and R

are

qJA

qCS

qSA

functions of the package type, heatsink and the interface

between them. These values appear in data sheets of

heatsink manufacturers. Thermal, mounting, and

heatsinking considerations are discussed in the

ON Semiconductor application note AN1040/D, available

on the ON Semiconductor website.

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8

NCV4269

ORDERING INFORMATION

Device

Output Voltage

Package

Shipping

NCV4269D1

98 Units/Rail

SO−8

NCV4269D1R2

NCV4269D2

2500 Tape & Reel

55 Units/Rail

5.0 V

SO−14

NCV4269D2R2

NCV4269DW

2500 Tape & Reel

38 Units/Rail

SO−20L

NCV4269DWR2

1000 Tape & Reel

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9

NCV4269

PACKAGE DIMENSIONS

SO−8

D SUFFIX

CASE 751−07

ISSUE AD

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

B

0.25 (0.010)

Y

1

K

−Y−

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

−Z−

1.27 BSC

0.050 BSC

0.10 (0.004)

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

RECOMMENDED FOOTPRINT

1.52

0.060

7.0

0.275

4.0

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

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10

NCV4269

PACKAGE DIMENSIONS

SO−14

D SUFFIX

CASE 751A−03

ISSUE G

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

14

8

7

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

−B−

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

P 7 PL

M

B

0.25 (0.010)

1

MILLIMETERS

INCHES

MIN

G

DIM MIN

MAX

8.75

4.00

1.75

0.49

1.25

MAX

0.344

0.157

0.068

0.019

0.049

F

R X 45

_

C

A

B

C

D

F

8.55

3.80

1.35

0.35

0.40

0.337

0.150

0.054

0.014

0.016

−T−

SEATING

PLANE

J

M

G

J

1.27 BSC

0.050 BSC

K

D 14 PL

0.19

0.10

0

0.25

7

0.008

0.004

0

0.009

7

M

S

0.25 (0.010)

T

B

A

K

M

P

R

_

5.80

0.25

6.20

0.50

0.228

0.010

0.244

0.019

SO−20L

DW SUFFIX

CASE 751D−05

ISSUE G

D

A

q

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

20

11

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

E

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

1

10

MILLIMETERS

B

DIM MIN

MAX

2.65

0.25

0.49

0.32

12.95

7.60

20X B

A

A1

B

C

D

E

2.35

0.10

0.35

0.23

12.65

7.40

M

S

B

T

0.25

A

e

1.27 BSC

H

h

10.05

0.25

0.50

0

10.55

0.75

0.90

7

SEATING

PLANE

L

^18Xe

q

_

A1

C

T

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11

NCV4269

SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC).

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

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