NCV8501 Series
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV8501 contains the microprocessor compatible
control function RESET (Figure 13).
The DELAY lead provides source current (typically 2.5 mA)
to the external DELAY capacitor during the following
proceedings:
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
V
IN
RESET
V
OUT
Threshold
DELAY
RESET
DELAY
Threshold
(V
)
DT
FLAG/Monitor Function
T
T
d
d
An on−chip comparator is provided to perform an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap reference. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 15). The typical
threshold is 1.20 V on the MON pin.
Figure 13. Reset and Delay Circuit Wave Forms
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V is within 6.0% of the regulated output
OUT
voltage, or when V
drops out of regulation,and is lower
OUT
than 8.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for V
as 1.0 V.
as low
OUT
V
BAT
V
OUT
V
CC
V
IN
mP
ENABLE Function
NCV8501
C
OUT
The part stays in a low I sleep mode when the ENABLE
I/O
Q
MON
FLAG
pin is held low. The part has an internal pull down if the pin
is left floating. This is intended for failure modes only. An
external connection (active pulldown, resistor, or switch) for
normal operation is recommended.
R
RESET
ADJ
RESET
GND
DELAY
The integrity of the ENABLE pin allows it to be tied
directly to the battery line through an external resistor. It will
withstand load dump potentials in this configuration.
Figure 15. FLAG/Monitor Function
Voltage Adjust
Figure 16 shows the device setup for a user configurable
output voltage. The feedback to the V pin is taken from
V
BAT
V
OUT
V
IN
ADJ
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.28 V
typical).
NCV8501
10 k
ENABLE
GND
≈5.0 V
V
OUT
C
OUT
15 k
NCV8501
Figure 14. ENABLE Function
V
ADJ
1.28 V
5.1 k
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
Figure 16. Adjustable Output Voltage
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