NTHS5445T1原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

NTHS5445T1

Power MOSFET

P−Channel ChipFETE

5.2 Amps, 8 Volts

Features

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• Low R

for Higher Efficiency

DS(on)

• Logic Level Gate Drive

• Miniature ChipFET Surface Mount Package Saves Board Space

5.2 AMPS

8 VOLTS

Applications

• Power Management in Portable and Battery−Powered Products; i.e.,

Cellular and Cordless Telephones and PCMCIA Cards

R_DS(on)= 35 mW

S

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

A

G

Steady

State

Rating

Symbol

5 secs

−8.0

"8.0

Unit

V

Drain−Source Voltage

Gate−Source Voltage

Continuous Drain Current

V

DS

V

GS

V

D

I

D

A

P−Channel MOSFET

(T = 150°C) (Note 1.)

J

T = 25°C

T = 85°C

A

"7.1

"5.2

"3.7

A

Pulsed Drain Current

I

"20

A

DM

Continuous Source Current

(Note 1.)

I

S

−2.1

−1.1

Maximum Power Dissipation

(Note 1.)

P

D

W

ChipFET

CASE 1206A

STYLE 1

T = 25°C

2.5

1.3

0.7

A

T = 85°C

A

Operating Junction and Storage

Temperature Range

T , T

−55 to +150

°C

J

stg

MARKING

DIAGRAM

1. Surface Mounted on 1″ x 1″ FR4 Board.

PIN CONNECTIONS

8

7

6

5

1

2

3

4

D

G

1

2

3

4

8

7

6

5

D

S

A5 = Specific Device Code

ORDERING INFORMATION

Device

Package

Shipping

3000/Tape & Reel

NTHS5445T1

ChipFET

1

Publication Order Number:

February, 2005 − Rev. XXX

NTHS5445T1/D

NTHS5445T1

THERMAL CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Maximum Junction−to−Ambient (Note 2.)

R

°C/W

thJA

t v 5 sec

Steady State

40

80

50

95

Maximum Junction−to−Foot (Drain)

R

15

20

°C/W

thJF

Steady State

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

J

Characteristic

Symbol

Test Condition

Min

Typ

Max

Unit

Static

Gate Threshold Voltage

V

= V , I = −250 µA

−0.45

−

V

GS(th)

DS

GS

D

Gate−Body Leakage

I

V

DS

= 0 V, V = "8.0 V

−

"100

−1.0

−5.0

nA

µA

GSS

GS

Zero Gate Voltage Drain Current

I

V

= −6.4 V, V = 0 V

GS

DSS

DS

V

= −6.4 V, V = 0 V,

GS

T = 85°C

J

On−State Drain Current (Note 3.)

I

V

v −5.0 V, V = −4.5 V

−20

−

A

D(on)

DS

GS

Drain−Source On−State Resistance (Note 3.)

r

V

= −4.5 V, I = −5.2 A

0.030

0.040

0.052

18

0.035

0.047

0.062

−

Ω

DS(on)

GS

DS

D

= −2.5 V, I = −4.5 A

−

D

= −1.8 V, I = −2.0 A

−

D

Forward Transconductance (Note 3.)

Diode Forward Voltage (Note 3.)

g

fs

= −5.0 V, I = −5.2 A

−

S

V

D

V

I

= −1.1 A, V = 0 V

−

−0.8

−1.2

SD

S

GS

Dynamic (Note 4.)

Total Gate Charge

Q

−

17

2.8

2.6

15

26

−

nC

ns

g

V

= −4.0 V, V = −4.5 V,

GS

DS

Gate−Source Charge

Gate−Drain Charge

Turn−On Delay Time

Rise Time

Q

gs

Q

gd

I

D

= −5.2 A

−

t

25

70

165

100

60

d(on)

V

= −4.0 V, R = 4 Ω

L

DD

t

r

45

I

D

^^ −1.0 A, V

= −4.5 V,

GEN

Turn−Off Delay Time

Fall Time

t

110

65

d(off)

R

= 6 Ω

G

t

f

Source−Drain Reverse Recovery Time

t

rr

I = −1.1 A, di/dt = 100 A/µs

F

30

2. Surface Mounted on 1″ x 1″ FR4 Board.

3. Pulse Test: Pulse Width v 300 µs, Duty Cycle v 2%.

4. Guaranteed by design, not subject to production testing.

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2

NTHS5445T1

TYPICAL ELECTRICAL CHARACTERISTICS

20

16

20

V

GS

= 5 thru 2.5 V

T

= −55°C

C

16

12

8

2 V

25°C

12

8

125°C

1.5 V

1 V

4

0

0.5

1.0

1.5

2.0

2.5

0

0.5

1.0

1.5

2.0

2.5

3.0

V

DS

, Drain−to−Source Voltage (V)

V

GS

, Gate−to−Source Voltage (V)

Figure 1. Output Characteristics

Figure 2. Transfer Characteristics

0.10

0.08

0.06

0.04

0.02

0

3000

2500

2000

1500

1000

500

V

= 1.8 V

C

GS

iss

V

= 2.5 V

= 4.5 V

GS

C

oss

GS

C

rss

0

2

4

6

8

0

4

8

12

16

20

V

DS

, Drain−to−Source Voltage (V)

I , Drain Current (A)

D

Figure 3. On−Resistance vs. Drain Current

Figure 4. Capacitance

5

1.6

1.4

1.2

1.0

0.8

0.6

V

= 4 V

= 5.2 A

DS

V

GS

= 4.5 V

4

3

2

1

0

I

D

I

D

= 5.2 A

4

0

8

12

16

20

−50

−25

0

25

50

75

100

125 150

Q

Total Gate Charge (nC)

T , Junction Temperature (°C)

J

g,

Figure 5. Gate Charge

Figure 6. On−Resistance vs. Junction

Temperature

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NTHS5445T1

TYPICAL ELECTRICAL CHARACTERISTICS

0.10

20

10

T = 150°C

J

0.08

0.06

0.04

0.02

0

I

D

= 5.2 A

T = 25°C

J

1

0

1

2

3

4

5

0

0.2

0.4

0.6

0.8

1.0

1.2

V

GS

, Gate−to−Source Voltage (V)

V

DS

, Drain−to−Source Voltage (V)

Figure 7. Source−Drain Diode Forward Voltage

Figure 8. On−Resistance vs. Gate−to−Source

Voltage

0.4

0.3

50

40

30

I

D

= 250 µA

0.2

0.1

20

10

0

0.0

−0.1

−0.2

−3

10

−2

10

−1

10

−50 −25

0

25

50

75

100

125

150

1

10

100

600

T , Temperature (°C)

J

Time (sec)

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

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4

NTHS5445T1

TYPICAL ELECTRICAL CHARACTERISTICS

2

1

Duty Cycle = 0.5

Notes:

P

DM

0.2

0.1

t

1

t

2

t

0.1

0.05

1

1. Duty Cycle, D =

t

2

2. Per Unit Base = R

= 80°C/W

0.02

thJA

(t)

3. T

T = P

A

Z

JM −

DM thJA

Single Pulse

4. Surface Mounted

0.01

−4

−3

10

−2

10

−1

10

1

10

100

600

Square Wave Pulse Duration (sec)

Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient

2

1

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

Single Pulse

10

0.01

−4

−3

−2

10

−1

10

Square Wave Pulse Duration (sec)

1

10

Figure 12. Normalized Thermal Transient Impedance, Junction−to−Foot

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NTHS5445T1

PACKAGE DIMENSIONS

CHIPFET

CASE 1206A−01

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM

PER SIDE.

4. LEADFRAME TO MOLDED BODY OFFSET IN

HORIZONTAL AND VERTICAL SHALL NOT EXCEED

0.08 MM.

5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE

BURRS.

A

M

K

8

1

7

2

6

3

5

4

5

4

6

3

7

2

8

1

S

B

6. NO MOLD FLASH ALLOWED ON THE TOP AND

BOTTOM LEAD SURFACE.

L

D

J

MILLIMETERS

INCHES

G

DIM MIN

MAX

MIN

0.116

MAX

0.122

0.067

0.043

0.014

A

B

C

D

G

J

2.95

1.55

1.00

0.25

3.10

1.70 0.061

1.10 0.039

0.35 0.010

STYLE 1:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. GATE

5. SOURCE

6. DRAIN

7. DRAIN

8. DRAIN

0.65 BSC

0.025 BSC

0.10

0.30

0.15 0.004

0.45 0.012

0.008

0.018

0.022 BSC

C

K

L

0.55 BSC

5 ° NOM

−−− 1.80

M

S

5 ° NOM

0.05 (0.002)

−−−

0.071

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NTHS5445T1

80 mil

18 mil

25 mil

68 mil

28

mil

28

mil

26

mil

Figure 13.

Figure 14.

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in

Figure 14. This is sufficient for low power dissipation

MOSFET applications, but power semiconductor

performance requires a greater copper pad area,

particularly for the drain leads.

The minimum recommended pad pattern shown in

Figure 13 improves the thermal area of the drain

connections (pins 1, 2, 3, 6, 7, 8) while remaining within the

confines of the basic footprint. The drain copper area is

0.0054 sq. in. (or 3.51 sq. mm). This will assist the power

dissipation path away from the device (through the copper

leadframe) and into the board and exterior chassis (if

applicable) for the single device. The addition of a further

copper area and/or the addition of vias to other board layers

will enhance the performance still further.

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NTHS5445T1

ChipFET is a trademark of Vishay Siliconix

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

JAPAN: ON Semiconductor, Japan Customer Focus Center

4−32−1 Nishi−Gotanda, Shinagawa−ku, Tokyo, Japan 141−0031

Phone: 81−3−5740−2700

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

N. American Technical Support: 800−282−9855 Toll Free USA/Canada

NTHS5445T1/D

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8

型号:	NTHS5445T1
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	ON SEMICONDUCTOR
包装说明：	CASE 1206A-01, CHIPFET-8
针数：	8
制造商包装代码：	CASE 1206A-01
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
风险等级：	5.36
Is Samacsys：	N
其他特性：	LOGIC LEVEL COMPATIBLE
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	8 V
最大漏极电流 (Abs) (ID)：	5.2 A
最大漏极电流 (ID)：	5.2 A
最大漏源导通电阻：	0.035 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：	R-XDSO-C8
JESD-609代码：	e0
湿度敏感等级：	1
元件数量：	1
端子数量：	8
工作模式：	ENHANCEMENT MODE
最高工作温度：	150 °C
封装主体材料：	UNSPECIFIED
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
极性/信道类型：	P-CHANNEL
最大功率耗散 (Abs)：	0.7 W
认证状态：	Not Qualified
子类别：	Other Transistors
表面贴装：	YES
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	C BEND
端子位置：	DUAL
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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