NTP52N10各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号NTP52N10的概述

芯片NTP52N10概述 NTP52N10是一款具有高效能和高电流能力的N沟道MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor），广泛应用于电源管理、电动机驱动和开关电源等领域。这款MOSFET的电流承载能力和低导通电阻使其在高效能电路中成为一种理想的选择。NTP52N10能够在更高的电压和电流下工作，确保系统的稳定性和高效性。详细参数根据其技术数据手册，NTP52N10的主要参数如下： - 类型：N沟道MOSFET - 最大漏极-源极电压（V_DS）：100V - 最大漏极电流（I_D）：52A - 最大功耗（P_D）：94W（在25°C时） - 导通电阻（R_DS(on)）：约0.045Ω（在V_GS=10V时） - 输入电容（C_iss）：约1380pF - 开关时间（t_on）：约60ns - 关断时间（t_o...

产品型号NTP52N10的Datasheet PDF文件预览

NTP52N10

Power MOSFET

52 Amps, 100 Volts

N−Channel Enhancement Mode TO−220

Features

• Source−to−DrainDiode Recovery Time comparable to a Discrete

Fast Recovery Diode

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• Avalanche Energy Specified

52 AMPERES

100 VOLTS

30 mΩ @ V_GS= 10 V

• I

and R

Specified at Elevated Temperature

DSS

DS(on)

Typical Applications

• PWM Motor Controls

• Power Supplies

• Converters

N−Channel

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Symbol

Value

100

Unit

Vdc

Drain−to−Source Voltage

DSS

DGR

Drain−to−Source Voltage (R = 1.0 MΩ)

100

Gate−to−Source Voltage

− Continuous

"20

"40

− Non−Repetitive (t v10 ms)

GSM

MARKING DIAGRAM

& PIN ASSIGNMENT

Drain− Continuous @ T 25°C

Adc

− Continuous @ T 100°C

− Pulsed (Note 1.)

156

Drain

Total Power Dissipation @ T 25°C

Derate above 25°C

178

1.43

Watts

W/°C

Operating and Storage Temperature Range

T , T

−55 to

+150

°C

stg

TO−220AB

CASE 221A

STYLE 5

Single Drain−to−Source Avalanche Energy

800

NTP52N10

LLYWW

− Starting T = 25°C

(V = 50 V, V = 10 Vdc,

I (pk) = 40 A, L = 1.0 mH, R = 25 Ω)

Gate

Source

Thermal Resistance

°C/W

°C

− Junction−to−Case

− Junction−to−Ambient

0.7

62.5

Drain

NTP52N10 = Device Code

Maximum Lead Temperature for Soldering

260

= Location Code

Purposes, 1/8″ from case for 10 seconds

= Year

= Work Week

1. Pulse Test: Pulse Width = 10 µs, Duty Cycle = 2%.

ORDERING INFORMATION

Device

NTP52N10

Package

Shipping

50 Units/Rail

TO−220AB

Semiconductor Components Industries, LLC, 2003

Publication Order Number:

December, 2003 − Rev. 2

NTP52N10/D

NTP52N10

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Vdc

(BR)DSS

(V = 0 Vdc, I = 250 µAdc)

Temperature Coefficient (Positive)

100

−

160

−

mV/°C

µAdc

Zero Gate Voltage Drain Current

DSS

(V = 0 Vdc, V = 100 Vdc, T =25°C)

−

5.0

(V = 0 Vdc, V = 100 Vdc, T =125°C)

Gate−Body Leakage Current (V = ±20 Vdc, V = 0 Vdc)

−

±100

nAdc

Vdc

GSS

ON CHARACTERISTICS

Gate Threshold Voltage

GS(th)

DS(on)

(V = V , I = 250 µAdc)

2.0

−

2.92

−8.75

4.0

−

Temperature Coefficient (Negative)

mV/°C

Static Drain−to−Source On−State Resistance

Ω

(V = 10 Vdc, I = 26 Adc)

−

0.023

0.050

0.030

0.060

(V = 10 Vdc, I = 26 Adc, T = 125°C)

Drain−to−Source On−Voltage

(V = 10 Vdc, I = 52 Adc)

Vdc

−

1.25

1.45

−

Forward Transconductance (V = 26 Vdc, I = 10 Adc)

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

Output Capacitance

Transfer Capacitance

−

2250

620

3150

860

iss

(V = 25 Vdc, V = 0 Vdc,

oss

f = 1.0 MHz)

135

265

rss

SWITCHING CHARACTERISTICS (Notes 2. & 3.)

Turn−On Delay Time

−

180

150

190

135

−

d(on)

Rise Time

(V = 80 Vdc, I = 52 Adc,

= 10 Vdc, R = 9.1 Ω)

Turn−Off Delay Time

Fall Time

d(off)

100

Gate Charge

tot

(V = 80 Vdc, I = 52 Adc,

= 10 Vdc)

−

BODY−DRAIN DIODE RATINGS (Note 2.)

Diode Forward On−Voltage

(I = 52 Adc, V = 0 Vdc)

−

1.06

0.95

1.5

−

Vdc

(I = 52 Adc, V = 0 Vdc, T = 125°C)

Reverse Recovery Time

−

148

106

−

(I = 52 Adc, V = 0 Vdc,

di /dt = 100 A/µs)

Reverse Recovery Stored Charge

0.66

µC

2. Indicates Pulse Test: P.W. = 300 µs Max, Duty Cycle = 2%.

3. Switching characteristics are independent of operating junction temperature.

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NTP52N10

100

= 10 V

T = 25°C

≥ 10 V

8 V

7 V

9 V

6 V

5.5 V

T = 25°C

4.5 V

5 V

4 V

T = 100°C

T = −55°C

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

Figure 2. Transfer Characteristics

0.05

0.04

0.03

0.02

0.05

0.04

0.03

0.02

T = 25°C

= 10 V

T = 100°C

= 10 V

T = 25°C

= 15 V

0.01

T = −55°C

10 20

90 100

100

I , DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

Drain Current and Temperature

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

10000

1000

2.5

= 0 V

= 26 A

T = 150°C

= 10 V

1.5

100

T = 100°C

0.5

−60

−30

120

150

100

T , JUNCTION TEMPERATURE (°C)

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with

Temperature

Figure 6. Drain−To−Source Leakage

Current versus Voltage

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NTP52N10

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (∆t)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The capacitance (C ) is read from the capacitance curve at

a voltage corresponding to the off−state condition when

iss

calculating t

and is read at a voltage corresponding to the

d(on)

on−state when calculating t

d(off)

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a

resistive load, V remains virtually constant at a level

known as the plateau voltage, V . Therefore, rise and fall

SGP

times may be approximated by the following:

t = Q x R /(V − V )

GSP

t = Q x R /V

GSP

where

= the gate drive voltage, which varies from zero to V

R = the gate drive resistance

and Q and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

= R C In [V /(V − V )]

G iss GG GG GSP

d(on)

d(off)

= R C In (V /V )

GG GSP

iss

6000

= 0 V

T = 25°C

5000

4000

iss

3000

2000

rss

iss

oss

1000

rss

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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NTP52N10

1000

100

d(off)

= 80 V

= 52 A

= 10 V

100

d(on)

= 52 A

T = 25°C

100

Q , TOTAL GATE CHARGE (nC)

R , GATE RESISTANCE (OHMS)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

= 0 V

T = 25°C

0.25 0.35

0.45

0.55

0.65

0.75

0.85

0.95

, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain−to−source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and adjusted for operating conditions

differing from those specified. Although industry practice is

to rate in terms of energy, avalanche energy capability is not

a constant. The energy rating decreases non−linearly with an

increase of peak current in avalanche and peak junction

temperature.

junction temperature and a case temperature (T ) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed

AN569,

“Transient

Thermal

Resistance−General Data and Its Use.”

Switching between the off−state and the on−state may

traverse any load line provided neither rated peak current

Although many E−FETs can withstand the stress of

drain−to−source avalanche at currents up to rated pulsed

current (I ), the energy rating is specified at rated

(I ) nor rated voltage (V ) is exceeded and the

continuous current (I ), in accordance with industry custom.

DSS

transition time (t ,t ) do not exceed 10 µs. In addition the total

power averaged over a complete switching cycle must not

The energy rating must be derated for temperature as shown

in the accompanying graph (Figure 12). Maximum energy at

r f

exceed (T

− T )/(R ).

currents below rated continuous I can safely be assumed to

J(MAX)

θJC

A Power MOSFET designated E−FET can be safely used

in switching circuits with unclamped inductive loads. For

equal the values indicated.

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NTP52N10

SAFE OPERATING AREA

1000

100

800

700

= 20 V

= 40 A

SINGLE PULSE

= 25°C

10 µs

600

500

400

300

200

100

100 µs

1 ms

10 ms

LIMIT

DS(on)

THERMAL LIMIT

PACKAGE LIMIT

0.1

100

1000

100

125

150

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

T , STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

1.0

D = 0.5

0.2

0.1

(pk)

0.1

0.05

(t) = r(t) R

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

0.02

READ TIME AT t

0.01

J(pk)

− T = P

(t)

(pk)

DUTY CYCLE, D = t /t

SINGLE PULSE

0.01

0.00001

0.0001

0.001

0.01

t, TIME (µs)

0.1

1.0

Figure 13. Thermal Response

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

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NTP52N10

PACKAGE DIMENSIONS

TO−220 THREE−LEAD

TO−220AB

CASE 221A−09

ISSUE AA

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

SEATING

PLANE

−T−

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

INCHES

DIM MIN MAX

MILLIMETERS

MIN

14.48

9.66

4.07

0.64

3.61

2.42

2.80

0.46

12.70

1.15

4.83

2.54

2.04

1.15

5.97

0.00

1.15

−−−

MAX

15.75

10.28

4.82

0.88

3.73

2.66

3.93

0.64

14.27

1.52

5.33

3.04

2.79

1.39

6.47

1.27

−−−

0.570

0.380

0.160

0.025

0.142

0.095

0.110

0.018

0.500

0.045

0.190

0.100

0.080

0.045

0.235

0.000

0.045

−−−

0.620

0.405

0.190

0.035

0.147

0.105

0.155

0.025

0.562

0.060

0.210

0.120

0.110

0.055

0.255

0.050

−−−

0.080

2.04

STYLE 5:

PIN 1. GATE

2. DRAIN

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NTP52N10

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

NTP52N10/D

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NTP52N10相关文章

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NTP52N10产品参数

型号:	NTP52N10
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	TO-220AB
包装说明：	CASE 221A-09, TO-220, 3 PIN
针数：	3
制造商包装代码：	CASE 221A-09
Reach Compliance Code：	not_compliant
HTS代码：	8541.29.00.95
风险等级：	5.35
雪崩能效等级（Eas）：	800 mJ
外壳连接：	DRAIN
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	100 V
最大漏极电流 (Abs) (ID)：	52 A
最大漏极电流 (ID)：	60 A
最大漏源导通电阻：	0.03 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码：	TO-220AB
JESD-30 代码：	R-PSFM-T3
JESD-609代码：	e0
元件数量：	1
端子数量：	3
工作模式：	ENHANCEMENT MODE
最高工作温度：	150 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	FLANGE MOUNT
峰值回流温度（摄氏度）：	240
极性/信道类型：	N-CHANNEL
最大功率耗散 (Abs)：	178 W
最大脉冲漏极电流 (IDM)：	156 A
认证状态：	Not Qualified
子类别：	FET General Purpose Power
表面贴装：	NO
端子面层：	Tin/Lead (Sn80Pb20)
端子形式：	THROUGH-HOLE
端子位置：	SINGLE
处于峰值回流温度下的最长时间：	30
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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