OP491GSZ各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

Micropower Single-Supply

Rail-to-Rail Input/Output Op Amps

OP191/OP291/OP491

PIN CONFIGURATIONS

FEATURES

Single-supply operation: 2.7 V to 12 V

Wide input voltage range

Rail-to-rail output swing

Low supply current: 300 μA/amp

Wide bandwidth: 3 MHz

Slew rate: 0.5 V/μs

OUTA

–INA

+INA

–V

1

2

3

4

8

7

6

5

+V

NC

–INA

+INA

–V

1

2

3

4

8

7

6

5

NC

OUTB

–INB

+INB

+V

OP291

OP191

OUTA

NC

NC = NO CONNECT

Figure 1. 8-Lead Narrow-Body SOIC

Figure 2. 8-Lead Narrow-Body SOIC

Low offset voltage: 700 μV

No phase reversal

OUTA

–INA

+INA

+V

1

2

3

4

5

6

7

14 OUTD

13 –IND

12 +IND

11 –V

OUTA

–INA

+INA

+V

1

2

3

4

5

6

7

14 OUTD

13 –IND

12 +IND

11 –V

-

+

APPLICATIONS

Industrial process control

Battery-powered instrumentation

Power supply control and protection

Telecommunications

OP491

+INB

–INB

OUTB

10 +INC

+INB

–INB

OUTB

10 +INC

9

8

–INC

+

9

8

–INC

OUTC

Remote sensors

Low voltage strain gage amplifiers

DAC output amplifiers

Figure 3. 14-Lead Narrow-Body SOIC

Figure 4. 14-Lead PDIP

OUTA

–INA

+INA

+V

1

2

3

4

5

6

7

14 OUTD

13 –IND

12 +IND

11 –V

OP491

+INB

–INB

OUTB

10 +INC

9

8

–INC

OUTC

Figure 5. 14-Lead TSSOP

GENERAL DESCRIPTION

The OP191, OP291, and OP491 are single, dual, and quad

micropower, single-supply, 3 MHz bandwidth amplifiers

featuring rail-to-rail inputs and outputs. All are guaranteed to

operate from a +3 V single supply as well as ±± V dual supplies.

The ability to swing rail-to-rail at both the input and output

enables designers to build multistage filters in single-supply

systems and to maintain high signal-to-noise ratios.

The OP191/OP291/OP491 are specified over the extended

industrial –40°C to +12±°C temperature range. The OP191

single and OP291 dual amplifiers are available in 8-lead plastic

SOIC surface-mount packages. The OP491 quad is available in a

14-lead PDIP, a narrow 14-lead SOIC package, and a 14-lead

TSSOP.

Fabricated on Analog Devices CBCMOS process, the OPx91

family has a unique input stage that allows the input voltage to

safely extend 10 V beyond either supply without any phase

inversion or latch-up. The output voltage swings to within

millivolts of the supplies and continues to sink or source

current all the way to the supplies.

Applications for these amplifiers include portable tele-

communications equipment, power supply control and

protection, and interface for transducers with wide output

ranges. Sensors requiring a rail-to-rail input amplifier include

Hall effect, piezo electric, and resistive transducers.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

OP191/OP291/OP491

TABLE OF CONTENTS

Features .............................................................................................. 1

Overdrive Recovery ................................................................... 18

Applications..................................................................................... 19

Single 3 V Supply, Instrumentation Amplifier....................... 19

Single-Supply RTD Amplifier................................................... 19

A 2.± V Reference from a 3 V Supply ...................................... 20

± V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 20

A High-Side Current Monitor.................................................. 20

Applications....................................................................................... 1

Pin Configurations ........................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Specifications............................................................... 3

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 17

Input Overvoltage Protection ................................................... 18

Output Voltage Phase Reversal................................................. 18

A 3 V, Cold Junction Compensated Thermocouple Amplifier

....................................................................................................... 21

Single-Supply, Direct Access Arrangement for Modems...... 21

3 V, ±0 Hz/60 Hz Active Notch Filter with False Ground..... 22

Single-Supply, Half-Wave, and Full-Wave Rectifiers............. 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 24

REVISION HISTORY

3/04—Rev. B to Rev. C.

4/06—Rev. C to Rev. D

Changes to OP291 SOIC Pin Configuration .................................1

Changes to Noise Performance, Voltage Density, Table 1........... 3

Changes to Noise Performance, Voltage Density, Table 2........... 4

Changes to Noise Performance, Voltage Density, Table 3........... ±

Changes to Figure 23 and Figure 24............................................. 10

Changes to Figure 42...................................................................... 13

Changes to Figure 43...................................................................... 14

Changes to Figure ±7...................................................................... 16

Added Figure ±8.............................................................................. 16

Changed Reference from Figure 47 to Figure 12........................ 17

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide .......................................................... 24

11/03—Rev. A to Rev. B.

Edits to General Description ...........................................................1

Edits to Pin Configuration ...............................................................1

Changes to Ordering Guide.............................................................±

Updated Outline Dimensions....................................................... 19

12/02—Rev. 0 to Rev. A.

Edits to General Description ...........................................................1

Edits to Pin Configuration ...............................................................1

Changes to Ordering Guide.............................................................±

Edits to Dice Characteristics............................................................±

Rev. D | Page 2 of 24

OP191/OP291/OP491

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

@ V_S= 3.0 V, V_CM= 0.1 V, V_O= 1.4 V, T_A= 2±°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

OP191G

V_OS

I_B

80

30

0.1

500

1

μV

mV

μV

mV

nA

V

−40°C ≤ T_A≤ +125°C

OP291G/OP491G

Input Bias Current

Input Offset Current

700

1.25

65

95

11

22

3

I_OS

Input Voltage Range

0

Common-Mode Rejection Ratio

CMRR

A_VO

V_CM= 0 V to 2.9 V

70

65

25

90

87

70

dB

−40°C ≤ T_A≤ +125°C

R_L= 10 kΩ, V_O= 0.3 V to 2.7 V

−40°C ≤ T_A≤ +125°C

Large Signal Voltage Gain

V/mV

μV/°C

pA/°C

50

Offset Voltage Drift

Bias Current Drift

Offset Current Drift

∆V_OS/∆T

∆I_B/∆T

∆I_OS/∆T

1.1

100

20

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

R_L= 100 kΩ to GND

−40°C to +125°C

R_L= 2 kΩ to GND

−40°C to +125°C

R_L= 100 kΩ to V+

−40°C to +125°C

R_L= 2 kΩ to V+

−40°C to +125°C

Sink/source

2.95

2.90

2.8

2.99

2.98

2.9

2.80

4.5

V

mV

mA

Ω

2.70

Output Voltage Low

Short-Circuit Limit

V_OL

10

35

75

130

40

I_SC

8.75

6.0

13.50

10.5

200

−40°C to +125°C

f = 1 MHz, A_V= 1

Open-Loop Impedance

POWER SUPPLY

Z_OUT

PSRR

I_SY

Power Supply Rejection Ratio

V_S= 2.7 V to 12 V

−40°C ≤ T_A≤ +125°C

V_O= 0 V

80

75

110

200

330

dB

μA

Supply Current/Amplifier

350

480

−40°C ≤ T_A≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate

+SR

–SR

BW_P

t_S

GBP

θ_O

R_L= 10 kΩ

1% distortion

To 0.01%

0.4

1.2

22

3

V/μs

kHz

Slew Rate

Full-Power Bandwidth

Settling Time

Gain Bandwidth Product

Phase Margin

μs

MHz

Degrees

dB

45

145

Channel Separation

NOISE PERFORMANCE

Voltage Noise

CS

f = 1 kHz, R_L= 10 kΩ

e_np-p

e_n

i_n

0.1 Hz to 10 Hz

f = 1 kHz

2

30

0.8

μV p-p

nV/√Hz

pA/√Hz

Voltage Noise Density

Current Noise Density

Rev. D | Page 3 of 24

OP191/OP291/OP491

@ V_S= ±.0 V, V_CM= 0.1 V, V_O= 1.4 V, T_A= 2±°C, unless otherwise noted. +± V specifications are guaranteed by +3 V and ±± V testing.

Table 2.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

OP191

V_OS

I_B

80

30

0.1

500

1.0

700

1.25

65

95

11

22

μV

mV

μV

mV

nA

−40°C ≤ T_A≤ +125°C

OP291/OP491

Input Bias Current

Input Offset Current

I_OS

nA

Input Voltage Range

0

5

V

Common-Mode Rejection Ratio

CMRR

A_VO

V_CM= 0 V to 4.9 V

70

65

25

93

90

70

dB

–40°C ≤ T_A≤ +125°C

R_L= 10 kΩ, V_O= 0.3 V to 4.7 V

−40°C ≤ T_A≤ +125°C

Large Signal Voltage Gain

V/mV

μV/°C

pA/°C

50

Offset Voltage Drift

Bias Current Drift

Offset Current Drift

∆V_OS/∆T

∆I_B/∆T

∆I_OS/∆T

1.1

100

20

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

R_L= 100 kΩ to GND

−40°C to +125°C

R_L= 2 kΩ to GND

−40°C to +125°C

R_L= 100 kΩ to V+

−40°C to +125°C

R_L= 2 kΩ to V+

−40°C to +125°C

Sink/source

−40°C to +125°C

f = 1 MHz, A_V= 1

4.95

4.90

4.8

4.99

4.98

4.85

4.75

4.5

V

mV

mA

Ω

4.65

Output Voltage Low

V_OL

10

35

75

155

40

Short-Circuit Limit

I_SC

8.75

6.0

13.5

10.5

200

Open-Loop Impedance

POWER SUPPLY

Z_OUT

PSRR

I_SY

Power Supply Rejection Ratio

V_S= 2.7 V to 12 V

−40°C ≤ T_A≤ +125°C

V_O= 0 V

80

75

110

220

350

dB

μA

Supply Current/Amplifier

400

500

−40°C ≤ T_A≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate

+SR

–SR

BW_P

t_S

GBP

θ_O

R_L= 10 kΩ

1% distortion

To 0.01%

0.4

1.2

22

3

V/μs

kHz

Slew Rate

Full-Power Bandwidth

Settling Time

Gain Bandwidth Product

Phase Margin

μs

MHz

Degrees

dB

45

145

Channel Separation

NOISE PERFORMANCE

Voltage Noise

CS

f = 1 kHz, R_L= 10 kΩ

e_np-p

e_n

i_n

0.1 Hz to 10 Hz

f = 1 kHz

2

42

0.8

μV p-p

nV/√Hz

pA/√Hz

Voltage Noise Density

Current Noise Density

Rev. D | Page 4 of 24

OP191/OP291/OP491

@ V_O= ±±.0 V, –4.9 V ≤ V_CM≤ +4.9 V, T_A= +2±°C, unless otherwise noted.

Table 3.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INPUT CHARACTERISTICS

Offset Voltage

OP191

V_OS

I_B

80

30

500

1

700

1.25

65

μV

mV

μV

mV

nA

−40°C ≤ T_A≤ +125°C

OP291/OP491

Input Bias Current

95

Input Offset Current

I_OS

0.1

11

22

+5

nA

V

dB

−40°C ≤ T_A≤ +125°C

Input Voltage Range

Common-Mode Rejection Ratio

−5

75

67

25

CMRR

A_VO

V_CM

=

5 V

100

97

70

−40°C ≤ T_A≤ +125°C

R_L= +10 kΩ, V_O= 4.7 V

−40°C ≤ T_A≤ +125°C

Large Signal Voltage Gain

50

V/mV

μV/°C

pA/°C

Offset Voltage Drift

Bias Current Drift

Offset Current Drift

∆V_OS/∆T

∆I_B/∆T

∆I_OS/∆T

1.1

100

20

OUTPUT CHARACTERISTICS

Output Voltage Swing

V_O

R_L= 100 kΩ to GND

−40°C to +125°C

R_L= 2 kΩ to GND

–40°C ≤ T_A≤ +125°C

Sink/source

4.93

4.99

V

mA

Ω

4.90

4.80

4.65

8.75

6

4.98

4.95

4.75

16.00

13

Short-Circuit Limit

I_SC

−40°C to +125°C

f = 1 MHz, A_V= 1

Open-Loop Impedance

POWER SUPPLY

Z_OUT

PSRR

I_SY

200

Power Supply Rejection Ratio

V_S= 5 V

−40°C ≤ T_A≤ +125°C

V_O= 0 V

80

75

110

100

260

390

dB

μA

Supply Current/Amplifier

420

550

−40°C ≤ T_A≤ +125°C

DYNAMIC PERFORMANCE

Slew Rate

SR

BW_P

t_S

GBP

θ_O

R_L= 10 kΩ

1% distortion

To 0.01%

0.5

1.2

22

3

45

145

V/μs

kHz

μs

MHz

Degrees

dB

Full-Power Bandwidth

Settling Time

Gain Bandwidth Product

Phase Margin

Channel Separation

NOISE PERFORMANCE

Voltage Noise

CS

f = 1 kHz

e_np-p

e_n

i_n

0.1 Hz to 10 Hz

f = 1 kHz

2

42

0.8

μV p-p

nV/√Hz

pA/√Hz

Voltage Noise Density

Current Noise Density

Rev. D | Page 5 of 24

OP191/OP291/OP491

5V

V

= ±5V

s

R

= 2kΩ

100

90

L

A

= +1

V

= 20V p-p

IN

INPUT

OUTPUT

10

0%

5V

200μs

Figure 6. Input and Output with Inputs Overdriven by 5 V

Rev. D | Page 6 of 24

OP191/OP291/OP491

ABSOLUTE MAXIMUM RATINGS

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

Supply Voltage

16 V

Input Voltage

GND to V_S10 V

7 V

Indefinite

Differential Input Voltage

Output Short-Circuit Duration to GND

Storage Temperature Range

N, R, RU Packages

Operating Temperature Range

OP191G/OP291G/OP491G

Junction Temperature Range

N, R, RU Packages

–65°C to +150°C

–40°C to +125°C

Absolute maximum ratings apply to both DICE and packaged

parts, unless otherwise noted.

THERMAL RESISTANCE

–65°C to +150°C

300°C

θ_JAis specified for the worst-case conditions; that is, θ_JAis

specified for device in socket for PDIP packages; θ_JAis specified

for device soldered in circuit board for TSSOP and SOIC

packages.

Lead Temperature (Soldering, 60 sec)

Table 5. Thermal Resistance

Package Type

θ_JA

θ_JC

43

33

36

35

Unit

°C/W

8-Lead SOIC (R)

14-Lead PDIP (N)

14-Lead SOIC (R)

14-Lead TSSOP (RU)

158

76

120

180

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. D | Page 7 of 24

OP191/OP291/OP491

TYPICAL PERFORMANCE CHARACTERISTICS

180

40

30

V

= 3V

= 25°C

S

V

= 3V

CM

T

A

160

140

120

BASED ON

1200 OP AMPS

20

10

= 2.9V

0

100

80

V

= 3V

S

–10

V

= 0.1V

CM

–20

–30

–40

60

40

= 0V

85

20

0

–50

–60

–0.18

–0.10

–0.02

0.06

0.14

0.22

–40

25

TEMPERATURE (°C)

125

INPUT OFFSET VOLTAGE (mV)

Figure 7. OP291 Input Offset Voltage Distribution, V_S= 3 V

Figure 10. Input Bias Current vs. Temperature, V_S= 3 V

120

0

V

= 3V

S

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–40°C < T < +125°C

BASED ON 600 OP AMPS

A

100

V

= 0.1V

= 2.9V

CM

V

= 3V

CM

S

80

60

40

20

0

V

= 3V

CM

V

= 0V

CM

0

1

2

3

4

5

6

7

–40

25

85

125

INPUT OFFSET VOLTAGE (µV/°C)

TEMPERATURE (°C)

Figure 8. OP291 Input Offset Voltage Drift Distribution, V_S= 3 V

Figure 11. Input Offset Current vs. Temperature, V_S= 3 V

0

36

V

= 3V

V = 3V

S

30

24

18

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

V

= 0.1V

CM

12

6

V

= 0V

CM

V

= 3V

CM

0

–6

V

= 2.9V

–12

–18

CM

–24

–30

–36

–40

25

85

125

0

0.3

0.6

0.9 1.2

1.5 1.8

2.1 2.4

2.7 3.0

TEMPERATURE (°C)

INPUT COMMON-MODE VOLTAGE (V)

Figure 9. Input Offset Voltage vs. Temperature, V_S= 3 V

Figure 12. Input Bias Current vs. Input Common-Mode Voltage, V_S= 3 V

Rev. D | Page 8 of 24

OP191/OP291/OP491

3.00

2.95

2.90

2.85

2.80

2.75

50

40

+V @ R = 100kꢀ

V

T

= 3V

= 25°C

O

L

S

A

30

20

10

0

+V @ R = 2kꢀ

O

L

–10

–20

–30

–40

V

= 3V

S

–50

160

–40

25

85

125

10

100

1k

10k

100k

1M

10M

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 13. Output Voltage Swing vs. Temperature, V_S= 3 V

Figure 16. Closed-Loop Gain vs. Frequency, V_S= 3 V

160

CMRR

V

T

= 3V

= 25°C

S

A

V

= 3V

140

120

140

120

100

80

S

A

T

= 25°C

100

80

60

40

20

0

60

40

90

20

0

45

0

–20

–40

–45

–90

–20

–40

100

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 17. CMRR vs. Frequency, V_S= 3 V

Figure 14. Open-Loop Gain and Phase vs. Frequency, V_S= 3 V

90

89

1200

V

= 3V

S

R

V

= 100kꢀ,

L

= 2.9V

CM

1000

800

600

400

200

0

R

= 100kꢀ,

= 0.1V

L

88

87

86

85

84

V

CM

V

= 3V, V = 0.3V/2.7V

O

S

–40

25

85

125

–40

25

85

125

TEMPERATURE (°C)

Figure 18. CMRR vs. Temperature, V_S= 3 V

Figure 15. Open-Loop Gain vs. Temperature, V_S= 3 V

Rev. D | Page 9 of 24

OP191/OP291/OP491

0.35

160

V

= 3V

±PSRR

S

140

120

100

80

V

T

= 3V

= 25°C

S

A

0.30

0.25

+PSRR

60

0.20

0.15

0.10

–PSRR

40

20

0

–20

–40

0.05

–40

100

1k

10k

100k

1M

10M

125

25

85

125

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 19. PSRR vs. Frequency, V_S= 3 V

Figure 22. Supply Current vs. Temperature, V_S= +3 V, +5 V, 5 V

113

112

111

110

109

108

107

3.0

V

A

R

= 2.8V p-p

= 3V

= +1

IN

S

V

= 3V

S

2.5

V

L

= 100kꢀ

2.0

1.5

1.0

0.5

0

100

1k

10k

100k

1M

–40

25

85

FREQUENCY (Hz)

TEMPERATURE (°C)

Figure 23. Maximum Output Swing vs. Frequency, V_S= 3 V

Figure 20. PSRR vs. Temperature, V_S= 3 V

1k

1.6

1.4

1.2

1.0

0.8

V

= 3V

S

+SR

100

0.6

0.4

0.2

–SR

10

0

–40

10

100

1k

FREQUENCY (Hz)

10k

25

85

TEMPERATURE (°C)

Figure 24. Voltage Noise Density, V_S= 5 V or 5 V

Figure 21. Slew Rate vs. Temperature, V_S= 3 V

Rev. D | Page 10 of 24

OP191/OP291/OP491

70

40

30

V = 5V

S

V

= 5V

= 25°C

S

+I

B

T

A

60

50

BASED ON 600

OP AMPS

–I

B

V

= 5V

CM

20

10

40

30

0

–10

–20

–30

–40

20

10

0

V

= 0V

CM

–I

B

+I

B

–0.50

–0.30

–0.10

0.10

0.30

0.50

–40

25

85

125

INPUT OFFSET VOLTAGE (mV)

TEMPERATURE (°C)

Figure 25. OP291 Input Offset Voltage Distribution, V_S= 5 V

Figure 28. Input Bias Current vs. Temperature, V_S= 5 V

120

1.6

1.4

1.2

1.0

0.8

0.6

0.4

V

= 5V

S

V

= 5V

S

–40°C < T < +125°C

BASED ON 600 OP AMPS

A

100

80

60

40

20

0

V

= 0V

CM

0.2

0

V

= 5V

CM

–0.2

0

1

2

3

4

5

6

7

–40

25

85

125

INPUT OFFSET VOLTAGE (µV/°C)

TEMPERATURE (°C)

Figure 26. OP291 Input Offset Voltage Drift Distribution, V_S= 5 V

Figure 29. Input Offset Current vs. Temperature, V_S= 5 V

0.15

36

V

= 5V

S

V

= 5V

S

30

24

18

0.10

0.05

0

V

= 0V

CM

12

6

0

–6

–12

–18

V

= 5V

CM

–0.05

–0.10

–24

–30

–36

0

1

2

3

4

5

–40

25

85

125

COMMON-MODE INPUT VOLTAGE (V)

TEMPERATURE (°C)

Figure 27. Input Offset Voltage vs. Temperature, V_S= 5 V

Figure 30. Input Bias Current vs. Common-Mode Input Voltage, V_S= 5 V

Rev. D | Page 11 of 24

OP191/OP291/OP491

50

40

5.00

4.95

4.90

4.85

R

= 100kꢀ

V

T

= 5V

= 25°C

L

S

A

30

20

10

0

R

= 2kꢀ

–10

L

4.80

4.75

4.70

–20

–30

–40

V

= 5V

S

–50

160

–40

25

85

125

10

100

1k

10k

100k

1M

10M

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 31. Output Voltage Swing vs. Temperature, V_S= 5 V

Figure 34. Closed-Loop Gain vs. Frequency, V_S= 5 V

160

CMRR

V

T

= 5V

= 25°C

S

A

V

= 5V

140

120

140

120

100

80

S

A

T

= 25°C

100

80

60

40

20

0

60

40

90

20

0

45

0

–20

–40

–45

–90

–20

–40

100

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 35. CMRR vs. Frequency, V_S= 5V

Figure 32. Open-Loop Gain and Phase vs. Frequency, V_S= 5 V

96

95

94

140

V

= 5V

S

V

= 5V

S

R

= 100kꢀ, V

= 5V

CM

120

100

80

L

93

92

91

90

60

R

= 100kꢀ, V

= 0V

CM

L

89

88

40

20

R

= 2kꢀ, V = 5V

CM

L

87

86

R

= 2kꢀ, V = 0V

CM

L

0

–40

25

85

125

25

85

125

TEMPERATURE (°C)

Figure 36. CMRR vs. Temperature, V_S= 5 V

Figure 33. Open-Loop Gain vs. Temperature, V_S= 5 V

Rev. D | Page 12 of 24

OP191/OP291/OP491

20

18

16

14

12

160

±PSRR

V

= 5V

S

A

140

120

100

80

+I , V = ±5V

SC

S

T

= 25°C

–I , V = ±5V

SC

S

+PSRR

+I , V = +3V

SC

S

60

40

10

8

–I , V = +3V

SC

S

–PSRR

20

0

6

4

–20

–40

25

85

125

100

1k

10k

100k

1M

10M

125

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 40. Short-Circuit Current vs. Temperature, V_S= +3 V, +5 V, 5 V

Figure 37. PSRR vs. Frequency, V_S= 5 V

80

0.6

0.5

0.4

0.3

0.2

0.1

0

V

= ±5V

S

70

60

50

+SR

–SR

40

30

20

10kꢀ

1kꢀ

V

O

A

B

10

0

10kꢀ

= 10V p-p @ 1kHz

V

= 5V

S

V

IN

0

500

1000

1500

2000

2500

–40

25

85

FREQUENCY (Hz)

TEMPERATURE (°C)

Figure 41. Channel Separation, V_S= 5 V

Figure 38. OP291 Slew Rate vs. Temperature, V_S= 5 V

5.0

0.50

V

= 4.8V p-p

= 5V

IN

V

= 5V

S

4.5

4.0

0.45

0.40

A

R

= +1

= 100kꢀ

V

L

+SR

3.5

3.0

0.35

0.30

–SR

2.5

2.0

0.25

0.20

1.5

1.0

0.15

0.10

0.5

0

0.05

0

100

1k

10k

100k

1M

–40

25

85

FREQUENCY (Hz)

TEMPERATURE (°C)

Figure 42. Maximum Output Swing vs. Frequency, V_S= 5 V

Figure 39. OP491 Slew Rate vs. Temperature, V_S= 5 V

Rev. D | Page 13 of 24

OP191/OP291/OP491

10

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

A

R

= 9.8V p-p

= ±5V

= +1

IN

S

V = ±5V

S

V

L

= 100kꢀ

8

V

= –5V

CM

6

4

2

V

= +5V

CM

0

100

–0.2

1k

10k

100k

1M

–40

25

85

125

FREQUENCY (Hz)

TEMPERATURE (°C)

Figure 43. Maximum Output Swing vs. Frequency, V_S= 5 V

Figure 46. Input Offset Current vs. Temperature, V_S= 5 V

0.15

36

V

= ±5V

S

V

= ±5V

S

24

12

0.10

0.05

0

V

= –5V

CM

0

–12

–24

–36

V

= +5V

CM

–0.05

–0.10

–40

25

85

125

–5

–4

–3

–2

–1

0

1

2

3

4

5

TEMPERATURE (°C)

COMMON-MODE INPUT VOLTAGE (V)

Figure 44. Input Offset Voltage vs. Temperature, V_S= 5 V

Figure 47. Input Bias Current vs. Common-Mode Voltage, V_S= 5 V

50

5.00

V

= ±5V

S

R

= 2kꢀ

L

4.95

4.90

4.85

40

+I

B

30

20

10

0

–I

V

= +5V

B

CM

4.80

4.75

R

= 2kꢀ

L

V

= ±5V

S

0

–4.75

–4.80

–10

–20

–30

V

= –5V

CM

–I

B

–4.85

–4.90

B

R

= 2kꢀ

L

+I

–40

–50

–4.95

–5.00

R

= 2kꢀ

L

–40

25

85

125

–40

25

85

125

TEMPERATURE (°C)

Figure 45. Input Bias Current vs. Temperature, V_S= 5 V

Figure 48. Output Voltage Swing vs. Temperature, V_S= 5 V

Rev. D | Page 14 of 24

OP191/OP291/OP491

70

60

160

CMRR

V

T

= ±5V

= 25°C

S

V

= ±5V

S

A

140

120

A

T

= 25°C

50

40

30

20

10

100

80

0

45

60

40

90

135

180

225

270

0

–10

–20

–30

20

0

–20

–40

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 49. Open-Loop Gain and Phase vs. Frequency, V_S= 5 V

Figure 52. CMRR vs. Frequency, V_S= 5 V

200

102

V

= ±5V

V

= ±5V

S

180

160

101

100

R

L

= 2kꢀ

140

120

99

98

100

80

97

96

95

94

65

40

25

0

R

L

= 2kꢀ

93

92

–40

25

85

125

–40

25

85

125

TEMPERATURE (°C)

Figure 50. Open-Loop Gain vs. Temperature, V_S= 5 V

Figure 53. CMRR vs. Temperature, V_S= 5 V

50

40

160

±PSRR

V

T

= ±5V

= 25°C

S

A

V

= ±5V

S

A

140

120

T

= 25°C

30

20

10

100

80

+PSRR

0

60

40

–10

–PSRR

–20

20

0

–30

–40

–20

–40

–50

10

100

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 51. Closed-Loop Gain vs. Frequency, V_S= 5 V

Figure 54. PSRR vs. Frequency, V_S= 5 V

Rev. D | Page 15 of 24

OP191/OP291/OP491

115

1k

V

= ±5V

S

OP491

110

105

100

95

OP291

100

10

90

–40

10

100

1k

FREQUENCY (Hz)

10k

25

85

125

TEMPERATURE (°C)

Figure 55. OP291/OP491 PSRR vs. Temperature, V_S= 5 V

Figure 58. Voltage Noise Density, V_S= 3 V

0.7

V

= ±5V

S

1.00V

0.6

0.5

0.4

0.3

0.2

0.1

0

100

90

+SR

–SR

INPUT

V

S

= 3V

= 200kꢀ

OUTPUT

10

R

L

0%

500mV

2.00µs

100mV

–40

25

85

125

TEMPERATURE (°C)

Figure 56. Slew Rate vs. Temperature, V_S= 5 V

Figure 59. Large Signal Transient Response, V_S= 3 V

1k

100

10

V

= 3V

S

2.00V

A

= +100

V

100

90

A

= +10

V

INPUT

A

= +1

V

1

V

R

A

= ±5V

= 200kꢀ

= +1V/V

S

L

V

10

0%

OUTPUT

1.00V

2.00µs

100mV

0.1

1k

10k

100k

FREQUENCY (Hz)

1M 2M

Figure 57. Output Impedance vs. Frequency

Figure 60. Large Signal Transient Response, V_S= 5 V

Rev. D | Page 16 of 24

OP191/OP291/OP491

THEORY OF OPERATION

The OP191/OP291/OP491 are single-supply, micropower

amplifiers featuring rail-to-rail inputs and outputs. To achieve

wide input and output ranges, these amplifiers employ unique

input and output stages. In Figure 61 , the input stage comprises

two differential pairs, a PNP pair and an NPN pair. These two

stages do not work in parallel. Instead, only one stage is on for

any given input signal level. The PNP stage (Transistor Q1 and

Transistor Q2) is required to ensure that the amplifier remains

in the linear region when the input voltage approaches and

reaches the negative rail. On the other hand, the NPN stage

(Transistor Q± and Transistor Q6) is needed for input voltages

up to and including the positive rail.

Notice that the input stage includes ± kΩ series resistors and

differential diodes, a common practice in bipolar amplifiers to

protect the input transistors from large differential voltages.

These diodes turn on whenever the differential voltage exceeds

approximately 0.6 V. In this condition, current flows between

the input pins, limited only by the two ± kΩ resistors. This

characteristic is important in circuits where the amplifier may

be operated open-loop, such as a comparator. Evaluate each

circuit carefully to make sure that the increase in current does

not affect the performance.

The output stage in OP191 devices uses a PNP and an NPN

transistor, as do most output stages; however, Q32 and Q33, the

output transistors, are actually connected with their collectors

to the output pin to achieve the rail-to-rail output swing. As the

output voltage approaches either the positive or negative rail,

these transistors begin to saturate. Thus, the final limit on

output voltage is the saturation voltage of these transistors,

which is about ±0 mV. The output stage does have inherent gain

arising from the collectors and any external load impedance.

Because of this, the open-loop gain of the amplifier is

dependent on the load resistance.

For the majority of the input common-mode range, the PNP

stage is active, as is shown in Figure 12. Notice that the bias

current switches direction at approximately 1.2 V to 1.3 V

below the positive rail. At voltages below this, the bias current

flows out of the OP291, indicating a PNP input stage. Above

this voltage, however, the bias current enters the device,

revealing the NPN stage. The actual mechanism within the

amplifier for switching between the input stages comprises

Transistor Q3, Transistor Q4, and Transistor Q7. As the input

common-mode voltage increases, the emitters of Q1 and Q2

follow that voltage plus a diode drop. Eventually, the emitters

of Q1 and Q2 are high enough to turn on Q3, which diverts the

8 μA of tail current away from the PNP input stage, turning it

off. Instead, the current is mirrored through Q4 and Q7 to

activate the NPN input stage.

Q22

Q26

8µA

–IN

Q32

Q23

Q27

5kꢀ

Q3

Q20

Q30

Q31

5kꢀ

Q16

Q5 Q6

+IN

Q1 Q2

10pF

Q17

Q8

Q10

Q11

Q12

Q14

Q15

V

Q21

OUT

Q9

Q13

Q24 Q28

Q18

Q19

Q25

Q29

Q33

Q4

Q7

Figure 61. Simplified Schematic

Rev. D | Page 17 of 24

OP191/OP291/OP491

OUTPUT VOLTAGE PHASE REVERSAL

INPUT OVERVOLTAGE PROTECTION

Some operational amplifiers designed for single-supply

operation exhibit an output voltage phase reversal when their

inputs are driven beyond their useful common-mode range.

Typically, for single-supply bipolar op amps, the negative supply

determines the lower limit of their common-mode range.

With these devices, external clamping diodes with the anode

connected to ground and the cathode to the inputs prevent

input signal excursions from exceeding the device’s negative

supply (that is, GND), preventing a condition that could cause

the output voltage to change phase. JFET input amplifiers can

also exhibit phase reversal, and, if so, a series input resistor is

usually required to prevent it.

As with any semiconductor device, whenever the condition

exists for the input to exceed either supply voltage, check the

input overvoltage characteristic. When an overvoltage occurs,

the amplifier could be damaged depending on the voltage level

and the magnitude of the fault current. Figure 62 shows the

characteristics for the OP191 family. This graph was generated

with the power supplies at ground and a curve tracer connected

to the input. When the input voltage exceeds either supply by

more than 0.6 V, internal PN junctions energize, allowing

current to flow from the input to the supplies. As described, the

OP291/OP491 do have ± kΩ resistors in series with each input

to help limit the current. Calculating the slope of the current vs.

voltage in the graph confirms the ± kΩ resistor.

The OP191 is free from reasonable input voltage range

restrictions due to its novel input structure. In fact, the input

signal can exceed the supply voltage by a significant amount

without causing damage to the device. As shown in Figure 64,

the OP191 family can safely handle a 20 V p-p input signal on

±± V supplies without exhibiting any sign of output voltage

phase reversal or other anomalous behavior. Thus, no external

clamping diodes are required.

I

IN

+2mA

+1mA

–10V

–5V

+5V

+10V

V

IN

OVERDRIVE RECOVERY

The overdrive recovery time of an operational amplifier is the

time required for the output voltage to recover to its linear

region from a saturated condition. This recovery time is

important in applications where the amplifier must recover

quickly after a large transient event, such as a comparator. The

circuit shown in Figure 63 was used to evaluate the OPx91

overdrive recovery time. The OPx91 takes approximately 8 μs to

recover from positive saturation and approximately 6.± μs to

recover from negative saturation.

–1mA

–2mA

Figure 62. Input Overvoltage Characteristics

This input current is not inherently damaging to the device as

long as it is limited to ± mA or less. For an input of 10 V over

the supply, the current is limited to 1.8 mA. If the voltage is

large enough to cause more than ± mA of current to flow, then

an external series resistor should be added. The size of this

resistor is calculated by dividing the maximum overvoltage by

± mA and subtracting the internal ± kΩ resistor. For example, if

the input voltage could reach 100 V, the external resistor should

be (100 V/± mA) − ± kꢀ = 1± kΩ. This resistance should be

placed in series with either or both inputs if they are subjected

to the overvoltages.

R1

9kꢀ

3

2

+

1/2

V

1

OUT

IN

10V STEP

OP291

–

R2

10kꢀ

R3

10kꢀ

V

= ±5V

S

Figure 63. Overdrive Recovery Time Test Circuit

5µs

100

90

100

90

+5V

8

V

IN

3

2

+

20V p-p

1/2

OP291

V

1

OUT

–

4

10

0%

–5V

20mV

TIME (200µs/DIV)

Figure 64. Output Voltage Phase Reversal Behavior

Rev. D | Page 18 of 24

OP191/OP291/OP491

APPLICATIONS

SINGLE 3 V SUPPLY, INSTRUMENTATION

AMPLIFIER

SINGLE-SUPPLY RTD AMPLIFIER

The circuit in Figure 66 uses three op amps of the OP491 to

develop a bridge configuration for an RTD amplifier that

operates from a single ± V supply. The circuit takes advantage of

the OP491 wide output swing range to generate a high bridge

excitation voltage of 3.9 V. In fact, because of the rail-to-rail

output swing, this circuit works with supplies as low as 4.0 V.

Amplifier A1 servos the bridge to create a constant excitation

current in conjunction with the AD±89, a 1.23± V precision

reference. The op amp maintains the reference voltage across

the parallel combination of the 6.19 kΩ and 2.±± MΩ resistors,

which generate a 200 μA current source. This current splits

evenly and flows through both halves of the bridge. Thus,

100 μA flows through the RTD to generate an output voltage

based on its resistance. A 3-wire RTD is used to balance the line

resistance in both 100 Ω legs of the bridge to improve accuracy.

The OP291 low supply current and low voltage operation

make it ideal for battery-powered applications, such as the

instrumentation amplifier shown in Figure 6±. The circuit uses

the classic two op amp instrumentation amplifier topology, with

four resistors to set the gain. The equation is simply that of a

noninverting amplifier, as shown in Figure 6±. The two resistors

labeled R1 should be closely matched both to each other and to

the two resistors labeled R2 to ensure good common-mode

rejection performance. Resistor networks ensure the closest

matching as well as matched drifts for good temperature

stability. Capacitor C1 is included to limit the bandwidth and,

therefore, the noise in sensitive applications. The value of this

capacitor should be adjusted depending on the desired closed-

loop bandwidth of the instrumentation amplifier. The RC

combination creates a pole at a frequency equal to 1/(2π ×

R1C1). If AC-CMRR is critical, then a matched capacitor to C1

should be included across the second resistor labeled R1.

GAIN = 274

200ꢀ

10 TURNS

5V

26.7kꢀ

3V

A3

1/4

OP491

8

V

100ꢀ

RTD

OUT

5

6

A2

+

1/2

1/4

7

V

OUT

IN

OP291

100ꢀ

2.55Mꢀ

OP491

4

3

2

–

1/2

OP291

365ꢀ

100kꢀ

1

6.19kꢀ

A1

1/4

OP491

100kꢀ

R1

R2

R1

0.01pF

ALL RESISTORS 1% OR BETTER

AD589

C1

100pF

37.4kꢀ

R1

R2

V

= (1 +

OUT

) = V

IN

Figure 65. Single 3 V Supply Instrumentation Amplifier

5V

Figure 66. Single-Supply RTD Amplifier

Because the OP291 accepts rail-to-rail inputs, the input

common-mode range includes both ground and the positive

supply of 3 V. Furthermore, the rail-to-rail output range ensures

the widest signal range possible and maximizes the dynamic

range of the system. Also, with its low supply current of

300 μA/device, this circuit consumes a quiescent current of

only 600 μA yet still exhibits a gain bandwidth of 3 MHz.

Amplifier A2 and Amplifier A3 are configured in the two op

amp instrumentation amplifier topology described in the Single

3 V Supply, Instrumentation Amplifier section. The resistors are

chosen to produce a gain of 274, such that each 1°C increase in

temperature results in a 10 mV change in the output voltage, for

ease of measurement. A 0.01 μF capacitor is included in parallel

with the 100 kΩ resistor on Amplifier A3 to filter out any

unwanted noise from this high gain circuit. This particular RC

combination creates a pole at 1.6 kHz.

A question may arise about other instrumentation amplifier

topologies for single-supply applications. For example, a

variation on this topology adds a fifth resistor between the two

inverting inputs of the op amps for gain setting. While that

topology works well in dual-supply applications, it is inherently

inappropriate for single-supply circuits. The same could be said

for the traditional three op amp instrumentation amplifier. In

both cases, the circuits simply cannot work in single-supply

situations unless a false ground between the supplies is created.

Rev. D | Page 19 of 24

OP191/OP291/OP491

A 2.5 V REFERENCE FROM A 3 V SUPPLY

In many single-supply applications, the need for a 2.± V

reference often arises. Many commercially available monolithic

2.± V references require a minimum operating supply voltage of

4 V. The problem is exacerbated when the minimum operating

system supply voltage is 3 V. The circuit illustrated in Figure 67

is an example of a 2.± V reference that operates from a single

3 V supply. The circuit takes advantage of the OP291 rail-to-rail

input and output voltage ranges to amplify an AD±89 1.23± V

output to 2.± V. The OP291 low TCV_OSof 1 μV/°C helps

maintain an output voltage temperature coefficient of less than

200 ppm/°C. The circuit overall temperature coefficient is

dominated by the temperature coefficient of R2 and R3. Lower

temperature coefficient resistors are recommended. The entire

circuit draws less than 420 μA from a 3 V supply at 2±°C.

The OP291 serves two functions. First, it is required to buffer

the high output impedance of the DAC V_REFpin, which is on the

order of 10 kΩ. The op amp provides a low impedance output

to drive any following circuitry. Second, the op amp amplifies

the output signal to provide a rail-to-rail output swing. In this

particular case, the gain is set to 4.1 to generate a ±.0 V output

when the DAC is at full scale. If other output voltage ranges are

needed, such as 0 V to 4.09± V, the gain can easily be adjusted

by altering the value of the resistors.

A HIGH-SIDE CURRENT MONITOR

In the design of power supply control circuits, a great deal of

design effort is focused on ensuring a pass transistor’s long-

term reliability over a wide range of load current conditions.

As a result, monitoring and limiting device power dissipation

is of prime importance in these designs. The circuit illustrated

in Figure 69 is an example of a ± V, single-supply, high-side

current monitor that can be incorporated into the design of a

voltage regulator with fold-back current limiting or a high

current power supply with crowbar protection. This design uses

an OP291 rail-to-rail input voltage range to sense the voltage

drop across a 0.1 Ω current shunt. A p-channel MOSFET used

as the feedback element in the circuit converts the op amp

differential input voltage into a current. This current is then

applied to R2 to generate a voltage that is a linear representation

of the load current. The transfer equation for the current

monitor is given by

3V

R1

3V

17.4kꢀ

3

2

8

1/2

OP291

2.5V

1

AD589

REF

4

RESISTORS = 1%, 100ppm/°C

POTENTIOMETER = 10 TURN, 100ppm/°C

R3

R2

R1

5kꢀ

100kꢀ

Figure 67. A 2.5 V Reference that Operates on a Single 3 V Supply

5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL

The OPx91 family is ideal for use with a CMOS DAC to

generate a digitally controlled voltage with a wide output range.

Figure 68 shows the DAC8043 used in conjunction with the

AD±89 to generate a voltage output from 0 V to 1.23 V. The

DAC is operated in voltage switching mode, where the reference

is connected to the current output, I_OUT, and the output voltage

is taken from the V_REFpin. This topology is inherently

R

⎛

⎜

⎝

⎞

⎟

⎠

SENSE

Monitor Output = R2×

×I

L

R1

For the element values shown, the monitor output transfer

characteristic is 2.± V/A.

noninverting as opposed to the classic current output mode,

which is inverting and, therefore, unsuitable for single supply.

R

0.1ꢀ

SENSE

I

L

5V

R1

100ꢀ

8

3

2

8

1/2

1

R1

2

OP291

V

R

FB

DD

DAC8043

GND CLK SR1 LD

17.8kꢀ

4

3

1

I

S

M1

3N163

1.23V

V

OUT

REF

G

5V

8

MONITOR

OUTPUT

4

7

6

5

D

3

AD589

D

1/2

OP291

R2

2.49kꢀ

V

= –––– (5V)

1

OUT

4096

DIGITAL

4

CONTROL

2

Figure 69. A High-Side Load Current Monitor

R2

32.4kꢀ

R4

100kꢀ

R3

232ꢀ

1%

Figure 68. 5 V Only, 12-Bit DAC Swings Rail-to-Rail

Rev. D | Page 20 of 24

OP191/OP291/OP491

The transmit signal, TXA, is inverted by A2 and then reinverted

by A3 to provide a differential drive to the transformer, where

each amplifier supplies half the drive signal. This is needed

because of the smaller swings associated with a single supply as

opposed to a dual supply. Amplifier A1 provides some gain for

the received signal, and it also removes the transmit signal

present at the transformer from the received signal. To do this,

the drive signal from A2 is also fed to the noninverting input of

A1 to cancel the transmit signal from the transformer.

A 3 V, COLD JUNCTION COMPENSATED

THERMOCOUPLE AMPLIFIER

The OP291 low supply operation makes it ideal for 3 V battery-

powered applications such as the thermocouple amplifier

shown in Figure 70. The K-type thermocouple terminates in an

isothermal block where the junction ambient temperature is

continuously monitored using a simple 1N914 diode. The diode

corrects the thermal EMF generated in the junctions by feeding

a small voltage, scaled by the 1.± MΩ and 47± Ω resistors, to the

op amp.

390pF

37.4kꢀ

To calibrate this circuit, immerse the thermocouple measuring

junction in a 0°C ice bath and adjust the ±00 Ω potentiometer

to 0 V out. Next, immerse the thermocouple in a 2±0°C

temperature bath or oven and adjust the scale adjust

potentiometer for an output voltage of 2.±0 V. Within this

temperature range, the K-type thermocouple is accurate to

within ±3°C without linearization.

20kꢀ,1%

A1

13

0.1μF

1/4

OP491

RXA

14

12

0.0047μF

3.3kꢀ

20kꢀ,1%

A2

10

475ꢀ,1%

1.235V

1/4

OP491

8

10kꢀ

AD589

3.0V

9

37.4kꢀ,1%

T1

ISOTHERMAL

BLOCK

SCALE

ADJUST

1.33Mꢀ 20kꢀ

0.1μF

7.15kꢀ

24.3kꢀ

1%

750pF

20kꢀ,1%

1N914

1%

TXA

0.033μF

1:1

20kꢀ,1%

24.9kꢀ

1%

1.5Mꢀ

1%

4.99kꢀ

1%

ALUMEL

8

2

3

AL

CR

V

OUT

1/2

OP291

5.1V TO 6.2V

ZENER 5

COLD

JUNCTIONS

1

500ꢀ

10 TURN

A3

7

6

5

O¹P^/4491

0V = 0°C

3V = 300°C

11.2mV

4

ZERO

ADJUST

CHROMEL

475ꢀ

1%

2.1kꢀ

1%

3V OR 5V

K-TYPE

THERMOCOUPLE

40.7μV/°C

Figure 70. A 3 V, Cold Junction Compensated Thermocouple Amplifier

4

2

3

100kꢀ

1/4

OP491

11

1

SINGLE-SUPPLY, DIRECT ACCESS ARRANGEMENT

FOR MODEMS

A4

10μF

0.1μF

100kꢀ

An important building block in modems is the telephone line

interface. In the circuit shown in Figure 71, a direct access

arrangement is used to transmit and receive data from the

telephone line. Amplifier A1 is the receiving amplifier;

Amplifier A2 and Amplifier A3 are the transmitters. The fourth

amplifier, A4, generates a pseudo ground halfway between the

supply voltage and ground. This pseudo ground is needed for

the ac-coupled bipolar input signals.

Figure 71. Single-Supply, Direct Access Arrangement for Modems

The OP491 bandwidth of 3 MHz and rail-to-rail output swings

ensure that it can provide the largest possible drive to the

transformer at the frequency of transmission.

Rev. D | Page 21 of 24

OP191/OP291/OP491

The filter section uses a pair of OP491s in a twin-T

3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH

FALSE GROUND

configuration whose frequency selectivity is very sensitive

to the relative matching of the capacitors and resistors in

the twin-T section. Mylar is the material of choice for the

capacitors, and the relative matching of the capacitors and

resistors determines the pass band symmetry of the filter. Using

1% resistors and ±% capacitors produces satisfactory results.

To process ac signals in a single-supply system, it is often best

to use a false ground biasing scheme. Figure 72 illustrates a

circuit that uses this approach. In this circuit, a false-ground

circuit biases an active notch filter used to reject ±0 Hz/60 Hz

power line interference in portable patient monitoring

equipment. Notch filters are quite commonly used to reject

power line frequency interference that often obscures low

frequency physiological signals, such as heart rates, blood

pressure readings, EEGs, and EKGs. This notch filter effectively

squelches 60 Hz pickup at a filter Q of 0.7±. Substituting

3.16 kΩ resistors for the 2.67 kΩ resistors in the twin-T section

(R1 through R±) configures the active filter to reject ±0 Hz

interference.

SINGLE-SUPPLY, HALF-WAVE, AND FULL-WAVE

RECTIFIERS

An OPx91 device configured as a voltage follower operating on

a single supply can be used as a simple half-wave rectifier in low

frequency (<2 kHz) applications. A full-wave rectifier can be

configured with a pair of OP291s, as illustrated in Figure 73.

The circuit works in the following way. When the input signal is

above 0 V, the output of Amplifier A1 follows the input signal.

Because the noninverting input of Amplifier A2 is connected to

the output of A1, op amp loop control forces the inverting input

of the A2 to the same potential. The result is that both terminals

of R1 are equipotential; that is, no current flows. Because there

is no current flow in R1, the same condition exists for R2; thus,

the output of the circuit tracks the input signal. When the input

signal is below 0 V, the output voltage of A1 is forced to 0 V.

This condition now forces A2 to operate as an inverting voltage

follower because the noninverting terminal of A2 is also at 0 V.

The output voltage at V_OUTA is then a full-wave rectified version

of the input signal. If needed, a buffered, half-wave rectified

version of the input signal is available at V_OUTB.

R2

2.67kꢀ

R1

3V

2.67kꢀ

C1

1μF

C2

1μF

11

2

3

1/4

OP491

1

5

V

IN

OUT

R3

R4

2.67kꢀ

1/4

OP491

2.67kꢀ

7

A1

4

6

A2

R5

C3

2μF

(1μF × 2)

R6

100kꢀ

1.33kꢀ

(2.67kꢀ ÷ 2)

R7

1kꢀ

R8

1kꢀ

R11

100kꢀ

C5

3V

R1

100kꢀ

R2

100kꢀ

0.01μF

R9

1Mꢀ

R12

499ꢀ

9

1/4

5V

8

6

5

OP491

V

A

C6

1.5V

1μF

OUT

1/2

OP291

V

10

IN

3

2

7

FULL-WAVE

RECTIFIED

OUTPUT

A3

C4

1μF

2V p-p

<2kHz

1/2

1

A2

OP291

R10

1Mꢀ

4

A1

V

B

HALF-WAVE

RECTIFIED

OUTPUT

Figure 72. A 3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter

with False Ground

1V

500mV

V

IN

Amplifier A3 is the heart of the false ground bias circuit.

It buffers the voltage developed by R9 and R10 and is the

reference for the active notch filter. Because the OP491

exhibits a rail-to-rail input common-mode range, R9 and R10

are chosen to split the 3 V supply symmetrically. An in-the-loop

compensation scheme used around the OP491 allows the op

amp to drive C6, a 1 μF capacitor, without oscillation. C6

maintains a low impedance ac ground over the operating

frequency range of the filter.

100

90

(1V/DIV)

V

A

OUT

(0.5V/DIV)

10

0%

V

B

OUT

(0.5V/DIV)

500mV

TIME (200μs/DIV)

200μs

Figure 73. Single-Supply, Half-Wave, and Full-Wave Rectifiers

Using an OP291

Rev. D | Page 22 of 24

OP191/OP291/OP491

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

8.75 (0.3445)

8.55 (0.3366)

8

1

5

4

14

1

8

7

4.00 (0.1575)

3.80 (0.1496)

6.20 (0.2441)

5.80 (0.2283)

6.20 (0.2440)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

0.50 (0.0197)

0.25 (0.0098)

1.35 (0.0531)

1.75 (0.0689)

1.27 (0.0500)

BSC

0.50 (0.0196)

0.25 (0.0099)

× 45°

0.25 (0.0098)

0.10 (0.0039)

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8°

0.51 (0.0201)

0.31 (0.0122)

0°

SEATING

PLANE

8°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.25 (0.0098)

0.17 (0.0067)

0.51 (0.0201)

0.31 (0.0122)

0° 1.27 (0.0500)

COPLANARITY

0.10

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 76. 14-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-14)

Figure 74. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

[S-Suffix]

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

0.775 (19.69)

0.750 (19.05)

0.735 (18.67)

14

1

8

7

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

14

8

7

4.50

4.40

4.30

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

6.40

BSC

PIN 1

0.100 (2.54)

BSC

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210

(5.33)

MAX

1

0.015

(0.38)

MIN

PIN 1

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.015 (0.38)

GAUGE

0.65

BSC

1.05

1.00

0.80

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

PLANE

SEATING

PLANE

0.20

0.09

1.20

MAX

0.75

0.60

0.45

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.430 (10.92)

MAX

0.005 (0.13)

MIN

8°

0°

0.15

0.05

0.30

0.19

SEATING

PLANE

0.070 (1.78)

0.050 (1.27)

0.045 (1.14)

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

COMPLIANT TO JEDEC STANDARDS MS-001-AA

Figure 77. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Dimensions shown in millimeters

Figure 75. 14-Lead Plastic Dual In-Line Package [PDIP]

(N-14)

[P-Suffix]

Dimensions shown in inches and (millimeters)

Rev. D | Page 23 of 24

OP191/OP291/OP491

ORDERING GUIDE

Model

OP191GS

OP191GS-REEL

OP191GS-REEL7

OP191GSZ¹

OP191GSZ-REEL¹

OP191GSZ-REEL7¹

OP291GS

OP291GS-REEL

OP291GS-REEL7

OP291GSZ¹

OP291GSZ-REEL¹

OP291GSZ-REEL7¹

OP491GP

Temperature Range

−40°C to +125°C

Package Description

8-Lead SOIC

14-Lead PDIP

14-Lead SOIC

14-Lead TSSOP

Package Option

R-8 [S-Suffix]

N-14 [P-Suffix]

R-14 [S-Suffix]

RU-14

OP491GPZ¹

OP491GS

OP491GS-REEL

OP491GS-REEL7

OP491GSZ¹

OP491GSZ-REEL¹

OP491GSZ-REEL7¹

OP491GRU-REEL

OP491GRUZ-REEL¹

OP491GBC

RU-14

DIE

¹Z = Pb-free part.

registered trademarks are the property of their respective owners.

C00294-0-4/06(D)

Rev. D | Page 24 of 24

型号:	OP491GSZ
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP,
针数：	14
Reach Compliance Code：	unknown
风险等级：	5.29
放大器类型：	OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB)：	0.095 µA
标称共模抑制比：	97 dB
最大输入失调电压：	1250 µV
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e3
长度：	8.65 mm
湿度敏感等级：	NOT SPECIFIED
负供电电压上限：	-8 V
标称负供电电压 (Vsup)：	-5 V
功能数量：	4
端子数量：	14
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT APPLICABLE
座面最大高度：	1.75 mm
标称压摆率：	0.5 V/us
子类别：	Operational Amplifier
供电电压上限：	8 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BICMOS
温度等级：	AUTOMOTIVE
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT APPLICABLE
标称均一增益带宽：	3000 kHz
宽度：	3.9 mm
Base Number Matches：	1

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