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  • 北京元坤伟业科技有限公司

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  • OPA2140AIDR
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     该会员已使用本站16年以上
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产品型号OPA2140AIDR的概述

OPA2140AIDR概述 OPA2140AIDR是一款高性能的运算放大器,广泛应用于信号处理和低噪声应用。其设计基于先进的CMOS工艺,具备高增益带宽、高共模抑制比和低功耗的显著特点,使得OPA2140AIDR非常适合用于高精度的测量和数据采集领域。该芯片拥有极低的失调电压和失调漂移,使其在高精度应用中具有优异的稳定性和可靠性。 OPA2140AIDR采用了双通道设计,提供了良好的电源抑制比和广泛的供电电压范围,确保其在多种环境下都能稳定工作。由于其低噪声特性,该芯片适合用于音频信号处理、传感器信号放大及数据采集系统等场合。 OPA2140AIDR详细参数 以下是OPA2140AIDR的一些关键参数: - 供应电压范围: ±2.5V至±18V,或单电源供电3V至36V - 增益带宽积: 10MHz - 输入失调电压: 50µV(典型值) - 输入失调电压漂移: 0.1µV/°C(典型...

产品型号OPA2140AIDR的Datasheet PDF文件预览

OPA140  
OPA2140, OPA4140  
www.ti.com  
SBOS498A JULY 2010REVISED AUGUST 2010  
High-Precision, Low-Noise, Rail-to-Rail Output,  
11MHz JFET Op Amp  
Check for Samples: OPA140, OPA2140, OPA4140  
1
FEATURES  
DESCRIPTION  
2
Very Low Offset Drift: 1mV/°C max  
The OPA140, OPA2140, and OPA4140 op amp  
family is a series of low-power JFET input amplifiers  
that feature good drift and low input bias current. The  
rail-to-rail output swing and input range that includes  
V– allow designers to take advantage of the  
low-noise characteristics of JFET amplifiers while  
also interfacing to modern, single-supply, precision  
Very Low Offset: 120mV  
Low Input Bias Current: 10pA max  
Very Low 1/f Noise: 250nVPP, 0.1Hz to 10Hz  
Low Noise: 5.1nV/Hz  
Slew Rate: 20V/ms  
analog-to-digital  
converters  
(ADCs)  
and  
Low Supply Current: 2.0mA max  
Input Voltage Range Includes V– Supply  
Single-Supply Operation: 4.5V to 36V  
Dual-Supply Operation: ±2.25V to ±18V  
No Phase Reversal  
digital-to-analog converters (DACs).  
The OPA140 achieves 11MHz unity-gain bandwidth  
and 20V/ms slew rate while consuming only 1.8mA  
(typ) of quiescent current. It runs on a single 4.5 to  
36V supply or dual ±2.25V to ±18V supplies.  
All versions are fully specified from –40°C to +125°C  
for use in the most challenging environments. The  
OPA140 (single) is available in the SOT23-5,  
MSOP-8, and SO-8 packages; the OPA2140 (dual) is  
available in both MSOP-8 and SO-8 packages; and  
the OPA4140 (quad) is available in the SO-14 and  
TSSOP-14 packages.  
Industry-Standard SO Packages  
MSOP-8, TSSOP, and SOT23 Packages  
APPLICATIONS  
Battery-Powered Instruments  
Industrial Controls  
Medical Instrumentation  
Photodiode Amplifiers  
Active Filters  
Data Acquisition Systems  
Automatic Test Systems  
RELATED PRODUCTS  
FEATURES  
PRODUCT  
Low-Power, 10MHz FET Input  
Industrial Op Amp  
OPA141  
2.2nV/Hz, Low-Power, 36V  
Operational Amplifier in SOT23  
Package  
OPA209  
OPA827  
0.1Hz to 10Hz NOISE  
Low-Noise, High-Precision, 22MHz,  
4nV/Hz JFET-Input Operational  
Amplifier  
VSUPPLY = ±18V  
Competitor’s Device  
OPAx140  
Low-Noise, Low IQ Precision CMOS  
Operational Amplifier  
OPA376  
OPA132  
High-Speed, FET-Input Operational  
Amplifier  
Time (1s/div)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
OPA140  
OPA2140, OPA4140  
SBOS498A JULY 2010REVISED AUGUST 2010  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating free-air temperature range (unless otherwise noted).  
VALUE  
UNIT  
V
Supply Voltage  
±20  
(V–) –0.5 to (V+) +0.5  
±10  
Voltage(2)  
Current(2)  
V
Signal Input  
Terminals  
mA  
Output Short-Circuit(3)  
Continuous  
Operating Temperature, TA  
Storage Temperature, TA  
Junction Temperature, TJ  
–55 to +150  
–65 to +150  
+150  
°C  
°C  
°C  
V
Human Body Model (HBM)  
Charged Device Model (CDM)  
2000  
ESD Ratings  
500  
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not supported.  
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should  
be current limited to 10 mA or less.  
(3) Short-circuit to VS/2 (ground in symmetrical dual-supply setups), one amplifier per package.  
PACKAGE INFORMATION(1)  
PRODUCT  
PACKAGE-LEAD  
PACKAGE DESIGNATOR  
PACKAGE MARKING  
OPA140  
140  
SO-8  
D
DGK  
DBV  
D
OPA140  
MSOP-8  
SOT23-5  
SO-8  
O140  
O2140A  
2140  
OPA2140  
OPA4140  
MSOP-8  
TSSOP-14  
SO-14  
DGK  
PW  
D
O4140A  
O4140A  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the  
device product folder at www.ti.com.  
2
Copyright © 2010, Texas Instruments Incorporated  
Product Folder Link(s): OPA140 OPA2140 OPA4140  
 
OPA140  
OPA2140, OPA4140  
www.ti.com  
SBOS498A JULY 2010REVISED AUGUST 2010  
ELECTRICAL CHARACTERISTICS: VS = +4.5V to +36V; ±2.25V to ±18V  
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.  
At TA = +25°C, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
OPA140, OPA2140, OPA4140  
PARAMETER  
OFFSET VOLTAGE  
Offset Voltage, RTI  
Over Temperature  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VOS  
VS = ±18V  
VS = ±18V  
30  
120  
220  
1.0  
mV  
mV  
Drift  
dVOS/dT  
VS = ±18V  
±0.35  
mV/°C  
mV/V  
mV/V  
vs Power Supply  
xxxOver Temperature  
INPUT BIAS CURRENT(1)  
Input Bias Current  
Over Temperature  
Input Offset Current  
Over Temperature  
NOISE  
PSRR  
VS = ±2.25V to ±18V  
VS = ±2.25V to ±18V  
±0.1  
±0.5  
±4  
IB  
±0.5  
±0.5  
±10  
±3  
pA  
nA  
pA  
nA  
IOS  
±10  
±1  
Input Voltage Noise  
f = 0.1Hz to 10Hz  
f = 0.1Hz to 10Hz  
Input Voltage Noise Density  
f = 10Hz  
250  
42  
nVPP  
nVRMS  
en  
8
nV/Hz  
nV/Hz  
nV/Hz  
f = 100Hz  
5.8  
5.1  
f = 1kHz  
Input Current Noise Density  
f = 1kHz  
In  
0.8  
fA/Hz  
INPUT VOLTAGE RANGE  
Common-Mode Voltage Range  
VCM  
(V–) –0.1  
(V+)–3.5  
V
VS = ±18V, VCM = (V–) –0.1V  
to (V+) – 3.5V  
Common-Mode Rejection Ratio  
CMRR  
126  
140  
dB  
VS = ±18V, VCM = (V–) –0.1V  
to (V+) – 3.5V  
Over Temperature  
120  
dB  
INPUT IMPEDANCE  
Differential  
1013 || 10  
1013 || 7  
Ω || pF  
Ω || pF  
Common-Mode  
OPEN-LOOP GAIN  
VCM = (V–) –0.1V to (V+) –3.5V  
VO = (V–)+0.35V to (V+)–0.35V, RL  
=
Open-Loop Voltage Gain  
AOL  
120  
126  
126  
dB  
10kΩ  
VO = (V–)+0.35V to (V+)–0.35V, RL = 2kΩ  
VO = (V–)+0.35V to (V+)–0.35V, RL = 2kΩ  
114  
dB  
Over Temperature  
FREQUENCY RESPONSE  
Gain Bandwidth Product  
Slew Rate  
108  
dB  
BW  
11  
20  
MHz  
V/ms  
ns  
Settling Time, 12-bit (0.024)  
Settling Time, 16-bit  
THD+N  
880  
1.6  
ms  
1kHz, G = 1, VO = 3.5VRMS  
0.00005  
600  
%
Overload Recovery Time  
ns  
(1) High-speed test, TA = TJ.  
Copyright © 2010, Texas Instruments Incorporated  
3
Product Folder Link(s): OPA140 OPA2140 OPA4140  
OPA140  
OPA2140, OPA4140  
SBOS498A JULY 2010REVISED AUGUST 2010  
www.ti.com  
ELECTRICAL CHARACTERISTICS: VS = +4.5V to +36V; ±2.25V to ±18V (continued)  
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.  
At TA = +25°C, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
OPA140, OPA2140, OPA4140  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OUTPUT  
Voltage Output  
VO  
RL = 10kΩ, AOL 108dB  
RL = 2kΩ, AOL 108dB  
Source  
(V–)+0.2  
(V+)–0.2  
V
V
(V–)+0.35  
(V+)–0.35  
Short-Circuit Current  
ISC  
+36  
–30  
mA  
mA  
Sink  
Capacitive Load Drive  
Open-Loop Output Impedance  
POWER SUPPLY  
CLOAD  
RO  
See Figure 20 and Figure 21  
16  
f = 1MHz, IO = 0 (See Figure 19)  
Ω
Specified Voltage Range  
VS  
IQ  
±2.25  
±18  
2.0  
2.7  
V
Quiescent Current  
(per amplifier)  
IO = 0mA  
1.8  
mA  
mA  
Over Temperature  
CHANNEL SEPARATION  
Channel Separation  
At dc  
0.02  
10  
mV/V  
mV/V  
At 100kHz  
TEMPERATURE RANGE  
Specified Range  
–40  
–55  
+125  
+150  
°C  
°C  
Operating Range  
THERMAL INFORMATION  
OPA140,  
OPA2140  
OPA140,  
OPA2140  
OPA140  
THERMAL METRIC(1)  
UNITS  
D (SO)  
8
DGK (MSOP)  
DBV (SOT23)  
8
5
qJA  
Junction-to-ambient thermal resistance  
Junction-to-case(top) thermal resistance  
Junction-to-board thermal resistance  
160  
75  
180  
55  
210  
200  
110  
40  
qJC(top)  
qJB  
60  
130  
n/a  
120  
n/a  
°C/W  
yJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case(bottom) thermal resistance  
9
yJB  
50  
105  
n/a  
qJC(bottom)  
n/a  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
THERMAL INFORMATION  
OPA4140  
OPA4140  
THERMAL METRIC(1)  
D (SO)  
14  
PW (TSSOP)  
UNITS  
14  
135  
45  
qJA  
Junction-to-ambient thermal resistance  
97  
qJC(top)  
qJB  
Junction-to-case(top) thermal resistance  
Junction-to-board thermal resistance  
56  
53  
66  
°C/W  
yJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case(bottom) thermal resistance  
19  
n/a  
60  
yJB  
46  
qJC(bottom)  
n/a  
n/a  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
4
Copyright © 2010, Texas Instruments Incorporated  
Product Folder Link(s): OPA140 OPA2140 OPA4140  
OPA140  
OPA2140, OPA4140  
www.ti.com  
SBOS498A JULY 2010REVISED AUGUST 2010  
PIN ASSIGNMENTS  
OPA140  
SO-8, MSOP-8  
(TOP VIEW)  
OPA2140  
SO-8, MSOP-8  
(TOP VIEW)  
(1)  
(1)  
NC  
1
2
3
4
8
7
6
5
NC  
V+  
OUT A  
-In A  
+In A  
V-  
1
2
3
4
8
7
6
5
V+  
-In  
+In  
V-  
A
Out B  
-In B  
+In B  
Out  
B
(1)  
NC  
(1) NC denotes no internal connection.  
OPA4140  
SO-14, TSSOP-14  
(TOP VIEW)  
OPA140  
SOT23-5  
(TOP VIEW)  
Out A  
Out D  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
-In A  
+In A  
V+  
-In D  
+In D  
V-  
V+  
OUT  
V-  
1
2
3
5
4
A
D
-IN  
+IN  
+ In B  
-In B  
Out B  
+ In C  
-In C  
Out C  
B
C
8
SIMPLIFIED BLOCK DIAGRAM  
V+  
Pre-Output Driver  
OUT  
IN-  
IN+  
V-  
Figure 1.  
Copyright © 2010, Texas Instruments Incorporated  
5
Product Folder Link(s): OPA140 OPA2140 OPA4140  
 
OPA140  
OPA2140, OPA4140  
SBOS498A JULY 2010REVISED AUGUST 2010  
www.ti.com  
TYPICAL CHARACTERISTICS SUMMARY  
TABLE OF GRAPHS  
Table 1. Characteristic Performance Measurements  
DESCRIPTION  
FIGURE  
Figure 2  
Offset Voltage Production Distribution  
Offset Voltage Drift Distribution  
Figure 3  
Offset Voltage vs Common-Mode Voltage (Max Supply)  
IB vs Common-Mode Voltage  
Figure 4  
Figure 6  
Input Offset Voltage vs Temperature  
Output Voltage Swing vs Output Current  
CMRR and PSRR vs Frequency (RTI)  
Common-Mode Rejection Ratio vs Temperature  
0.1Hz to 10Hz Noise  
Figure 5  
Figure 7  
Figure 8  
Figure 9  
Figure 10  
Figure 11  
Figure 12  
Figure 13  
Figure 14  
Figure 15  
Figure 16  
Figure 17  
Figure 18  
Figure 19  
Figure 20  
Figure 21  
Figure 22  
Figure 24  
Figure 25  
Figure 26, Figure 27  
Figure 28  
Figure 29  
Figure 30  
Figure 31  
Figure 32  
Figure 23  
Figure 33  
Input Voltage Noise Density vs Frequency  
THD+N Ratio vs Frequency (80kHz AP Bandwidth)  
THD+N Ratio vs Output Amplitude  
Quiescent Current vs Temperature  
Quiescent Current vs Supply Voltage  
Gain and Phase vs Frequency  
Closed-Loop Gain vs Frequency  
Open-Loop Gain vs Temperature  
Open-Loop Output Impedance vs Frequency  
Small-Signal Overshoot vs Capacitive Load (G = +1)  
Small-Signal Overshoot vs Capacitive Load (G = –1)  
No Phase Reversal  
Positive Overload Recovery  
Negative Overload Recovery  
Large-Signal Positive and Negative Settling Time  
Small-Signal Step Response (G = +1)  
Small-Signal Step Response (G = –1)  
Large-Signal Step Response (G = +1)  
Large-Signal Step Response (G = –1)  
Short-Circuit Current vs Temperature  
Maximum Output Voltage vs Frequency  
Channel Separation vs Frequency  
6
Copyright © 2010, Texas Instruments Incorporated  
Product Folder Link(s): OPA140 OPA2140 OPA4140  
OPA140  
OPA2140, OPA4140  
www.ti.com  
SBOS498A JULY 2010REVISED AUGUST 2010  
TYPICAL CHARACTERISTICS  
At TA = +25°C, VS = ±18V, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
OFFSET VOLTAGE PRODUCTION DISTRIBUTION  
OFFSET VOLTAGE DRIFT DISTRIBUTION  
Offset Voltage (mV)  
Offset Voltage Drift (mV/°C)  
Figure 2.  
Figure 3.  
INPUT OFFSET VOLTAGE vs TEMPERATURE  
(144 Amplifiers)  
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE  
160  
120  
80  
120  
18 Typical Units Shown  
100  
80  
60  
40  
40  
20  
0
0
-20  
-40  
-60  
-80  
-100  
-120  
-40  
-80  
-120  
-160  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
-18  
-12  
-6  
0
6
12  
18  
Temperature (?C)  
VCM (V)  
Figure 4.  
Figure 5.  
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT  
(MAX SUPPLY)  
IB vs COMMON-MODE VOLTAGE  
18.0  
10  
8
17.5  
17.0  
16.5  
16.0  
Specified Common-Mode  
Voltage Range  
+14.5V  
-0.1V  
6
+25°C  
-40°C  
+85°C  
+125°C  
4
-16.0  
-16.5  
-17.0  
-17.5  
-18.0  
+IB  
2
-IB  
-18 -15 -12 -9 -6 -3  
0
0
10  
20  
30  
40  
50  
60  
70  
0
3
6
9
12 15 18  
Output Current (mA)  
VCM (V)  
Figure 6.  
Figure 7.  
Copyright © 2010, Texas Instruments Incorporated  
7
Product Folder Link(s): OPA140 OPA2140 OPA4140  
 
OPA140  
OPA2140, OPA4140  
SBOS498A JULY 2010REVISED AUGUST 2010  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = ±18V, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
CMRR AND PSRR vs FREQUENCY (Referred to Input)  
COMMON-MODE REJECTION RATIO vs TEMPERATURE  
180  
CMRR  
160  
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0
140  
120  
100  
-PSRR  
80  
+PSRR  
60  
40  
20  
0
1
10  
100  
1k  
10k 100k  
1M  
10M 100M  
-75  
75  
-50 -25  
0
25  
50  
100 125 150  
Frequency (Hz)  
Temperature (°C)  
Figure 8.  
Figure 9.  
0.1Hz to 10Hz NOISE  
INPUT VOLTAGE NOISE DENSITY vs FREQUENCY  
100  
10  
1
Time (1s/div)  
0.1  
1
10  
100  
1k  
10k  
100k  
Frequency (Hz)  
Figure 10.  
Figure 11.  
THD+N RATIO vs FREQUENCY  
THD+N RATIO vs OUTPUT AMPLITUDE  
0.01  
-80  
0.001  
-100  
BW = 80kHz  
1kHz Signal  
RL = 2kW  
G = -1  
VOUT = 3VRMS  
G = +1  
BW = 80kHz  
RL = 2kW  
G = -1  
0.001  
0.0001  
-100  
-120  
-140  
0.0001  
-120  
G = +1  
NOTE: Increase at low signal levels is a result  
of increased % contribution of noise.  
0.00001  
0.00001  
-140  
0.1  
1
10  
100  
10  
100  
1k  
10k 20k  
Frequency (Hz)  
Frequency (Hz)  
Figure 12.  
Figure 13.  
8
Copyright © 2010, Texas Instruments Incorporated  
Product Folder Link(s): OPA140 OPA2140 OPA4140  
OPA140  
OPA2140, OPA4140  
www.ti.com  
SBOS498A JULY 2010REVISED AUGUST 2010  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = ±18V, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
QUIESCENT CURRENT vs TEMPERATURE  
QUIESCENT CURRENT vs SUPPLY VOLTAGE  
2.5  
2.0  
1.5  
1.0  
0.5  
0
2.00  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0
OPA140  
Specified Supply-Voltage Range  
-75 -50 -25  
0
25  
50  
75  
100 125 150  
0
4
8
12  
16  
20  
24  
28  
32  
36  
Temperature (°C)  
Supply Voltage (V)  
Figure 14.  
Figure 15.  
GAIN AND PHASE vs FREQUENCY  
CLOSED-LOOP GAIN vs FREQUENCY  
140  
120  
100  
80  
180  
135  
90  
40  
30  
CL = 30pF  
G = +10  
Gain  
20  
10  
G = +1  
60  
0
40  
-10  
-20  
-30  
-40  
Phase  
20  
45  
G = -1  
0
-20  
0
10  
100  
1k  
10k  
100k  
1M  
10M  
100M  
100k  
1M  
10M  
100M  
Frequency (Hz)  
Frequency (Hz)  
Figure 16.  
Figure 17.  
OPEN-LOOP GAIN vs TEMPERATURE  
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY  
1k  
0
10kW Load  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-1.2  
-1.4  
100  
10  
1
2kW Load  
10  
100  
1k  
10k  
100k  
1M  
10M  
100M  
-75 -50 -25  
0
25  
50  
75  
100 125 150  
Temperature (°C)  
Frequency (Hz)  
Figure 18.  
Figure 19.  
Copyright © 2010, Texas Instruments Incorporated  
9
Product Folder Link(s): OPA140 OPA2140 OPA4140  
OPA140  
OPA2140, OPA4140  
SBOS498A JULY 2010REVISED AUGUST 2010  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = ±18V, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
SMALL-SIGNAL OVERSHOOT  
SMALL-SIGNAL OVERSHOOT  
vs CAPACITIVE LOAD (100mV Output Step)  
vs CAPACITIVE LOAD (100mV Output Step)  
40  
35  
30  
25  
20  
15  
10  
5
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
ROUT = 0W  
G = +1  
+15V  
ROUT  
ROUT = 0W  
OPA140  
RL  
CL  
ROUT = 24W  
-15V  
ROUT = 24W  
ROUT = 51W  
RF = 2kW  
RI = 2kW  
G = -1  
+15V  
ROUT  
ROUT = 51W  
OPA140  
CL  
-15V  
0
0
0
200  
400  
600  
800 1000 1200 1400 1600  
0
500  
1000  
1500  
2000  
Capacitive Load (pF)  
Capacitive Load (pF)  
Figure 20.  
Figure 21.  
NO PHASE REVERSAL  
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY  
35  
30  
25  
20  
15  
10  
5
Maximum output  
voltage range  
VS = ±15V  
without slew-rate  
induced distortion  
Output  
+18V  
OPA140  
VS = ±5V  
Output  
-18V  
37VPP  
VS = ±2.25V  
Sine Wave  
(±18.5V)  
0
Time (0.4ms/div)  
10k  
100k  
Frequency (Hz)  
1M  
10M  
Figure 22.  
Figure 23.  
POSITIVE OVERLOAD RECOVERY  
NEGATIVE OVERLOAD RECOVERY  
VOUT  
VIN  
20kW  
20kW  
2kW  
2kW  
VIN  
VOUT  
OPA140  
VOUT  
OPA140  
VIN  
VIN  
VOUT  
G = -10  
G = -10  
Time (0.4ms/div)  
Time (0.4ms/div)  
Figure 24.  
Figure 25.  
10  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = ±18V, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
LARGE-SIGNAL POSITIVE SETTLING TIME  
(10V Step)  
LARGE-SIGNAL NEGATIVE SETTLING TIME  
(10V Step)  
1000  
800  
1000  
800  
600  
600  
400  
400  
16-bit Settling  
16-bit Settling  
200  
200  
0
0
-200  
-400  
-600  
-800  
-1000  
-200  
-400  
-600  
-800  
-1000  
( 1/2LSB = 0.00075%)  
( 1/2LSB = 0.00075%)  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
Time (ms)  
Time (ms)  
Figure 26.  
Figure 27.  
SMALL-SIGNAL STEP RESPONSE  
(100mV)  
SMALL-SIGNAL STEP RESPONSE  
(100mV)  
CL = 100pF  
CL = 100pF  
G = +1  
+15V  
OPA140  
-15V  
RI = 2kW RF = 2kW  
+15V  
OPA140  
RL  
CL  
CL  
-15V  
G = -1  
Time (100ns/div)  
Time (100ns/div)  
Figure 28.  
Figure 29.  
LARGE-SIGNAL STEP RESPONSE  
LARGE-SIGNAL STEP RESPONSE  
G = +1  
CL = 100pF  
G = -1  
CL = 100pF  
Time (400ns/div)  
Time (400ns/div)  
Figure 30.  
Figure 31.  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, VS = ±18V, RL = 2kconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.  
SHORT-CIRCUIT CURRENT vs TEMPERATURE  
CHANNEL SEPARATION vs FREQUENCY  
60  
50  
40  
30  
20  
10  
0
-90  
-100  
-110  
-120  
-130  
-140  
-150  
VOUT = 3VRMS  
G = +1  
ISC, Source  
ISC, Sink  
RL = 2kW  
Short-circuiting causes thermal shutdown;  
RL = 5kW  
see Applications Information section.  
-75 -50 -25  
0
25  
50  
75  
100 125 150  
10  
100  
1k  
10k  
100k  
Temperature (°C)  
Frequency (Hz)  
Figure 32.  
Figure 33.  
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SBOS498A JULY 2010REVISED AUGUST 2010  
APPLICATION INFORMATION  
with total circuit noise calculated. The op amp itself  
contributes both a voltage noise component and a  
current noise component. The voltage noise is  
commonly modeled as a time-varying component of  
the offset voltage. The current noise is modeled as  
the time-varying component of the input bias current  
and reacts with the source resistance to create a  
voltage component of noise. Therefore, the lowest  
noise op amp for a given application depends on the  
source impedance. For low source impedance,  
current noise is negligible, and voltage noise  
generally dominates. The OPA140, OPA2140, and  
OPA4140 family has both low voltage noise and  
extremely low current noise because of the FET input  
of the op amp. As a result, the current noise  
contribution of the OPAx140 series is negligible for  
any practical source impedance, which makes it the  
better choice for applications with high source  
impedance.  
The OPA140, OPA2140, and OPA4140 are unity-gain  
stable, operational amplifiers with very low noise,  
input bias current, and input offset voltage.  
Applications with noisy or high-impedance power  
supplies require decoupling capacitors placed close  
to the device pins. In most cases, 0.1mF capacitors  
are adequate. Figure 1 shows a simplified schematic  
of the OPA140.  
OPERATING VOLTAGE  
The OPA140, OPA2140, and OPA4140 series of op  
amps can be used with single or dual supplies from  
an operating range of VS = +4.5V (±2.25V) and up to  
VS = +36V (±18V). These devices do not require  
symmetrical supplies; they only require a minimum  
supply voltage of +4.5V (±2.25V). For VS less than  
±3.5V, the common-mode input range does not  
include midsupply. Supply voltages higher than +40V  
can permanently damage the device; see the  
Absolute Maximum Ratings table. Key parameters  
are specified over the operating temperature range,  
TA = –40°C to +125°C. Key parameters that vary over  
the supply voltage or temperature range are shown in  
the Typical Characteristics section of this data sheet.  
The equation in Figure 34 shows the calculation of  
the total circuit noise, with these parameters:  
en = voltage noise  
In = current noise  
RS = source impedance  
k = Boltzmann's constant = 1.38 × 10–23 J/K  
T = temperature in degrees Kelvin (K)  
CAPACITIVE LOAD AND STABILITY  
The dynamic characteristics of the OPAx140 have  
been optimized for commonly encountered gains,  
loads, and operating conditions. The combination of  
low closed-loop gain and high capacitive loads  
decreases the phase margin of the amplifier and can  
lead to gain peaking or oscillations. As a result,  
heavier capacitive loads must be isolated from the  
output. The simplest way to achieve this isolation is to  
add a small resistor (ROUT equal to 50Ω, for example)  
in series with the output.  
For more details on calculating noise, see the section  
on Basic Noise Calculations.  
10k  
EO  
OPA211  
1k  
RS  
100  
Figure 20 and Figure 21 illustrate graphs of  
Small-Signal Overshoot vs Capacitive Load for  
several values of ROUT. Also, refer to Applications  
Bulletin AB-028 (literature number SBOA015,  
available for download from the TI web site) for  
details of analysis techniques and application circuits.  
OPA140  
Resistor Noise  
10  
2
2
2
EO = en + (in RS) + 4kTRS  
1
100  
1k  
10k  
100k  
1M  
Source Resistance, RS (W)  
NOISE PERFORMANCE  
Figure 34. Noise Performance of the OPA140 and  
OPA211 in Unity-Gain Buffer Configuration  
Figure 34 shows the total circuit noise for varying  
source impedances with the operational amplifier in a  
unity-gain configuration (with no feedback resistor  
network and therefore no additional noise  
contributions). The OPA140 and OPA211 are shown  
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BASIC NOISE CALCULATIONS  
Figure 35 illustrates both noninverting (A) and  
inverting (B) op amp circuit configurations with gain.  
In circuit configurations with gain, the feedback  
network resistors also contribute noise. In general,  
the current noise of the op amp reacts with the  
feedback resistors to create additional noise  
components. However, the extremely low current  
noise of the OPAx140 means that its current noise  
contribution can be neglected.  
Low-noise circuit design requires careful analysis of  
all noise sources. External noise sources can  
dominate in many cases; consider the effect of  
source resistance on overall op amp noise  
performance. Total noise of the circuit is the  
root-sum-square  
components.  
combination  
of  
all  
noise  
The resistive portion of the source impedance  
produces thermal noise proportional to the square  
root of the resistance. This function is plotted in  
Figure 34. The source impedance is usually fixed;  
consequently, select the op amp and the feedback  
resistors to minimize the respective contributions to  
the total noise.  
The feedback resistor values can generally be  
chosen to make these noise sources negligible. Note  
that low impedance feedback resistors load the  
output of the amplifier. The equations for total noise  
are shown for both configurations.  
space  
A) Noise in Noninverting Gain Configuration  
Noise at the output:  
R2  
2
2
2
R2  
R1  
R2  
R1  
R2  
R1  
2
EO  
2
en  
2
2
es  
e12 + e2  
+
R1  
1 +  
1 +  
=
+
EO  
4kTRS  
4kTR1  
4kTR2  
Where eS =  
e1 =  
= thermal noise of RS  
= thermal noise of R1  
= thermal noise of R2  
RS  
VS  
e2 =  
B) Noise in Inverting Gain Configuration  
Noise at the output:  
R2  
2
2
2
R2  
R2  
R2  
R1 + RS  
EO2 = 1 +  
2
2
2
en  
+
e12 + e2  
+
es  
R1  
R1 + RS  
R1 + RS  
EO  
RS  
4kTRS  
4kTR1  
4kTR2  
Where eS =  
e1 =  
= thermal noise of RS  
= thermal noise of R1  
= thermal noise of R2  
VS  
e2 =  
For the OPAx140 series of operational amplifiers at 1kHz, en = 5.1nV/Hz.  
Figure 35. Noise Calculation in Gain Configurations  
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PHASE-REVERSAL PROTECTION  
Although the output current is limited by internal  
protection circuitry, accidental shorting of one or more  
output channels of a device can result in excessive  
heating. For instance, when an output is shorted to  
mid-supply, the typical short-circuit current of 36mA  
leads to an internal power dissipation of over 600mW  
at a supply of ±18V.  
The OPA140, OPA2140, and OPA4140 family has  
internal phase-reversal protection. Many FET- and  
bipolar-input op amps exhibit a phase reversal when  
the input is driven beyond its linear common-mode  
range. This condition is most often encountered in  
noninverting circuits when the input is driven beyond  
the specified common-mode voltage range, causing  
the output to reverse into the opposite rail. The input  
circuitry of the OPA140, OPA2140, and OPA4140  
In the case of a dual OPA2140 in an MSOP-8  
package (thermal resistance qJA = 180°C/W), such  
power dissipation would lead the die temperature to  
be 220°C above ambient temperature, when both  
channels are shorted. This temperature increase  
significantly decreases the operating life of the  
device.  
prevents  
phase  
reversal  
with  
excessive  
common-mode voltage; instead, the output limits into  
the appropriate rail (see Figure 22).  
OUTPUT CURRENT LIMIT  
In order to prevent excessive heating, the OPAx140  
series has an internal thermal shutdown circuit, which  
shuts down the device if the die temperature exceeds  
approximately +180°C. Once this thermal shutdown  
circuit activates, a built-in hysteresis of 15°C ensures  
that the die temperature must drop to approximately  
+165°C before the device switches on again.  
The output current of the OPAx140 series is limited  
by  
internal  
circuitry  
to  
+36mA/–30mA  
(sourcing/sinking), to protect the device if the output  
is accidentally shorted. This short-circuit current  
depends on temperature, as shown in Figure 32.  
POWER DISSIPATION AND THERMAL  
PROTECTION  
Additional consideration should be given to the  
combination of maximum operating voltage,  
maximum operating temperature, load, and package  
type. Figure 36 and Figure 37 show several practical  
considerations when evaluating the OPA2140 (dual  
version) and the OPA4140 (quad version).  
The OPAx140 series of op amps are capable of  
driving 2kΩ loads with power-supply voltages of up to  
±18V over the specified temperature range. In a  
single-supply configuration, where the load is  
connected to the negative supply voltage, the  
minimum load resistance is 2.8kΩ at a supply voltage  
of +36V. For lower supply voltages (either  
single-supply or symmetrical supplies), a lower load  
resistance may be used, as long as the output current  
does not exceed 13mA; otherwise, the device  
short-circuit current protection circuit may activate.  
As an example, the OPA4140 has a maximum total  
quiescent current of 10.8mA (2.7mA/channel) over  
temperature. The TSSOP-14 package has a typical  
thermal resistance of 135°C/W. This parameter  
means that because the junction temperature should  
not exceed +150°C in order to ensure reliable  
operation, either the supply voltage must be reduced,  
or the ambient temperature should remain low  
enough so that the junction temperature does not  
exceed +150°C. This condition is illustrated in  
Figure 36 for various package types. Moreover,  
resistive loading of the output causes additional  
power dissipation and thus self-heating, which also  
must be considered when establishing the maximum  
supply voltage or operating temperature. To this end,  
Figure 37 shows the maximum supply voltage versus  
temperature for a worst-case dc load resistance of  
2kΩ.  
Internal power dissipation increases when operating  
at high supply voltages. Copper leadframe  
construction used in the OPA140, OPA2140, and  
OPA4140 series devices improves heat dissipation  
compared to conventional materials. Printed circuit  
board (PCB) layout can also help reduce a possible  
increase in junction temperature. Wide copper traces  
help dissipate the heat by acting as an additional  
heatsink. Temperature rise can be further minimized  
by soldering the devices directly to the PCB rather  
than using a socket.  
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particular semiconductor fabrication process and  
specific circuits connected to the pin. Additionally,  
internal electrostatic discharge (ESD) protection is  
built into these circuits to protect them from  
accidental ESD events both before and during  
product assembly.  
MAXIMUM SUPPLY VOLTAGE  
(Quiescent Condition)  
20  
18  
16  
14  
12  
10  
8
It is helpful to have a good understanding of this  
basic ESD circuitry and its relevance to an electrical  
overstress event. See Figure 38 for an illustration of  
the ESD circuits contained in the OPAx140 series  
(indicated by the dashed line area). The ESD  
protection circuitry involves several current-steering  
diodes connected from the input and output pins and  
routed back to the internal power-supply lines, where  
they meet at an absorption device internal to the  
operational amplifier. This protection circuitry is  
intended to remain inactive during normal circuit  
operation.  
6
TSSOP Quad  
SOIC Quad  
MSOP Dual  
SOIC Dual  
4
2
0
80  
90  
100  
110  
120  
130  
140  
150  
160  
Ambient Temperature (?C)  
Figure 36. Maximum Supply Voltage vs  
Temperature (OPA2140 and OPA4140), Quiescent  
Condition  
An ESD event produces  
a
short duration,  
high-voltage pulse that is transformed into a short  
duration, high-current pulse as it discharges through  
a semiconductor device. The ESD protection circuits  
are designed to provide a current path around the  
operational amplifier core to prevent it from being  
damaged. The energy absorbed by the protection  
circuitry is then dissipated as heat.  
MAXIMUM SUPPLY VOLTAGE  
(Maximum DC Load on All Channels)  
20  
18  
16  
14  
12  
10  
8
When an ESD voltage develops across two or more  
of the amplifier device pins, current flows through one  
or more of the steering diodes. Depending on the  
path that the current takes, the absorption device  
may activate. The absorption device has a trigger, or  
threshold voltage, that is above the normal operating  
voltage of the OPAx140 but below the device  
breakdown voltage level. Once this threshold is  
exceeded, the absorption device quickly activates  
and clamps the voltage across the supply rails to a  
safe level.  
6
TSSOP Quad  
SOIC Quad  
MSOP Dual  
SOIC Dual  
4
2
0
80  
90  
100  
110  
120  
130  
140  
150  
160  
Ambient Temperature (?C)  
When the operational amplifier connects into a circuit  
such as the one Figure 38 shows, the ESD protection  
components are intended to remain inactive and not  
become involved in the application circuit operation.  
However, circumstances may arise where an applied  
voltage exceeds the operating voltage range of a  
given pin. Should this condition occur, there is a risk  
that some of the internal ESD protection circuits may  
be biased on, and conduct current. Any such current  
flow occurs through steering diode paths and rarely  
involves the absorption device.  
Figure 37. Maximum Supply Voltage vs  
Temperature (OPA2140 and OPA4140), Maximum  
DC Load  
ELECTRICAL OVERSTRESS  
Designers often ask questions about the capability of  
an operational amplifier to withstand electrical  
overstress. These questions tend to focus on the  
device inputs, but may involve the supply voltage pins  
or even the output pin. Each of these different pin  
functions have electrical stress limits determined by  
the voltage breakdown characteristics of the  
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Figure 38 depicts a specific example where the input  
voltage, VIN, exceeds the positive supply voltage  
(+VS) by 500mV or more. Much of what happens in  
the circuit depends on the supply characteristics. If  
+VS can sink the current, one of the upper input  
steering diodes conducts and directs current to +VS.  
Excessively high current levels can flow with  
increasingly higher VIN. As a result, the datasheet  
specifications recommend that applications limit the  
input current to 10mA.  
Again, it depends on the supply characteristic while at  
0V, or at a level below the input signal amplitude. If  
the supplies appear as high impedance, then the  
operational amplifier supply current may be supplied  
by the input source via the current steering diodes.  
This state is not a normal bias condition; the amplifier  
most likely will not operate normally. If the supplies  
are low impedance, then the current through the  
steering diodes can become quite high. The current  
level depends on the ability of the input source to  
deliver current, and any resistance in the input path.  
If the supply is not capable of sinking the current, VIN  
may begin sourcing current to the operational  
amplifier, and then take over as the source of positive  
supply voltage. The danger in this case is that the  
voltage can rise to levels that exceed the operational  
amplifier absolute maximum ratings.  
If there is an uncertainty about the ability of the  
supply to absorb this current, external zener diodes  
may be added to the supply pins as shown in  
Figure 38. The zener voltage must be selected such  
that the diode does not turn on during normal  
operation.  
Another common question involves what happens to  
the amplifier if an input signal is applied to the input  
while the power supplies +VS and/or –VS are at 0V.  
However, its zener voltage should be low enough so  
that the zener diode conducts if the supply pin begins  
to rise above the safe operating supply voltage level.  
(2)  
TVS  
RF  
+VS  
+V  
OPA140  
RI  
ESD Current-  
Steering Diodes  
-In  
(3)  
Out  
Op Amp  
Core  
RS  
+In  
Edge-Triggered ESD  
Absorption Circuit  
RL  
ID  
(1)  
VIN  
-V  
-VS  
(2)  
TVS  
(1) VIN = +VS + 500mV.  
(2) TVS: +VS(max) > VTVSBR (Min) > +VS  
(3) Suggested value approximately 1kΩ.  
Figure 38. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application  
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PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
Samples Not Available  
Samples Not Available  
Samples Not Available  
Samples Not Available  
Samples Not Available  
Samples Not Available  
Samples Not Available  
Purchase Samples  
OPA140AID  
OPA140AIDBVR  
OPA140AIDBVT  
OPA140AIDGKT  
OPA140AIDR  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
ACTIVE  
SOIC  
SOT-23  
SOT-23  
MSOP  
SOIC  
D
8
5
5
8
8
8
8
8
75  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
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DBV  
DBV  
DGK  
D
3000  
250  
250  
2500  
OPA140IDGKR  
OPA2140AID  
MSOP  
SOIC  
DGK  
D
75  
OPA2140AIDGKR  
MSOP  
DGK  
2500  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
OPA2140AIDGKT  
ACTIVE  
MSOP  
DGK  
8
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
Request Free Samples  
OPA2140AIDR  
OPA4140AID  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
SOIC  
SOIC  
D
D
8
2500  
50  
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
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Samples Not Available  
Samples Not Available  
Samples Not Available  
Samples Not Available  
Samples Not Available  
14  
14  
14  
14  
OPA4140AIDR  
OPA4140AIPW  
OPA4140AIPWR  
SOIC  
D
2500  
90  
TSSOP  
TSSOP  
PW  
PW  
2000  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
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11-Oct-2010  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
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dsp.ti.com  
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www.ti.com/computers  
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www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
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Energy  
www.ti.com/consumer-apps  
www.ti.com/energy  
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www.ti.com/industrial  
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Microcontrollers  
RFID  
power.ti.com  
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www.ti.com/medical  
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www.ti-rfid.com  
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配单直通车
OPA2140AIDR产品参数
型号:OPA2140AIDR
Brand Name:Texas Instruments
是否无铅:不含铅
是否Rohs认证:符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SOIC
包装说明:SOIC-8
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.33.00.01
Factory Lead Time:6 weeks
风险等级:1.13
Is Samacsys:N
放大器类型:OPERATIONAL AMPLIFIER
架构:VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB):0.00001 µA
25C 时的最大偏置电流 (IIB):0.00001 µA
最小共模抑制比:126 dB
标称共模抑制比:140 dB
频率补偿:YES
最大输入失调电流 (IIO):0.001 µA
最大输入失调电压:120 µV
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:4.9 mm
低-偏置:YES
低-失调:YES
微功率:NO
湿度敏感等级:2
负供电电压上限:-20 V
标称负供电电压 (Vsup):-18 V
功能数量:2
端子数量:8
最高工作温度:125 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
包装方法:TR
峰值回流温度(摄氏度):260
功率:NO
电源:+-2.25/+-18/4.5/36 V
可编程功率:NO
认证状态:Not Qualified
座面最大高度:1.75 mm
标称压摆率:20 V/us
子类别:Operational Amplifier
最大压摆率:2 mA
供电电压上限:20 V
标称供电电压 (Vsup):18 V
表面贴装:YES
温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
标称均一增益带宽:11000 kHz
最小电压增益:251000
宽带:NO
宽度:3.9 mm
Base Number Matches:1
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