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OPA2683

P

A

2

6

8

3

O

P

A

2

6

8

3

www.ti.com

SBOS244H – MAY 2002 – REVISED JULY 2009

Very Low-Power, Dual, Current-Feedback

Operational Amplifier

APPLICATIONS

FEATURES

● LOW-POWER BROADCAST VIDEO DRIVERS

● µPOWER ACTIVE FILTERS

● REDUCED BANDWIDTH CHANGE VERSUS GAIN

● 150MHz BANDWIDTH G = +2

● SHORT-LOOP ADSL CO DRIVERS

● MULTICHANNEL SUMMING AMPLIFIERS

● PROFESSIONAL CAMERAS

● > 80MHz BANDWIDTH TO GAIN > +10

● LOW DISTORTION: < –65dBc at 5MHz

● HIGH OUTPUT CURRENT: 110mA

● DIFFERENTIAL ADC INPUT DRIVERS

● SINGLE-SUPPLY OPERATION: +5V to +12V

● DUAL-SUPPLY OPERATION: ±2.5V to ±6V

● LOW SUPPLY CURRENT: 1.9mA Total

● POWER SHUTDOWN VERSION: MSOP-10

flexibility allows frequency response peaking elements to be

added, multiple input inverting summing circuits to have greater

bandwidth, and low-power differential line drivers to meet the

demanding requirements of DSL.

DESCRIPTION

The OPA2683 provides a new level of performance for dual, very

low-power, wideband, current-feedback amplifiers. This CFB_PLUS

amplifier is among the first to use an internally closed-loop input

buffer stage that significantly enhances performance over earlier

low-power, current-feedback (CFB) amplifiers. This new archi-

tecture provides many of the advantages of a more ideal CFB

amplifier while retaining the benefits of very low-power operation.

The closed-loop input stage buffer gives a very low and linearized

impedance path at the inverting input to sense the feedback error

current. This improved inverting input impedance gives excep-

tional bandwidth retention to much higher gains and improved

harmonic distortion over earlier solutions limited by inverting input

linearity. Beyond simple high gain applications, the OPA2683

CFB_PLUSamplifier can allow the gain setting element to be set with

considerable freedom from amplifier bandwidth interaction. This

The output capability for the OPA2683 also sets a new mark in

performance for very low-power, current-feedback amplifiers. De-

livering a full ±4V_PPswing on ±5V supplies, the OPA2683 also has

the output current to support this swing into a 100Ω load. This

minimal output headroom requirement is complemented by a

similar 1.2V input stage headroom, giving exceptional capability for

single +5V operation.

The OPA2683’s low 1.9mA total supply current is precisely trimmed

at +25°C. This trim, along with low shift over temperature and supply

voltage, gives a very robust design over a wide range of operating

conditions. Further system power reduction is possible using

the shutdown feature of the MSOP-10 package.

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

6

V+

G = 10 G = 1

3

0

G = 2

+

V_O

–3

G = 50

Z_(S)I_ERR

V–

–6

G = 10

–9

I_ERR

G = 50

R_F

–12

–15

G = 100

R_G

R_F= 953Ω

–18

Low-Power

Amplifier

1

10

Frequency (Hz)

100

200

U.S. Patent No. 6,724,260

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Power Supply ............................................................................... ±6.5V_DC

Internal Power Dissipation...................................... See Thermal Analysis

Differential Input Voltage .................................................................. ±1.2V

Input Voltage Range............................................................................ ±V_S

Storage Temperature Range: ID, IDCN.........................–65°C to +125°C

Lead Temperature (soldering, 10s) .............................................. +300°C

Junction Temperature (T_J) ........................................................... +150°C

ESD Rating: Human Body Model (HBM) ........................................ 2000V

Charged Device Model (CDM) .................................. 1000V

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes

could cause the device not to meet its published specifications.

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

OPA2683 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

QUADS

FEATURES

OPA684

OPA691

OPA695

OPA2684

OPA2691

OPA2695

OPA3684

OPA3691

OPA3695

OPA4684 Low-Power CFB

—

High Slew Rate CFB

> 500MHz CFB

PACKAGE/ORDERING INFORMATION⁽¹⁾

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

OPA2683

SO-8

D

"

–40°C to +85°C

OPA2683

OPA2683ID

OPA2683IDR

Rails,100

"

B83

"

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 3000

Tape and Reel, 250

Tape and Reel, 2500

OPA2683

SOT23-8

DCN

–40°C to +85°C

OPA2683IDCNT

OPA2683IDCNR

OPA2683IDGST

OPA2683IDGSR

"

OPA2683

"

MSOP-10

DGS

"

–40°C to +85°C

BUI

"

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

PIN CONFIGURATION

Top View

SO-8

Top View

SOT23-8

Out A

–In A

+In A

–V_S

1

2

3

4

8

7

6

5

+V_S

Out A

–In A

+In A

–V_S

1

2

3

4

8

7

6

5

+V_S

Out B

–In B

+In B

Out B

–In B

+In B

Top View

MSOP-10

+In A

DIS A

–V_S

1

2

3

4

5

10 –In A

B83

9

8

7

6

Out A

+V_S

DIS B

+In B

Out B

–In B

Pin 1

OPA2683

SBOS244H

2

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= ±5V

Boldface limits are tested at +25°C.

R_F= 953Ω, R_L= 1kΩ, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted.

OPA2683ID, IDCN, IDGS

TYP

MIN/MAX OVER TEMPERATURE

0

°

C to

–40

°

C to

MIN/

TEST

MAX LEVEL⁽³⁾

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C⁽²⁾

+85°C⁽²⁾

UNITS

AC PERFORMANCE (see Figure 1)

Small-Signal Bandwidth (V_O= 0.5V_PP

)

G = +1, R_F= 953kΩ

G = +2, R_F= 953Ω

G = +5, R_F= 953Ω

G = +10, R_F= 953Ω

G = +20, R_F= 953Ω

200

150

121

94

72

37

1.8

63

540

400

4.6

7.8

MHz

dB

MHz

V/µs

ns

typ

min

typ

min

max

typ

min

typ

C

B

C

B

C

B

C

B

C

124

121

117

Bandwidth for 0.1dB Gain Flatness

Peaking at a Gain of +1

Large-Signal Bandwidth

Slew Rate

G = +2, V_O= 0.5V_PP, R_F= 953Ω

R_F= 953Ω, V_O= 0.5V_PP

G = +2, V_O= 4V_PP

G = –1, V_O= 4V Step (see Figure 2)

G = +2, V_O= 4V Step

G = +2, V_O= 0.5V Step

G = +2, V_O= 4V Step

G = +2, f = 5MHz, V_O= 2V_PP

R_L= 100Ω

15

6.5

14

7.7

14

8.0

450

345

450

338

430

336

Rise-and-Fall Time

ns

typ

Harmonic Distortion

2nd-Harmonic

–63

–71

–67

–77

4.4

–54

–55

–62

–67

5.0

–54

–55

–62

–66

5.5

–54

–55

–62

–66

5.8

dBc

max

typ

B

C

R

_L≥ 1kΩ

R_L= 100Ω

_L≥ 1kΩ

3rd-Harmonic

R

dBc

Input Voltage Noise

f > 1MHz

nV/√Hz

pA/√Hz

%

deg

dB

Noninverting Input Current Noise

Inverting Input Current Noise

Differential Gain

Differential Phase

Channel-to-Channel Isolation

5.1

5.8

11.9

6.4

12.3

6.7

12.4

11.6

0.13

0.06

70

G = +2, NTSC, V_O= 1.4V_P, R_L= 150Ω

f = 5MHz

typ

DC PERFORMANCE⁽⁴⁾

Open-Loop Transimpedance Gain (Z_OL

Input Offset Voltage

Average Offset Voltage Drift

Noninverting Input Bias Current

Average Noninverting Input Bias Current Drift

Inverting Input Bias Current

)

V_O= 0V, R_L= 1kΩ

700

±1.5

300

±3.5

270

±4.1

±12

±5.1

±15

±11

±20

250

±4.3

±12

±5.3

±15

kΩ

mV

µV/°C

µA

nA/°C

µA

nA°/C

min

max

A

B

A

B

A

B

V

_CM= 0V

V_CM= 0V

_CM= 0V

V_CM= 0V

_CM= 0V

V

±2.0

±3.0

±4.5

±10

V

±11.5

±20

Average Inverting Input Bias Current Drift

V_CM= 0V

INPUT

Common-Mode Input Range⁽⁵⁾(CMIR)

Common-Mode Rejection Ratio (CMRR)

Noninverting Input Impedance

Inverting Input Resistance (R_I)

±3.75

60

±3.65

53

±3.65

52

±3.60

52

V

dB

kΩ || pF

Ω

min

typ

A

C

V_CM= 0V

50

5.0

2

Open-Loop, DC

typ

OUTPUT

Voltage Output Swing

Current Output, Sourcing

Current Output, Sinking

Closed-Loop Output Impedance

1kΩ Load

V_O= 0

±4.1

150

–110

0.007

±4.0

120

–100

±4.0

115

–95

±3.9

110

–90

V

min

typ

A

C

mA

Ω

V

_O= 0

G = +2, f = 100kHz

DISABLE (Disabled LOW) (MSOP-10 Only)

Power-Down Supply Current (+V_S)

Disable Time

Enable Time

Off Isolation

Output Capacitance in Disable

Turn On Glitch

Turn Off Glitch

Enable Voltage

Disable Voltage

V_DIS= 0, Both Channel

V_IN= +1, See Figure 1

–200

60

40

–300

–340

–360

µA

ms

ns

dB

pF

mV

V

max

typ

min

max

A

C

A

V

_IN= +1, See Figure 1

G = +2, 5MHz

70

1.7

±70

±20

3.4

1.8

80

G = +2, R_L= 150Ω, V_IN= 0

3.5

1.7

120

3.6

1.6

130

3.7

1.5

135

V

µA

Control Pin Input Bias Current (DIS)

V_DIS= 0V, Each Channel

POWER SUPPLY

Specified Operating Voltage

Max Operating Voltage Range

Min Operating Voltage Range

Max Quiescent Current

Min Quiescent Current

Power-Supply Rejection Ratio (–PSRR)

±5

V

mA

dB

typ

max

typ

max

min

typ

C

A

C

A

±6

±2

1.88

62

V_S= ±5V, Both Channels

Input Referred

2.06

1.70

55

2.08

1.6

54

2.10

1.54

54

TEMPERATURE RANGE

Specification: D, DCN, DGS

Thermal Resistance, θ_JA

–40 to +85

°C

typ

C

Junction-to-Ambient

D

SO-8

125

150

140

°C/W

typ

C

DCN SOT23-8

DGS MSOP-10

NOTES: (1) Junction temperature = ambient for +25°C tested specifications.

(2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +2°C at high temperature limit for over-temperature tested

specifications.

(3) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterizationand simulation.

(C) Typical value only for information.

(4) Current is considered positive out-of-node. V_CMis the input common-mode voltage.

(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.

OPA2683

SBOS244H

3

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= +5V

Boldface limits are tested at +25°C.

R_F= 1.2kΩ, R_L= 1kΩ, and G = +2 (see Figure 3 for AC performance only), unless otherwise noted.

OPA2683ID, IDCN, IDGS

TYP

MIN/MAX OVER TEMPERATURE

0

°

C to

–40

°

C to

MIN/

TEST

MAX LEVEL⁽³⁾

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C⁽²⁾

+85°C⁽²⁾

UNITS

AC PERFORMANCE (see Figure 3)

Small-Signal Bandwidth (V_O= 0.2V_PP

)

G = +1, R_F= 1.2kΩ

G = +2, R_F= 1.2kΩ

G = +5, R_F= 1.2kΩ

145

119

95

87

60

14

1

70

MHz

dB

MHz

V/µs

ns

typ

min

typ

min

max

typ

min

typ

96

92

90

B

C

B

C

B

C

G = +10, R_F= 1.2kΩ

G = +20, R_F= 1.2kΩ

G = +2, V_O< 0.5V_PP, R_F= 1.2kΩ

R_F= 1.2kΩ, V_O< 0.5V_PP

G = +2, V_O= 2V_PP

G = +2, V_O= 2V Step

G = +2, V_O= 0.5V Step

G = +2, V_O= 2V Step

G = 2, f = 5MHz, V_O= 2V_PP

R_L= 100Ω to V_S/2

Bandwidth for 0.1dB Gain Flatness

Peaking at a Gain of +1

Large-Signal Bandwidth

Slew Rate

9

6

8

210

5.9

7.8

180

175

170

Rise-and-Fall Time

ns

typ

Harmonic Distortion

2nd-Harmonic

–60

–66

–59

–74

4.4

–54

–55

–58

–57

5.0

–53

–55

–58

–56

5.5

–53

–55

–58

–56

5.8

dBc

max

typ

B

C

R_L≥ 1kΩ to V_S/2

3rd-Harmonic

R

_L= 100Ω to V_S/2

R_L≥ 1kΩ to V_S/2

dBc

Input Voltage Noise

f > 1MHz

nV/√Hz

pA/√Hz

%

deg

dB

Noninverting Input Current Noise

Inverting Input Current Noise

Differential Gain

Differential Phase

Channel-to-Channel Crosstalk

5.1

5.8

11.9

6.4

12.3

6.7

12.4

11.6

0.24

0.19

70

G = +2, NTSC, V_O= 1.4V_P, R_L= 150Ω

f = 5MHz

typ

type

DC PERFORMANCE⁽⁴⁾

Open-Loop Transimpedance Gain (Z_OL

Input Offset Voltage

Average Offset Voltage Drift

Noninverting Input Bias Current

Average Noninverting Input Bias Current Drift

Inverting Input Bias Current

)

V_O= V_S/2, R_L= 1kΩ to V_S/2

700

±1.0

300

±3.0

270

±3.6

±12

±5.1

±12

±8.7

±15

250

±3.8

±12

±5.3

±12

±8.9

±15

kΩ

mV

µV/°C

µA

nA/°C

µA

nA°/C

min

max

A

B

A

B

A

B

V

_CM= V_S/2

±2

±3

±4.5

±8

V_CM= V_S/2

V

_CM= V_S/2

Average Inverting Input Bias Current Drift

INPUT

Least Positive Input Voltage⁽⁵⁾

Most Positive Input Voltage⁽⁵⁾

Common-Mode Rejection Ratio (CMRR)

Noninverting Input Impedance

Inverting Input Resistance (R_I)

1.1

3.9

56

50

5.6

1.25

3.75

51

1.29

3.73

50

1.34

3.67

50

V

dB

kΩ || pF

Ω

max

min

typ

A

C

V

_CM= V_S/2

2

Open-Loop, DC

typ

OUTPUT

Most Positive Output Voltage

Least Positive Output Voltage

Current Output, Sourcing

Current Output, Sinking

Closed-Loop Output Impedance

R

_L= 1kΩ to V_S/2

4.2

0.8

80

–70

0.009

4.1

0.9

65

4.1

0.9

63

4.0

1.0

58

V

mA

Ω

min

max

min

typ

A

C

R_L= 1kΩ to V_S/2

V

_O= V_S/2

–52

–50

–45

G = +2, f = 100kHz

DISABLE (Disabled LOW) (MSOP-10 Only)

Power-Down Supply Current (+V_S)

Off Isolation

Output Capacitance in Disable

Turn On Glitch

Turn Off Glitch

Enable Voltage

Disable Voltage

Control Pin Input Bias Current (DIS)

V_DIS= 0, Both Channels

G = +2, 5MHz

–200

70

µA

dB

pF

mV

V

typ

min

max

C

A

1.7

±70

±20

3.4

1.8

80

G = +2, R_L= 150Ω, V_IN= V_S/2

3.5

1.7

120

3.6

1.6

130

3.7

1.5

135

V

µA

V_DIS= 0V, Each Channel

POWER SUPPLY

Specified Single-Supply Operating Voltage

Max Single-Supply Operating Voltage

Min Single-Supply Operating Voltage

Max Quiescent Current

Min Quiescent Current

Power-Supply Rejection Ratio (+PSRR)

+5

V

mA

dB

typ

max

typ

max

min

typ

C

A

C

A

C

+12

+4

1.58

65

V_S= +5V, Both Channels

1.76

1.36

1.76

1.32

1.76

1.28

V

_S= +5V, Both Channels

Input Referred

TEMPERATURE RANGE

Specification: D, DCN, DGS

Thermal Resistance, θ_JA

–40 to +85

°C

typ

C

Junction-to-Ambient

D

SO-8

125

150

140

°C/W

typ

C

DCN SOT23-8

DGS MSOP-10

NOTES: (1) Junction temperature = ambient for +25°C tested specifications.

(2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +2°C at high temperature limit for over-temperature tested

specifications.

(3) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.

(C) Typical value only for information.

(4) Current is considered positive out-of-node. V_CMis the input common-mode voltage.

(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.

OPA2683

SBOS244H

4

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V

T_A= +25°C, G = +2, R_F= 953Ω, and R_L= 1kΩ, unless otherwise noted.

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

6

3

6

3

G = 10

V_O= 0.5V_PP

R_F= 953Ω

G = 1

G = 2

G = –1

G = –2

0

–3

G = 50

G = 10

–6

–9

G = –10

G = 50

G = –5

–12

–15

–18

–12

–15

–18

G = 100

G = –20

See Figure 1

See Figure 2

1

10

Frequency (MHz)

100

200

1

10

100

200

Frequency (MHz)

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

9

6

3

0

R_F= 953Ω

G = –2

R_F= 953Ω

G = +2

1V_PP

0.5V_PP

–3

–6

–9

–12

2V_PP

3

1V_PP

5V_PP

0

2V_PP

5V_PP

See Figure 1

See Figure 2

–3

1

10

100

200

1

10

100

200

Frequency (MHz)

NONINVERTING PULSE RESPONSE

G = +2

INVERTING PULSE RESPONSE

G = –1

0.8

0.6

3.2

0.8

0.6

3.2

2.4

0.4

1.6

0.4

1.6

Large-Signal Right Scale

Small-Signal Left Scale

0.2

0.8

0.2

0.8

0

Small-Signal Left Scale

Large-Signal Right Scale

–0.2

–0.4

–0.6

–0.8

–1.6

–2.4

–3.2

–0.2

–0.4

–0.6

–0.8

–1.6

–2.4

–3.2

See Figure 1

See Figure 2

Time (10ns/div)

OPA2683

SBOS244H

5

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, R_F= 953Ω, and R_L= 1kΩ, unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

V_O= 2V_PP

HARMONIC DISTORTION vs FREQUENCY

V_O= 2V_PP

–50

–55

–60

–65

–70

–75

–80

–85

–90

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

f = 5MHz

G = +2

R_L= 1kΩ

2nd-Harmonic

3rd-Harmonic

See Figure 1

100

3rd-Harmonic

See Figure 1

0.1

1

10

20

6.0

20

1k

Frequency (MHz)

Load Resistance (Ω)

HARMONIC DISTORTION vs OUTPUT VOLTAGE

f = 5MHz

5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE

–50

–60

–70

–80

–90

–50

–55

–60

–65

–70

–75

–80

–85

V_O= 2V_PP

R_L= 1kΩ

2nd-Harmonic

3rd-Harmonic

See Figure 1

3rd-Harmonic

See Figure 1

0.1

1

5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Output Voltage (V_PP

)

Supply Voltage (±V)

HARMONIC DISTORTION vs NONINVERTING GAIN

_O= 2V_PP

HARMONIC DISTORTION vs INVERTING GAIN

–50

–60

–70

–80

–90

–50

–55

–60

–65

–70

–75

–80

–85

–90

V

V_O= 2V_PP

R_L= 1kΩ

2nd-Harmonic

3rd-Harmonic

See Figure 1

See Figure 2

1

10

20

1

10

Gain (V/V)

Gain |(–V/V)|

OPA2683

SBOS244H

6

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TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, R_F= 953Ω, and R_L= 1kΩ, unless otherwise noted.

2-TONE, 3RD-ORDER

INTERMODULATION DISTORTION

INPUT VOLTAGE AND CURRENT NOISE DENSITY

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

100

10

1

f_O= 20MHz

+5V

Inverting Current Noise

11.6pA/√Hz

P_I

f

_O= 10MHz

f_O= 5MHz

P_O

OPA2683

50Ω

Noninverting Current Noise

5.2pA/√Hz

1kΩ

–5V

953Ω

Voltage Noise

4.4nV/√Hz

f

_O= 1MHz

100

1k

10k

100k

1M

10M

0.1

1

2

Frequency (Hz)

V_PPat 1kΩ Load (Each tone)

R_Svs C_LOAD

SMALL-SIGNAL BANDWIDTH vs C_LOAD

50

45

40

35

30

25

20

15

10

5

9

6

10pF

0.5dB Peaking

22pF

R_SAdjusted to C_LOAD

+5V

100pF

3

R_S

V_I

V_O

OPA2683

47pF

50Ω

C_L

1kΩ

0

–5V

953Ω

–3

–6

953Ω

0

100k

1M

10M

Frequency (Hz)

100M 1G

1

10

100

C_LOAD(pF)

OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE

20log (Z_OL

CMRR AND PSRR vs FREQUENCY

CMRR

120

0

70

60

50

40

30

20

10

0

)

100

80

60

40

20

0

–30

–60

–90

–120

–150

–180

+PSRR

–PSRR

Z_OL

10k

100k

1M

10M

100M

1G

100

1k

10k

100k

1M

10M

100M

Frequency (Hz)

OPA2683

SBOS244H

7

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TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, R_F= 953Ω, and R_L= 1kΩ, unless otherwise noted.

OUTPUT CURRENT AND VOLTAGE LIMITATIONS

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

5

4

0.20

0.15

0.10

0.05

0

1W Power

Limit

Gain = +2

NTSC, Positive Video

3

2

1

0

dG

–1

–2

–3

–4

–5

dP

1W Power

Limit

Each Channel

1

–50

0

2

3

4

–150

–100

–50

0

50

100

150

I

_O(mA)

Number of 150Ω Video Loads

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

TYPICAL DC DRIFT OVER TEMPERATURE

200

175

150

125

100

2.0

1.9

1.8

1.7

1.6

4

3

Sourcing Output Current

2

Supply Current

Right Scale

1

Noninverting Input Bias Current

0

Input Offset Voltage

Sinking Output Current

–1

–2

–3

–4

Inverting Input Bias Current

25 50 75

–25

0

25

50

75

100

125

–25

0

100

125

Ambient Temperature (°C)

CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

SETTLING TIME

0.05

0.04

0.03

0.02

0.01

0

100

10

2V Step

See Figure 1

1/2

OPA2683

Z_O

953Ω

1

–0.01

–0.02

–0.03

–0.04

–0.05

0.01

0.001

100

1k

10k

100k

1M

10M

100M

10

20

30

40

50

60

Time (ns)

Frequency (Hz)

OPA2683

SBOS244H

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TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, R_F= 953Ω, and R_L= 1kΩ, unless otherwise noted.

NONINVERTING OVERDRIVE RECOVERY

INVERTING OVERDRIVE RECOVERY

4.0

3.2

8.0

6.4

8.0

6.4

2.4

4.8

1.6

3.2

Output Voltage

Right Scale

0.8

1.6

0

Output Voltage

–0.8

–1.6

–2.4

–3.2

–4.0

–1.6

–3.2

–4.8

–6.4

–8.0

–1.6

–3.2

–4.8

–6.4

–8.0

–1.6

–3.2

–4.8

–6.4

–8.0

Right Scale

See Figure 1

Input Voltage

Left Scale

Input Voltage

Left Scale

See Figure 2

Time (100ns/div)

INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE

CHANNEL-TO-CHANNEL CROSSTALK

6

5

0

Input Referred

–10

–20

–30

–40

–50

–60

–70

–80

–90

4

3

2

1

Input

Voltage

Range

Output

Voltage

Range

0

–1

–2

–3

–4

–5

–6

± 2

± 3

± 4

± Supply Voltage

± 5

± 6

1M

10M

100M

Frequency (Hz)

DISABLE SUPPLY CURRENT vs TEMPERATURE

Both Channels

DISABLE TIME

290

270

250

230

210

190

170

150

6

5

4

3

2

1

0

V_DIS

V_IN= 1V_DC

See Figure 1

V_OUT

0

10

20

30

40

50 60

70

80

90 100

50

25

0

25

50

75

100

125

Time (ms)

Ambient Temperature (°C)

OPA2683

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TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, R_F= 953Ω, and R_L= 1kΩ, unless otherwise noted.

DISABLED FEEDTHRU

–40

G = +2

Each Channel

V

_DIS= 0V

–50

–60

–70

–80

–90

See Figure 1

–100

0.1

1

10

100

Frequency (MHz)

OPA2683

SBOS244H

10

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TYPICAL CHARACTERISTICS: V_S= +5V

T_A= +25°C, V_S= 5V, G = +2, R_F= 1.2kΩ, and R_L= 1kΩ, unless otherwise noted.

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

6

3

6

3

G = 2

G = 1

0

G = –1

G = 5

G = 10

G = 20

–3

–6

G = –5

–9

G = 50

G = –10

G = –20

–12

–15

–18

–12

–15

–18

G = –2

See Figure 4

G = 100

See Figure 3

1

10

100

200

1

10

Frequency (MHz)

100

200

Frequency (MHz)

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

9

6

3

0

0.2V_PP

0.5V_PP

1V_PP

–3

–6

–9

–12

1V_PP

2V_PP

0.5V_PP

2V_PP

3

0

See Figure 4

See Figure 3

–3

1

10

Frequency (MHz)

100

200

1

10

100

200

Frequency (MHz)

INVERTING PULSE RESPONSE

NONINVERTING PULSE RESPONSE

Large-Signal Right Scale

0.4

0.3

1.6

0.4

0.3

1.6

1.2

0.2

0.8

0.2

0.8

0.1

0.4

0.1

0.4

Small-Signal Left Scale

0

Small-Signal Left Scale

Large-Signal Right Scale

–0.1

–0.2

–0.3

–0.4

–0.8

–1.2

–1.6

–0.1

–0.2

–0.3

–0.4

–0.8

–1.2

–1.6

See Figure 3

See Figure 4

Time (10ns/div)

OPA2683

SBOS244H

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TYPICAL CHARACTERISTICS: V_S= +5V (Cont.)

T_A= +25°C, V_S= 5V, G = +2, R_F= 1.2kΩ, and R_L= 1kΩ, unless otherwise noted.

HARMONIC DISTORTION vs FREQUENCY

HARMONIC DISTORTION vs LOAD RESISTANCE

–50

–60

–70

–80

–90

–50

–55

–60

–65

–70

–75

–80

–85

–90

f = 5MHz

_O= 2V_PP

V_O= 2V_PP

R_L= 1kΩ

V

2nd-Harmonic

3rd-Harmonic

2nd-Harmonic

3rd-Harmonic

See Figure 3

100

See Figure 3

0.1

1

10

20

1k

Frequency (MHz)

Load Resistance (Ω)

2-TONE, 3RD-ORDER

HARMONIC DISTORTION vs OUTPUT VOLTAGE

INTERMODULATION DISTORTION

–40

–50

–60

–70

–80

–90

–50

–55

–60

–65

–70

–75

–80

–85

–90

20MHz

10MHz

3rd-Harmonic

2nd-Harmonic

5MHz

See Figure 3

0.1

1

3

1

Output Voltage (V_PP

)

V_PPat 1kΩ Load (each tone)

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

100

90

80

70

60

50

1.9

1.8

1.7

1.6

1.5

1.4

0.30

0.25

0.20

0.15

0.10

0.05

0

G = +2

NTSC, Positive Video

Sourcing Output Current

Left Scale

dG

Supply Current

Right Scale

Left Scale

Sinking Output Current

dP

1

2

3

4

–50

–25

0

25

50

75

100

125

Number of 150Ω Video Loads

Ambient Temperature (°C)

OPA2683

SBOS244H

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Figure 2 shows the DC-coupled, gain of –1V/V, dual power-

supply circuit used as the basis of the inverting Typical

Characteristics for each channel. Inverting operation offers

several performance benefits. Since there is no common-

mode signal across the input stage, the slew rate for inverting

operation is typically higher and the distortion performance is

slightly improved. An additional input resistor, R_M, is included

in Figure 2 to set the input impedance equal to 50Ω. The

parallel combination of R_Mand R_Gset the input impedance.

As the desired gain increases for the inverting configuration,

R_Gis adjusted to achieve the desired gain, while R_Mis also

adjusted to hold a 50Ω input match. A point will be reached

where R_Gwill equal 50Ω, R_Mis removed, and the input match

is set by R_Gonly. With R_Gfixed to achieve an input match to

50Ω, increasing R_Fwill increase the gain. However, this will

reduce the achievable bandwidth as the feedback resistor

increases from its recommended value of 953Ω. If the source

does not require an input match to 50Ω, either adjust R_Mto

get the desired load, or remove it and let the R_Gresistor

alone provide the input load.

APPLICATIONS INFORMATION

LOW-POWER, CURRENT-FEEDBACK OPERATION

The dual channel OPA2683 gives a new level of perfor-

mance in low-power, current-feedback op amps. Using a

new input stage buffer architecture, the OPA2683 CFB_PLUS

amplifier holds nearly constant AC performance over a wide

gain range. This closed-loop internal buffer gives a very low

and linearized impedance at the inverting node, isolating the

amplifier’s AC performance from gain element variations.

This low impedance allows both the bandwidth and distortion

to remain nearly constant over gain, moving closer to the

ideal current- feedback performance of gain bandwidth inde-

pendence. This low-power amplifier also delivers exceptional

output power—its ±4V swing on ±5V supplies with > 100mA

output drive gives excellent performance into standard video

loads or doubly-terminated 50Ω cables. This dual-channel

device can provide adequate drive for several emerging

differential driver applications with exceptional power effi-

ciency. Single +5V supply operation is also supported with

similar bandwidths but reduced output power capability. For

higher output power in a dual current-feedback op amp,

consider the OPA2684, OPA2691, or OPA2677.

+5V

Figure 1 shows the DC-coupled, gain of +2, dual power-

supply circuit used as the basis of the ±5V Electrical and

Typical Characteristics for each channel. For test purposes,

the input impedance is set to 50Ω with a resistor to ground,

and the output impedance is set to a 1kΩ load. Voltage

swings reported in the characteristics are taken directly at the

input and output pins. For the circuit of Figure 1, the total

effective load will be 1kΩ || 1.9kΩ = 656Ω. Gain changes are

most easily accomplished by simply resetting the R_Gvalue,

holding R_Fconstant at its recommended value of 953Ω.

+

0.1µF

6.8µF

1/2

OPA2683

V_O

1kΩ

R_G

953Ω

R_F

953Ω

50Ω Source

V_I

R_M

52.3Ω

0.1µF

6.8µF

+

–5V

+5V

FIGURE 2. DC-Coupled, G = –1V/V, Bipolar Supply Specifi-

+

cations and Test Circuit.

0.1µF

6.8µF

V_I

These circuits show ±5V operation. The same circuit can be

applied with bipolar supplies from ±2.5V to ±6V. Internal

supply independent biasing gives nearly the same perfor-

mance for the OPA2683 over this wide range of supplies.

Generally, the optimum feedback resistor value (for nomi-

nally flat frequency response at G = +2) will increase in value

as the total supply voltage across the OPA2683 is reduced

from ±5V.

50Ω Source

R_M

50Ω

1/2

OPA2683

V_O

1kΩ

R_F

953Ω

R_G

953Ω

0.1µF

6.8µF

See Figure 3 for the AC-coupled, single +5V supply, gain of

+2V/V circuit configuration used as a basis only for the +5V

Electrical and Typical Characteristics for each channel. The

key requirement of broadband single-supply operation is to

maintain input and output signal swings within the usable

voltage ranges at both the input and the output. The circuit

of Figure 3 establishes an input midpoint bias using a simple

resistive divider from the +5V supply (two 10kΩ resistors) to

the noninverting input. The input signal is then AC-coupled

+

–5V

FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply Speci-

fications and Test Circuit.

OPA2683

SBOS244H

13

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into this midpoint voltage bias. The input voltage can swing

to within 1.25V of either supply pin, giving a 2.5V_PPinput

signal range centered between the supply pins. The input

impedance of Figure 3 is set to give a 50Ω input match. If the

source does not require a 50Ω match, remove this and drive

directly into the blocking capacitor. The source will then see

the 5kΩ load of the biasing network. The gain resistor (R_G)

is AC-coupled, giving the circuit a DC gain of +1, which puts

the noninverting input DC bias voltage (2.5V) on the output

as well. The feedback resistor value has been adjusted from

the bipolar ±5V supply condition to re-optimize for a flat

frequency response in +5V only, gain of +2, operation. On a

single +5V supply, the output voltage can swing to within

0.9V of either supply pin while delivering more than 70mA

output current, giving 3.2V output swing into 100Ω (8dBm

maximum at a matched 50Ω load). The circuit of Figure 3

shows a blocking capacitor driving into a 1kΩ load. Alterna-

tively, the blocking capacitor could be removed if the load is

tied to a supply midpoint or to ground if the DC current

required by the load is acceptable.

a current-feedback amplifier, wideband operation is retained

even under this condition.

The circuits of Figure 3 and 4 show single-supply operation

at +5V. These same circuits may be used up to single

supplies of +12V with minimal change in the performance of

the OPA2683.

+5V

+

0.1µF

6.8µF

10kΩ

0.1µF

1/2

OPA2683

V_O

0.1µF

1kΩ

R_G

1.2kΩ

R_F

1.2kΩ

50Ω Source

V_I

R_M

52.3Ω

+5V

FIGURE 4. AC-Coupled, G = –1V/V, Single-Supply Specifi-

cations and Test Circuit.

+

0.1µF

6.8µF

10kΩ

50Ω Source

0.1µF

DIFFERENTIAL INTERFACE APPLICATIONS

V_I

0.1µF

Dual op amps are particularly suitable to differential input to

differential output applications. Typically, these fall into either

Analog-to-Digital Converter (ADC) input interfaces or line

driver applications. Two basic approaches to differential I/O

are noninverting or inverting configurations. Since the output

is differential, the signal polarity is somewhat meaningless—

the noninverting and inverting terminology applies here to

where the input is brought into the OPA2683. Each has its

advantages and disadvantages. Figure 5 shows a basic

starting point for noninverting differential I/O applications.

1/2

OPA2683

R_M

50Ω

V_O

1kΩ

R_F

1.2kΩ

R_G

1.2kΩ

0.1µF

FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply Specifi-

cations and Test Circuit.

+V_CC

Figure 4 shows the AC-coupled, single +5V supply, gain of

–1V/V circuit configuration used as a basis for the +5V

Typical Characteristics for each channel. In this case, the

midpoint DC bias on the noninverting input is also decoupled

with an additional 0.1µF decoupling capacitor. This reduces

the source impedance at higher frequencies for the

noninverting input bias current noise. This 2.5V bias on the

noninverting input pin appears on the inverting input pin and,

since R_Gis DC blocked by the input capacitor, will also

appear at the output pin. One advantage to inverting opera-

tion is that since there is no signal swing across the input

stage, higher slew rates and operation to even lower supply

voltages is possible. To retain a 1V_PPoutput capability,

operation down to 3V supply is allowed. At +3V supply, the

input stage is saturated, but for the inverting configuration of

1/2

OPA2683

R_F

953Ω

R_F

953Ω

V_I

V_O

R_G

1/2

OPA2683

–V_CC

FIGURE 5. Noninverting Differential I/O Amplifier.

OPA2683

SBOS244H

14

www.ti.com

This approach provides for a source termination impedance

that is independent of the signal gain. For instance, simple

differential filters may be included in the signal path right up

to the noninverting inputs without interacting with the gain

setting. The differential signal gain for the circuit of Figure 5 is:

The two noninverting inputs provide an easy common-mode

control input. This is particularly simple if the source is

AC-coupled through either blocking caps or a transformer.

In either case, the common-mode input voltages on the two

noninverting inputs again have a gain of 1 to the output pins,

giving particularly easy common-mode control for single-

supply operation. The OPA2683 used in this configuration

does constrain the feedback to the 953Ω region for best

frequency response. With R_Ffixed, the input resistors may be

adjusted to the desired gain but will also be changing the

input impedance as well. The high-frequency common-mode

gain for this circuit from input to output will be the same as

for the signal gain. Again, if the source might include an

undesired common-mode signal, that signal could be re-

jected at the input using blocking caps (for low frequency and

DC common-mode) or a transformer coupling.

(1)

A_D= 1 + 2 • R_F/R_G

Since the OPA2683 is a CFB_PLUSamplifier, its bandwidth is

principally controlled with the feedback resistor value; see

Figure 5 for the recommended value of 953Ω. The differential

gain, however, may be adjusted with considerable freedom

using just the R_Gresistor. In fact, R_Gmay be a reactive

network providing a very isolated shaping to the differential

frequency response. Since the inverting inputs of the OPA2683

are very low impedance closed-loop buffer outputs, the R_G

element does not interact with the amplifier’s bandwidth;

wide ranges of resistor values and/or filter elements may be

inserted here with minimal amplifier bandwidth interaction.

DC-COUPLED SINGLE TO DIFFERENTIAL CONVERSION

Various combinations of single-supply or AC-coupled gain

can also be delivered using the basic circuit of Figure 5.

Common-mode bias voltages on the two noninverting inputs

pass on to the output with a gain of 1 since an equal DC

voltage at each inverting node creates no current through

R_G. This circuit does show a common-mode gain of 1 from

input to output. The source connection should either remove

this common-mode signal if undesired (using an input trans-

former can provide this function), or the common-mode

voltage at the inputs can be used to set the output common-

mode bias. If the low common-mode rejection of this circuit

is a concern, the output interface may also be used to reject

that common-mode. For instance, most modern differential

input ADCs reject common-mode signals very well, while a

line driver application through a transformer will also attenu-

ate the common-mode signal through to the line.

The previous differential output circuits were also set up to

receive a differential input. A simple way to provide a DC-

coupled single to differential conversion using a dual op amp

is shown in Figure 7. Here, the output of the first stage is

simply inverted by the second to provide an inverting version

of a single amplifier design. This approach works well for

lower frequencies but will start to depart from ideal differential

outputs as the propagation delay and distortion of the invert-

ing stage adds significantly to that present at the noninverting

output pin.

+5V

1V_PP

1/2

50Ω

OPA2683

Figure 6 shows a differential I/O stage configured as an

inverting amplifier. In this case, the gain resistors (R_G)

become part of the input resistance for the source. This

provides a better noise performance than the noninverting

configuration but does limit the flexibility in setting the input

impedance separately from the gain.

953Ω

191Ω

12V_PPDifferential

953Ω

+V_CC

V_CM

1/2

OPA2683

1/2

OPA2683

R_F

R_G

953Ω

–5V

R_F

953Ω

FIGURE 7. Single to Differential Conversion.

V_I

V_O

The circuit of Figure 7 is set up for a single-ended gain of 6

to the output of the first amplifier, then an inverting gain of

–1 through the second stage to provide a total differential

gain of 12. See Figure 8 for the 75MHz small-signal band-

width delivered by the circuit of Figure 7. Large-signal distor-

tion at 12V_PPoutput at 1MHz into the 1kΩ differential load is

≤ –76dBc.

1/2

OPA2683

V_CM

–V_CC

FIGURE 6. Inverting Differential I/O Amplifier.

OPA2683

SBOS244H

15

www.ti.com

of Figure 9 designs the filter for a differential gain of 5 using

the OPA2683. The resistor values have been adjusted slightly

to account for the amplifier bandwidth effects.

SINGLE TO DIFFERENTIAL CONVERSION

24

21

18

15

12

9

While this circuit is bipolar, using ±5V supplies, it can easily

be adapted to single-supply operation. This is typically done

by providing a supply midpoint reference at the noninverting

inputs, then adding DC blocking caps at each input and in

series with the amplifier gain resistor, R_G. This will add two

real zeroes in the response, transforming the circuit into a

bandpass. Figure 10 shows the frequency response for the

filter of Figure 9.

6

3

1

10

100

200

10MHz, 3RD-ORDER BUTTERWORTH LOW PASS

Frequency (MHz)

FREQUENCY RESPONSE

14

FIGURE 8. Small-Signal Bandwidth for Figure 7.

11

8

DIFFERENTIAL ACTIVE FILTER

The OPA2683 can provide a very capable gain block for low-

power active filters. The dual design lends itself very well to

differential active filters. Where the filter topology is looking

for a simple gain function to implement the filter, the

noninverting configuration is preferred to isolate the filter

elements from the gain elements in the design. Figure 9

shows an example of a very low-power, 10MHz, 3rd-order

Butterworth low-pass Sallen-Key filter. Often, these filters are

designed at an amplifier gain of 1 to minimize amplifier

bandwidth interaction with the desired filter shape. Since the

OPA2683 shows minimal bandwidth change with gain, this

feature would not be a constraint in this design. The example

5

2

–1

–4

1

10

20

Frequency (MHz)

FIGURE 10. Frequency Response for 10MHz, 3rd-Order

Butterworth Low-Pass Filter.

100pF

+5V

20Ω

47Ω

183Ω

1/2

OPA2683

953Ω

357Ω

75pF

R_G

475Ω

V_I

V_O

22pF

953Ω

1/2

OPA2683

20Ω

47Ω

183Ω

–5V

100pF

FIGURE 9. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter.

OPA2683

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SINGLE-SUPPLY, HIGH GAIN DIFFERENTIAL

ADC DRIVER

+5V

V_DIS

Where a very low-power differential I/O interface to a moder-

ate performance ADC is required, the circuit of Figure 11 may

be considered. The circuit builds on the inverting differential

I/O configuration of Figure 6 by adding the input transformer

and the output low-pass filter. The input transformer provides

a single-to-differential conversion where the input signal is

still very low power—it also provides a gain of 2 and removes

any common-mode signal from the inputs. This single +5V

design sets a midpoint bias from the supply at each of the

noninverting inputs.

Power-Supply

Decoupling

Not Shown

+5V

U1

CH0

78.7Ω

1/2

OPA2683

75Ω

V_OUT

75Ω Line

681Ω

953Ω

CH1

+5V

78.7Ω

1/2

OPA2683

75Ω

V_OUT

10kΩ

75Ω Line

V_CM

681Ω

953Ω

1/2

OPA2683

0.1µF

10kΩ

ADC

500Ω (Optional)

+5V

200Ω

800Ω

R_S

1:2

50Ω

Source

U2

C_L

800Ω

R_S

CH0

78.7Ω

1/2

OPA2683

75Ω

15.3dB

Noise Figure

1/2

OPA2683

Gain = 8V/V

18.1dB

681Ω

953Ω

V_CM

500Ω (Optional)

CH1

FIGURE 11. Single-Supply Differential ADC Driver.

78.7Ω

1/2

OPA2683

75Ω

This circuit also includes optional 500Ω pull-down resistors at

the output. With a 2.5V DC common-mode operating point

(set by V_CM), this will add 5mA to ground in the output stage.

This essentially powers up the NPN side of the output stage

significantly reducing distortion. It is important for good 2nd-

order distortion to connect the grounds of these two resistors

at the same point to minimize ground plane current for the

differential output signal.

681Ω

953Ω

FIGURE 12. Frequency Response for 10MHz, 3rd-Order

Butterworth Low-Pass Filter.

Since the OPA2683 does not disable quickly, this approach

is not suitable for pixel-by-pixel multiplexing—however, it

does provide an easy way to switch between two possible

RGB sources. The output swing provided by the active

channel will divide back through the inactive channel feed-

back to appear at the inverting input of the OFF channel. To

retain good pulse fidelity, or low distortion, this divided down

output signal at the inverting inputs of the OFF channels, plus

the OFF channel input signals, should not exceed 0.7V_PP. As

the signal across the buffers of the inactive channels ex-

ceeds 0.7V_PP, diodes across the inputs may begin to turn on

causing a nonlinear load to the active channel. This will

degrade signal linearity under those conditions.

LOW-POWER MUX/LINE DRIVER

Using the shutdown feature, two OPA2683s can provide an

easy low-power way to select one of two possible sources for

moderate-resolution monitors. Figure 12 shows a recom-

mended circuit where each of the outputs are combined in a

way that provides a net gain of 1 to the matched 75Ω load

with a 75Ω output impedance. This brings the two outputs for

each color together through a 78.7Ω resistor with a slightly

> 2 gain provided by the amplifiers. When one channel is

shutdown, the feedback network is still present, slightly

attenuating the signal and combining in parallel with the

78.7Ω to give a 75Ω source impedance.

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DESIGN-IN TOOLS

OPERATING SUGGESTIONS

DEMONSTRATION FIXTURES

SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH

Two printed circuit boards (PCBs) are available to assist in

the initial evaluation of circuit performance using the OPA2683

in its two package options. Both of these are offered free of

charge as unpopulated PCBs, delivered with a user’s guide.

The summary information for these fixtures is shown in

Table I.

Any current-feedback op amp like the OPA2683 can hold

high bandwidth over signal-gain settings with the proper

adjustment of the external resistor values. A low-power part

like the OPA2683 typically shows a larger change in band-

width due to the significant contribution of the inverting input

impedance to loop-gain changes as the signal gain is changed.

Figure 13 shows a simplified analysis circuit for any current-

feedback amplifier.

ORDERING

NUMBER

LITERATURE

NUMBER

PRODUCT

PACKAGE

OPA2683ID

OPA2683IDCN

OPA2683IDGS

SO-8

SOT23-8

MSOP-10

DEM-OPA-SO-2A

DEM-OPA-SOT-2A

DEM-OPA-MSOP-2B

SBOU003

SBOU001

SBOU040

V_I

TABLE I. Demonstration Fixtures by Package.

α

V_O

The demonstration fixtures can be requested at the Texas

Instruments web site (www.ti.com) through the OPA2683

product folder.

R_I

Z_(S)i_ERR

i_ERR

R_F

MACROMODELS

Computer simulation of circuit performance using SPICE is

often useful when analyzing the performance of analog

circuits and systems. This is particularly true for higher speed

designs where parasitic capacitance and inductance can

have a major effect on circuit performance. A SPICE model

for the OPA683 is available in the product folder on the TI

web site (www.ti.com). This is the single channel model for

the OPA2683—simply use two of these to implement an

OPA2683 simulation. These models do a good job of predict-

ing small-signal AC and transient performance under a wide

variety of operating conditions. However, they are less accu-

rate in predicting the harmonic distortion or dG/dP character-

istics. These models do not attempt to distinguish between

the package types in their small-signal AC performance.

R_G

FIGURE 13. Current-Feedback Transfer Function Analysis

Circuit.

The key elements of this current-feedback op amp model are:

α

Buffer gain from the noninverting input to the inverting input

Buffer output impedance

R_I

i_ERR

Feedback error current signal

Z(s)

Frequency dependent open-loop transimpedance

gain from i_ERRto V_O

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The buffer gain is typically very close to 1.00 and is normally

neglected from signal gain considerations. It will, however, set

the CMRR for a single op amp differential amplifier configura-

tion. For the buffer gain α < 1.0, the CMRR = –20 • log(1 – α).

The closed-loop input stage buffer used in the OPA2683 gives

a buffer gain more closely approaching 1.00 and this shows up

in a slightly higher CMRR than previous current-feedback op

amps.

frequency response given by Equation 2 will start to roll off,

and is exactly analogous to the frequency at which the noise

gain equals the open-loop voltage gain for a voltage-feed-

back op amp. The difference here is that the total impedance

in the denominator of Equation 3 may be controlled some-

what separately from the desired signal gain (or NG).

The OPA2683 is internally compensated to give a maximally

flat frequency response for R_F= 953Ω at NG = 2 on ±5V

supplies. That optimum value goes to 1.2kΩ on a single +5V

supply. Normally, with a current-feedback amplifier, it is

possible to adjust the feedback resistor to hold this band-

width up as the gain is increased. The CFB_PLUSarchitecture

has reduced the contribution of the inverting input impedance

to provide exceptional bandwidth to higher gains without

adjusting the feedback resistor value. The Typical Character-

istics show the small-signal bandwidth over gain with a fixed

feedback resistor.

R_I, the buffer output impedance, is a critical portion of the

bandwidth control equation. The OPA2683 reduces this

element to approximately 5.0Ω using the loop gain of the

closed-loop input buffer stage. This significant reduction in

output impedance, on very low power, contributes signifi-

cantly to extending the bandwidth at higher gains.

A current-feedback op amp senses an error current in the

inverting node (as opposed to a differential input error volt-

age for a voltage-feedback op amp) and passes this on to

the output through an internal frequency dependent

transimpedance gain. The Typical Characteristics show this

open-loop transimpedance response. This is analogous to

the open-loop voltage gain curve for a voltage-feedback op

amp. Developing the transfer function for the circuit of Figure

13 gives Equation 2:

Putting a closed-loop buffer between the noninverting and

inverting inputs does bring some added considerations. Since

the voltage at the inverting output node is now the output of

a locally closed-loop buffer, parasitic external capacitance on

this node can cause frequency response peaking for the

transfer function from the noninverting input voltage to the

inverting node voltage. While it is always important to keep

the inverting node capacitance low for any current-feedback

op amp, it is critically important for the OPA2683. External

layout capacitance in excess of 2pF will start to peak the

frequency response. This peaking can be easily reduced by

then increasing the feedback resistor value—but it is prefer-

able, from a noise and dynamic range standpoint, to keep

that capacitance low, allowing a close to nominal 953Ω

feedback resistor for flat frequency response. Very high

parasitic capacitance values on the inverting node (> 5pF)

can possibly cause input stage oscillation that cannot be

filtered by a feedback element adjustment.

R_F

α 1+

R_G

R_F+ R_I1+

Z_(S)

V_O

α NG

R_F+ R_ING

=

V

R_F

I

1+

Z_(S)

R_G

1+

R_F

(2)

NG = 1+

R_G

This is written in a loop-gain analysis format where the errors

arising from a non-infinite open-loop gain are shown in the

denominator. If Z_(S)were infinite over all frequencies, the

denominator of Equation 2 would reduce to 1 and the ideal

desired signal gain shown in the numerator would be achieved.

The fraction in the denominator of Equation 2 determines the

frequency response. Equation 3 shows this as the loop-gain

equation.

An added consideration is that at very high gains, 2nd-order

effects in the inverting output impedance cause the overall

response to peak up. If desired, it is possible to retain a flat

frequency response at higher gains by adjusting the feed-

back resistor to higher values as the gain is increased. Since

the exact value of feedback that will give a flat frequency

response at high gains depends strongly in inverting and

output node parasitic capacitance values, it is best to experi-

ment in the specific board with increasing values until the

desired flatness (or pulse response shape) is obtained. In

general, increasing R_F(and then adjusting R_Gto the desired

gain) will move towards flattening the response, while de-

creasing it will extend the bandwidth at the cost of some

peaking. The OPA683 data sheet gives an example of this

optimization of R_Fversus gain.

Z_(S)

= Loop Gain

(3)

R_F+ R_ING

If 20 • log(R_F+ NG • R_I) were drawn on top of the open-loop

transimpedance plot, the difference between the two would

be the loop gain at a given frequency. Eventually, Z_(S)rolls off

to equal the denominator of Equation 3, at which point the

loop gain has reduced to 1 (and the curves have intersected).

This point of equality is where the amplifier’s closed-loop

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OUTPUT CURRENT AND VOLTAGE

DRIVING CAPACITIVE LOADS

The OPA2683 provides output voltage and current capabili-

ties that can support the needs of driving doubly-terminated

50Ω lines. If the 1kΩ load of Figure 1 is changed to a 100Ω

load, the total load is the parallel combination of the 100Ω

load, and the 1.9kΩ total feedback network impedance. This

95Ω load will require no more than 42mA output current to

support the ±4.0V minimum output voltage swing specified

for 1kΩ loads. This is well below the specified minimum

+120/–90mA specifications over the full temperature range.

One of the most demanding and yet very common load

conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an ADC, including additional

external capacitance which may be recommended to im-

prove ADC linearity. A high-speed, high open-loop gain

amplifier like the OPA2683 can be very susceptible to de-

creased stability and closed-loop response peaking when a

capacitive load is placed directly on the output pin. When the

amplifier’s open-loop output resistance is considered, this

capacitive load introduces an additional pole in the signal

path that can decrease the phase margin. Several external

solutions to this problem have been suggested. When the

primary considerations are frequency response flatness, pulse

response fidelity, and/or distortion, the simplest and most

effective solution is to isolate the capacitive load from the

feedback loop by inserting a series isolation resistor between

the amplifier output and the capacitive load. This does not

eliminate the pole from the loop response, but rather shifts it

and adds a zero at a higher frequency. The additional zero

acts to cancel the phase lag from the capacitive load pole,

thus increasing the phase margin and improving stability.

The specifications described above, though familiar in the

industry, consider voltage and current limits separately. In

many applications, it is the voltage • current, or V-I product,

which is more relevant to circuit operation. Refer to the

Output Voltage and Current Limitations plot in the Typical

Characteristics. The X- and Y-axes of this graph show the

zero-voltage output current limit and the zero-current output

voltage limit, respectively. The four quadrants give a more

detailed view of the OPA2683’s output drive capabilities.

Superimposing resistor load lines onto the plot shows the

available output voltage and current for specific loads.

The minimum specified output voltage and current over

temperature are set by worst-case simulations at the cold

temperature extreme. Only at cold startup will the output

current and voltage decrease to the numbers shown in the

electrical characteristic tables. As the output transistors de-

liver power, their junction temperatures will increase, de-

creasing their V_BEs (increasing the available output voltage

swing) and increasing their current gains (increasing the

available output current). In steady-state operation, the avail-

able output voltage and current will always be greater than

that shown in the over-temperature specifications since the

output stage junction temperatures will be higher than the

minimum specified operating ambient.

The Typical Characteristics show the recommended R_Svs

C_LOADand the resulting frequency response at the load. The

1kΩ resistor shown in parallel with the load capacitor is a

measurement path and may be omitted. The required series

resistor value may be reduced by increasing the feedback

resistor value from its nominal recommended value. This will

increase the phase margin for the loop gain, allowing a lower

series resistor to be effective in reducing the peaking due to

capacitive load. SPICE simulation can be effectively used to

optimize this approach. Parasitic capacitive loads greater

than 5pF can begin to degrade the performance of the

OPA2683. Long PC board traces, unmatched cables, and

connections to multiple devices can easily cause this value

to be exceeded. Always consider this effect carefully, and

add the recommended series resistor as close as possible to

the OPA2683 output pin (see Board Layout Guidelines).

To maintain maximum output stage linearity, no output short-

circuit protection is provided. This will not normally be a

problem, since most applications include a series matching

resistor at the output that will limit the internal power dissipa-

tion if the output side of this resistor is shorted to ground.

However, shorting the output pin directly to the adjacent

positive power-supply pin can destroy the amplifier. If addi-

tional short-circuit protection is required, consider a small

series resistor in the power-supply leads. This resistor will,

under heavy output loads, reduce the available output volt-

age swing. A 5Ω series resistor in each power-supply lead

will limit the internal power dissipation to less than 1W for an

output short-circuit, while decreasing the available output

voltage swing only 0.25V for up to 50mA desired load

currents. Always place the 0.1µF power-supply decoupling

capacitors after these supply current limiting resistors directly

on the supply pins.

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DISTORTION PERFORMANCE

The OPA2683 has an extremely low 3rd-order harmonic

distortion, particularly for light loads and at lower frequen-

cies. This also gives low 2-tone, 3rd-order intermodulation

distortion as shown in the Typical Characteristics. Since the

OPA2683 includes internal power boost circuits to retain

good full-power performance at high frequencies and out-

puts, it does not show a classical 2-tone, 3rd-order inter-

modulation intercept characteristic. Instead, it holds relatively

low and constant 3rd-order intermodulation spurious levels

over power. The Typical Characteristics show this spurious

level as a dBc below the carrier at fixed center frequencies

swept over single-tone power at a matched 50Ω load. These

spurious levels drop significantly (> 12dB) for lighter loads

than the 100Ω used in that plot. Converter inputs, for in-

stance, will see ≤ 82dBc 3rd-order spurious to 10MHz for full-

scale inputs. For even lower 3rd-order intermodulation distor-

tion to much higher frequencies, consider the OPA2691.

The OPA2683 provides very low distortion in a low-power

part. The CFB_PLUSarchitecture also gives two significant

areas of distortion improvement. First, in operating regions

where the 2nd-harmonic distortion due to output stage

nonlinearities is very low (frequencies < 1MHz, low output

swings into light loads) the linearization at the inverting node

provided by the CFB_PLUSdesign gives 2nd-harmonic distor-

tions that extend into the –90dBc region. Previous current-

feedback amplifiers have been limited to approximately

–85dBc due to the nonlinearities at the inverting input. The

second area of distortion improvement comes in a distortion

performance that is largely gain independent. To the extent

that the distortion at a specific output power is output stage

dependent, 3rd-harmonics particularly, and to a lesser ex-

tend 2nd-harmonic distortion, remains constant as the gain

increases. This is due to the constant loop gain versus signal

gain provided by the CFB_PLUSdesign. As shown in the

Typical Characteristics, while the 3rd-harmonic is constant

with gain, the 2nd-harmonic degrades at higher gains. This

is largely due to board parasitic issues. Slightly imbalanced

load return currents will couple into the gain resistor to cause

a portion of the 2nd-harmonic distortion. At high gains, this

imbalance has more gain to the output giving increased

2nd-harmonic distortion.

NOISE PERFORMANCE

Wideband current-feedback op amps generally have a higher

output noise than comparable voltage-feedback op amps.

The OPA2683 offers an excellent balance between voltage

and current noise terms to achieve low output noise in a low-

power amplifier. The inverting current noise (11.6pA/√Hz) is

lower than most other current-feedback op amps while the

input voltage noise (4.4nV/√Hz) is lower than any unity-gain

stable, comparable slew rate, < 5mA/ch voltage-feedback op

amp. This low input voltage noise was achieved at the price

of higher noninverting input current noise (5.1pA/√Hz). As

long as the AC source impedance looking out of the

noninverting node is less than 200Ω, this current noise will

not contribute significantly to the total output noise. The op

amp input voltage noise and the two input current noise

terms combine to give low output noise under a wide variety

of operating conditions. Figure 14 shows the op amp noise

analysis model with all the noise terms included. In this

model, all noise terms are taken to be noise voltage or

Relative to alternative amplifiers with < 2mA supply current,

the OPA2683 holds much lower distortion at higher frequen-

cies (> 5MHz) and to higher gains. Generally, until the

fundamental signal reaches very high frequency or power

levels, the 2nd-harmonic will dominate the distortion with a

lower 3rd-harmonic component. Focusing then on the 2nd-

harmonic, increasing the load impedance improves distortion

directly. Remember that the total load includes the feedback

network—in the noninverting configuration (see Figure 1) this

is the sum of R_F+ R_G, while in the inverting configuration it

is just R_F. Also, providing an additional supply decoupling

capacitor (0.1µF) between the supply pins (for bipolar opera-

tion) improves the 2nd-order distortion slightly (3dB to 6dB).

current density terms in either nV/√Hz or pA/√Hz

.

In most op amps, increasing the output voltage swing in-

creases harmonic distortion directly. A low-power part like

the OPA2683 includes quiescent boost circuits to provide the

full-power bandwidth shown in the Typical Characteristics.

These act to increase the bias in a very linear fashion only

when high slew rate or output power are required. This also

acts to actually reduce the distortion slightly at higher output

power levels. The Typical Characteristics show the 2nd-

harmonic holding constant from 500mV_PPto 5V_PPoutputs

while the 3rd-harmonics actually decrease with increasing

output power.

E_NI

1/2

OPA2683

E_O

R_S

I_BN

E_RS

R_F

√4kTR_S

√4kTR_F

I_BI

R_G

4kT

R_G

4kT = 1.6E –20J

at 290°K

FIGURE 14. Op Amp Noise Analysis Model.

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The total output spot noise voltage can be computed as the

square root of the sum of all squared output noise voltage

contributors. Equation 4 shows the general form for the

output noise voltage using the terms presented in Figure 14.

While the last term, the inverting bias current error, is

dominant in this low-gain circuit, the input offset voltage will

become the dominant DC error term as the gain exceeds

5V/V. Where improved DC precision is required in a high-

speed amplifier, consider the OPA656 single and OPA2822

dual voltage-feedback amplifiers.

(4)

2

E_O

=

E_NI+ I_BNR_S+ 4kTR_SNG²+ I R

+ 4kTR_FNG

(

)

(

)

BI

F

DISABLE OPERATION

Dividing this expression by the noise gain (NG = (1 + R_F/R_G))

will give the equivalent input referred spot noise voltage at

the noninverting input, as shown in Equation 5.

The OPA2683 provides an optional disable feature that may

be used to reduce system power when channel operation is

not required. If the V_DIScontrol pin is left unconnected, the

OPA2683 will operate normally. To disable, the control pin

must be asserted LOW. Figure 14 shows a simplified internal

circuit for the disable control feature.

(5)

2

I_BIR_F

NG

4kTR_F

NG

2

E_N

=

E_NI+ I_BNR_S+ 4kTR_S

+

(

)

+V_S

Evaluating these two equations for the OPA2683 circuit and

component values (see Figure 1) will give a total output spot

noise voltage of 15.2nV/√Hz and a total equivalent input spot

noise voltage of 7.6nV/√Hz. This total input referred spot

noise voltage is higher than the 4.4nV/√Hz specification for

the op amp voltage noise alone. This reflects the noise

added to the output by the inverting current noise times the

feedback resistor. As the gain is increased, this fixed output

noise power term contributes less to the total output noise

and the total input referred voltage noise given by Equation 5

will approach just the 4.4nV/√Hz of the op amp itself. For

example, going to a gain of +20 in the circuit of Figure 1,

adjusting only the gain resistor to 50Ω, will give a total input

referred noise of 4.6nV/√Hz. A more complete description of

op amp noise analysis can be found in TI application note

AB-103, Noise Analysis for High-Speed Op Amps (SBOA066),

located at www.ti.com.

40kΩ

Q1

25kΩ

250kΩ

I_S

V_DIS

Control

–V_S

FIGURE 14. Simplified Disable Control Circuit.

In normal operation, base current to Q1 is provided through

the 250kΩ resistor while the emitter current through the 40kΩ

resistor sets up a voltage drop that is inadequate to turn on

the two diodes in Q1’s emitter. As V_DISis pulled LOW,

additional current is pulled through the 40kΩ resistor eventu-

ally turning on these two diodes (≈ 33µA). At this point, any

further current pulled out of V_DISgoes through those diodes

holding the emitter-base voltage of Q1 at approximately 0V.

This shuts off the collector current out of Q1, turning the

amplifier off. The supply current in the disable mode are only

those required to operate the circuit of Figure 14.

DC ACCURACY AND OFFSET CONTROL

A current-feedback op amp like the OPA2683 provides

exceptional bandwidth in high gains, giving fast pulse settling

but only moderate DC accuracy. The Electrical Characteris-

tics show an input offset voltage comparable to high slew

rate voltage-feedback amplifiers. The two input bias currents,

however, are somewhat higher and are unmatched. Whereas

bias current cancellation techniques are very effective with

most voltage-feedback op amps, they do not generally re-

duce the output DC offset for wideband current-feedback op

amps. Since the two input bias currents are unrelated in both

magnitude and polarity, matching the source impedance

looking out of each input to reduce their error contribution to

the output is ineffective. Evaluating the configuration of

Figure 1, using worst-case +25°C input offset voltage and the

two input bias currents, gives a worst-case output offset

range equal to:

When disabled, the output and input nodes go to a high

impedance state. If the OPA2683 is operating in a gain of +1

(with a 1.2kΩ feedback resistor still required for stability), this

will show a very high impedance (1.7pF || 1MΩ) at the output

and exceptional signal isolation. If operating at a gain greater

than +1, the total feedback network resistance (R_F+ R_G) will

appear as the impedance looking back into the output, but

the circuit will still show very high forward and reverse

isolation. If configured as an inverting amplifier, the input and

output will be connected through the feedback network

resistance (R_F+ R_G) giving relatively poor input to output

isolation.

±(NG • V_OS) + (I_BN• R_S/2 • NG) ± (I_BI• R_F)

where NG = noninverting signal gain

= ±(2 • 3.5mV) ± (4.5µA • 25Ω • 2) ± (953Ω • 10mA)

= ±7.0mV + 0.23mV ± 9.5mV

= ±16.73mV

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The OPA2683 provides very high power gain on low quies-

cent current levels. When disabled, internal high impedance

nodes discharge slowly which, with the exceptional power

gain provided, give a self powering characteristic that leads

to a slow turn off characteristic. Typical full turn off times to

rated 100µA disabled supply current are 60ms. Turn on times

are very fast—less than 40ns.

b) Minimize the distance (< 0.25") from the power-sup-

ply pins to high-frequency 0.1µF decoupling capaci-

tors. At the device pins, the ground and power-plane

layout should not be in close proximity to the signal I/O

pins. Avoid narrow power and ground traces to minimize

inductance between the pins and the decoupling capaci-

tors. The power-supply connections should always be

decoupled with these capacitors. An optional supply

decoupling capacitor (0.01µF) across the two power

supplies (for bipolar operation) will improve 2nd-har-

monic distortion performance. Larger (2.2µF to 6.8µF)

decoupling capacitors, effective at lower frequency,

should also be used on the main supply pins. These may

be placed somewhat farther from the device and may be

shared among several devices in the same area of the

PC board.

THERMAL ANALYSIS

The OPA2683 will not require external heatsinking for most

applications. Maximum desired junction temperature will set

the maximum allowed internal power dissipation as de-

scribed below. In no case should the maximum junction

temperature be allowed to exceed 150°C.

Operating junction temperature (T_J) is given by T_A+ P_D• θ_JA.

The total internal power dissipation (P_D) is the sum of

quiescent power (P_DQ) and additional power dissipated in the

output stage (P_DL) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total

supply voltage across the part. P_DLwill depend on the

required output signal and load but would, for a grounded

resistive load, be at a maximum when the output is fixed at

a voltage equal to 1/2 of either supply voltage (for equal

c) Careful selection and placement of external compo-

nents will preserve the high-frequency performance

of the OPA2683. Resistors should be a very low reac-

tance type. Surface-mount resistors work best and allow

a tighter overall layout. Metal film and carbon composi-

tion axially-leaded resistors can also provide good high-

frequency performance. Again, keep their leads and

PCB trace length as short as possible. Never use

wirewound type resistors in a high-frequency applica-

tion. Since the output pin and inverting input pin are the

most sensitive to parasitic capacitance, always position

the feedback and series output resistor, if any, as close

as possible to the output pin. Other network compo-

nents, such as noninverting input termination resistors,

should also be placed close to the package. The fre-

quency response is primarily determined by the feed-

back resistor value as described previously. Increasing

its value will reduce the peaking at higher gains, while

decreasing it will give a more peaked frequency re-

sponse at lower gains. The 800Ω feedback resistor used

in the Electrical Characteristics at a gain of +2 on ±5V

supplies is a good starting point for design. Note that a

953Ω feedback resistor, rather than a direct short, is

required for the unity-gain follower application. A cur-

rent-feedback op amp requires a feedback resistor even

in the unity-gain follower configuration to control stability.

2

bipolar supplies). Under this condition P_DL= V_S/(4 • R_L)

where R_Lincludes feedback network loading.

Note that it is the power in the output stage and not into the

load that determines internal power dissipation.

As an absolute worst-case example, compute the maximum

T_Jusing an OPA2683IDCN (SOT23-8 package) in the circuit

of Figure 1 operating at the maximum specified ambient

temperature of +85°C with both outputs driving a grounded

100Ω load to 2.5V_DC

.

P_D= 10V • 2.1mA + 2 • (5²/(4 • (100Ω || 1.9kΩ))) = 153mW

Maximum T_J= +85°C + (0.153W • 150°C/W) = 108°C

This maximum operating junction temperature is well below

most system level targets. Most applications will be lower

than this since an absolute worst-case output stage power in

both channels simultaneously was assumed in this calculation.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-

plifier like the OPA2683 requires careful attention to board

layout parasitics and external component types. Recommen-

dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for

all of the signal I/O pins. Parasitic capacitance on the

output and inverting input pins can cause instability; on

the noninverting input, it can react with the source

impedance to cause unintentional bandlimiting. To re-

duce unwanted capacitance, a window around the sig-

nal I/O pins should be opened in all of the ground and

power planes around those pins. Otherwise, ground and

power planes should be unbroken elsewhere on the

board.

OPA2683

SBOS244H

23

www.ti.com

d) Connections to other wideband devices on the board

may be made with short direct traces or through on-

board transmission lines. For short connections, con-

sider the trace and the input to the next device as a

lumped capacitive load. Relatively wide traces (50mils to

100mils) should be used, preferably with ground and

power planes opened up around them. Estimate the

total capacitive load and set R_Sfrom the plot of recom-

mended Rs vs C_LOAD. Low parasitic capacitive loads

(< 5pF) may not need an R_Ssince the OPA2683 is

nominally compensated to operate with a 2pF parasitic

load. If a long trace is required, and the 6dB signal loss

intrinsic to a doubly-terminated transmission line is ac-

ceptable, implement a matched impedance transmis-

sion line using microstrip or stripline techniques (consult

an ECL design handbook for microstrip and stripline

layout techniques). A 50Ω environment is normally not

necessary onboard, and in fact a higher impedance

environment will improve distortion, as shown in the

distortion versus load plots. With a characteristic board

trace impedance defined based on board material and

trace dimensions, a matching series resistor into the

trace from the output of the OPA2683 is used, as well as

a terminating shunt resistor at the input of the destina-

tion device. Remember also that the terminating imped-

ance will be the parallel combination of the shunt resistor

and the input impedance of the destination device; this

total effective impedance should be set to match the

trace impedance. The high output voltage and current

capability of the OPA2683 allows multiple destination

devices to be handled as separate transmission lines,

each with their own series and shunt terminations. If the

6dB attenuation of a doubly-terminated transmission line

is unacceptable, a long trace can be series-terminated

at the source end only. Treat the trace as a capacitive

load in this case and set the series resistor value as

shown in the plot of Rs vs C_LOAD. This will not preserve

signal integrity as well as a doubly-terminated line. If the

input impedance of the destination device is low, there

will be some signal attenuation due to the voltage divider

formed by the series output into the terminating imped-

ance.

e) Socketing a high-speed part like the OPA2683 is not

recommended. The additional lead length and pin-to-

pin capacitance introduced by the socket can create an

extremely troublesome parasitic network which can make

it almost impossible to achieve a smooth, stable fre-

quency response. Best results are obtained by soldering

the OPA2683 onto the board.

INPUT AND ESD PROTECTION

The OPA2683 is built using a very high-speed complemen-

tary bipolar process. The internal junction breakdown volt-

ages are relatively low for these very small geometry de-

vices. These breakdowns are reflected in the Absolute Maxi-

mum Ratings table where an absolute maximum 13V across

the supply pins is reported. All device pins have limited ESD

protection using internal diodes to the power supplies, as

shown in Figure 15.

These diodes provide moderate protection to input overdrive

voltages above the supplies as well. The protection diodes

can typically support 30mA continuous current. Where higher

currents are possible (for example, in systems with ±15V

supply parts driving into the OPA2683), current-limiting se-

ries resistors should be added into the two inputs. Keep

these resistor values as low as possible since high values

degrade both noise performance and frequency response.

+V_CC

External

Internal

Circuitry

–V_CC

FIGURE 15. Internal ESD Protection.

OPA2683

SBOS244H

24

www.ti.com

Revision History

DATE REVISION PAGE

SECTION

DESCRIPTION

7/09

7/08

H

G

2

Package/Ordering Information Changed package markings for D (SO-8) and DGS (MSOP-10) packages.

Absolute Maximum Ratings Changed minimum storage temperature from −40°C to −65°C.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

OPA2683

SBOS244H

25

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2009

PACKAGING INFORMATION

Orderable Device

OPA2683ID

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

OPA2683IDCNR

OPA2683IDCNRG4

OPA2683IDCNT

OPA2683IDG4

SOT-23

SOIC

DCN

D

8

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

8

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

8

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

OPA2683IDGSR

OPA2683IDGSRG4

OPA2683IDGST

OPA2683IDGSTG4

MSOP

DGS

10

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OPA2683IDCNR

OPA2683IDCNT

OPA2683IDGSR

OPA2683IDGST

SOT-23

MSOP

DCN

DGS

8

3000

250

180.0

330.0

180.0

8.4

3.2

5.3

3.1

3.4

1.39

1.4

4.0

8.0

Q3

Q1

10

2500

250

12.4

12.0

1.4

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

OPA2683IDCNR

OPA2683IDCNT

OPA2683IDGSR

OPA2683IDGST

SOT-23

MSOP

DCN

DGS

8

3000

250

190.5

346.0

190.5

212.7

346.0

212.7

31.8

29.0

31.8

10

2500

250

Pack Materials-Page 2

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	OPA2683ID
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOIC-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
Factory Lead Time：	1 week
风险等级：	1.65
Is Samacsys：	N
放大器类型：	OPERATIONAL AMPLIFIER
架构：	CURRENT-FEEDBACK
最大平均偏置电流 (IIB)：	11.5 µA
25C 时的最大偏置电流 (IIB)：	4.5 µA
最小共模抑制比：	51 dB
标称共模抑制比：	56 dB
频率补偿：	YES
最大输入失调电压：	3500 µV
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.905 mm
低-偏置：	NO
低-失调：	NO
微功率：	NO
湿度敏感等级：	2
负供电电压上限：	-6.5 V
标称负供电电压 (Vsup)：	-5 V
功能数量：	2
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TUBE
峰值回流温度（摄氏度）：	260
功率：	NO
可编程功率：	NO
认证状态：	Not Qualified
座面最大高度：	1.75 mm
最小摆率：	170 V/us
标称压摆率：	210 V/us
子类别：	Operational Amplifier
最大压摆率：	1.76 mA
供电电压上限：	6.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
标称均一增益带宽：	145000 kHz
宽带：	YES
宽度：	3.895 mm
Base Number Matches：	1

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