OPA692ID各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

OPA692

O

P

A

6

9

2

O

P

A

6

9

2

SBOS236C – MARCH 2002 – REVISED JANUARY 2003

Wideband, Fixed Gain

Video BUFFER AMPLIFIER With Disable

FEATURES

● FLEXIBLE SUPPLY RANGE:

+5V to +12V Single Supply

±2.5V to ±6V Dual Supplies

DESCRIPTION

The OPA692 provides an easy to use, broadband fixed gain

video buffer amplifier. Depending on the external connec-

tions, the internal resistor network may be used to provide

either a fixed gain of +2 video buffer or a gain of +1 or –1

voltage buffer. Operating on a very low 5.1mA supply cur-

rent, the OPA692 offers a slew rate and output power

normally associated with a much higher supply current. A

new output stage architecture delivers high output current

with minimal headroom and crossover distortion. This gives

exceptional single-supply operation. Using a single +5V

supply, the OPA692 can deliver a 1V to 4V output swing with

over 120mA drive current and > 200MHz bandwidth. This

combination of features makes the OPA692 an ideal RGB

line driver or single-supply Analog-to-Digital Converter (ADC)

input driver.

● INTERNALLY FIXED GAIN: +2 or ±1

● HIGH BANDWIDTH (G = +2): 225MHz

● LOW SUPPLY CURRENT: 5.1mA

● LOW DISABLED CURRENT: 150µA

● HIGH OUTPUT CURRENT: 190mA

● OUTPUT VOLTAGE SWING: ±4.0V

● SOT23-6 AVAILABLE

APPLICATIONS

● BROADBAND VIDEO LINE DRIVERS

● MULTIPLE LINE VIDEO DA

● PORTABLE INSTRUMENTS

● ADC BUFFERS

The low 5.1mA supply current for the OPA692 is precisely

trimmed at +25°C. This trim, along with low drift over tem-

perature, ensures a lower maximum supply current than

competing products that report only a room temperature

nominal supply current. System power may be further re-

duced by using the optional disable control pin. Leaving this

disable pin open, or holding it HIGH, gives normal operation.

If pulled LOW, the OPA692 supply current drops to less than

150µA while the I/O pins go into a high-impedance state.

● ACTIVE FILTERS

OPA692 RELATED PRODUCTS

SINGLES

OPA690

OPA691

OPA682

DUALS

OPA2690

OPA2691

OPA2682

TRIPLES

OPA3690

OPA3691

OPA3692

Voltage-Feedback

Current-Feedback

Fixed Gain

75Ω

Video

OPA692

Out

RG-59

75Ω

1

2

3

4

8

7

6

5

DIS

75Ω

+5V

Video

In

–5V

75Ω

SO-8

G = +2

225MHz, 4-Output Component Video DA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Power Supply ............................................................................... ±6.5V_DC

Internal Power Dissipation⁽²⁾............................ See Thermal Information

Differential Input Voltage⁽³⁾............................................................... ±1.2V

Input Voltage Range............................................................................ ±V_S

Storage Temperature Range: D, DVB ...........................–40°C to +125°C

Lead Temperature (soldering, 10s).............................................. +300°C

Junction Temperature (T_J) ........................................................... +175°C

ESD Resistance: HBM ........................................................................ 2kV

MM ........................................................................ 200V

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

NOTES: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability. These are stress ratings only, and functional operation of the

device at these or any other conditions beyond those specified is not implied.

(2) Packages must be derated based on specified θ_JA. Maximum T_Jmust be

observed. (3) Noninverting input to internal inverting node.

PACKAGE/ORDERING INFORMATION

SPECIFIED

PACKAGE

DESIGNATOR⁽¹⁾

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

OPA692ID

SO-8 Surface-Mount

D

"

–40°C to +85°C

OPA692

OPA692ID

OPA692IDR

Rails, 100

"

OAGI

"

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 3000

OPA692IDBV

SOT23-6

DBV

–40°C to +85°C

OPA692IDBVT

OPA692IDBVR

"

NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PIN CONFIGURATION

Top View

SO

Top View

SOT

Output

–V_S

1

2

3

6

5

4

+V_S

R_F

402Ω

DIS

R

F

NC

–IN

+IN

–V_S

1

2

3

4

8

7

6

5

DIS

R_G

402Ω

R

G

402Ω

+IN

–IN

+V_S

Output

NC

6

5

4

NC: No Connection

OAGI

1

2

3

Pin Orientation/Package Marking

OPA692

2

SBOS236C

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= ±5V

Boldface limits are tested at +25°C.

G = +2 (–IN grounded) and R_L= 100Ω (see Figure 1 for AC performance only), unless otherwise noted.

OPA692ID, IDBV

TYP

MIN/MAX OVER TEMPERATURE

0

°

C to

–40

+85°C

°

C to

MIN/

TEST

MAX LEVEL^{(2 )}

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C

UNITS

AC PERFORMANCE (see Figure 1)

Small-Signal Bandwidth (V_O< 0.5Vp-p)

G = +1

G = +2

280

225

220

120

0.2

220

2000

1.6

1.9

12

MHz

dB

typ

min

typ

C

B

C

B

C

B

C

185

180

170

G = –1

Bandwidth for 0.1dB Gain Flatness

Peaking at a Gain of +1

Large-Signal Bandwidth

Slew Rate

G = +2, V_O< 0.5Vp-p

V_O< 0.5Vp-p

40

1

35

30

2

min

max

typ

1.5

G = +2, V_O= 5Vp-p

G = +2, 4V Step

G = +2, V_O= 0.5V Step

G = +2, V_O= 5V Step

G = +2, V_O= 2V Step

G = +2, f = 5MHz, V_O= 2Vp-p

R_L= 100Ω

MHz

V/µs

ns

1400

1375

1350

min

typ

Rise-and-Fall Time

ns

typ

Settling Time to 0.02%

0.1%

ns

typ

8

ns

typ

Harmonic Distortion

2nd-Harmonic

–69

–79

–76

–94

1.7

–62

–70

–72

–87

2.5

14

–59

–67

–70

–82

2.9

15

–57

–65

–68

–78

3.1

15

dBc

max

typ

B

C

R_L≥ 500Ω

3rd-Harmonic

R_L= 100Ω

dBc

R_L≥ 500Ω

dBc

Input Voltage Noise

f > 1MHz

nV/√Hz

pA/√Hz

%

Noninverting Input Current Noise

Inverting Input Current Noise

Differential Gain

f > 1MHz

12

f > 1MHz

15

17

18

19

NTSC, R_L= 150Ω

NTSC, R_L= 37.5Ω

NTSC, R_L= 150Ω

NTSC, R_L= 37.5Ω

0.07

0.17

0.02

0.07

%

typ

Differential Phase

deg

typ

deg

typ

DC PERFORMANCE⁽³⁾

Gain Error

G = +1

G = +2

G = –1

±0.2

±0.3

±0.2

%

typ

C

A

B

±1.5

±1.6

±1.7

max

Internal R_Fand R_G

Maximum

402

457

347

462

342

0.13

±3.2

±12

+43

–300

±30

±90

464

340

Ω

max

min

A

B

A

B

A

B

A

B

Minimum

Average Drift

0.13

±2.5

0.13

±3.9

±20

%/C°

mV

max

Input Offset Voltage

V_CM= 0V

±0.5

+15

±5

Average Offset Voltage Drift

Noninverting Input Bias Current

Average Noninverting Input Bias Current Drift

Inverting Input Bias Current

Average Inverting Input Bias Current Drift

µV/°C

µA

+35

+45

–300

±40

nA/°C

µA

±25

±200

nA°C

INPUT

Common-Mode Input Range

Noninverting Input Impedance

±3.5

±3.4

±3.3

±3.2

V

min

typ

B

C

100 || 2

kΩ || pF

OUTPUT

Voltage Output Swing

No Load

±4.0

±3.9

+190

–190

±250

0.12

±3.8

±3.7

+160

–160

±3.7

±3.6

+140

–140

±3.6

±3.3

+100

–100

V

min

typ

A

C

100Ω Load

Current Output, Sourcing

Sinking

mA

Ω

Short-Circuit Current

Closed-Loop Output Impedance

V_O= 0

G = +2, f = 100kHz

typ

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C

at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by

characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V_CMis the input common-mode voltage.

OPA692

SBOS236C

3

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= ±5V (Cont.)

Boldface limits are tested at +25°C.

G = +2 (–IN grounded) and R_L= 100Ω (see Figure 1 for AC performance only), unless otherwise noted.

OPA692ID, IDBV

MIN/MAX OVER TEMPERATURE

C to –40 C to

TYP

0°

°

MIN/

TEST

MAX LEVEL^{(2 )}

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C

+85°C

UNITS

DISABLE/POWER DOWN (DIS Pin)

Power-Down Supply Current (+V_S)

Disable Time

V_DIS= 0

–150

1

–300

–350

–400

µA

µs

ns

dB

pF

mV

V

max

typ

A

C

A

V_IN= +1V_DC

G = +2, 5MHz

Enable Time

25

typ

Off Isolation

70

typ

Output Capacitance in Disable

Turn-On Glitch

4

typ

G = +2, R_L= 150Ω

±50

±20

3.3

1.8

75

typ

Turn-Off Glitch

typ

Enable Voltage

3.5

1.7

130

3.6

1.6

150

3.7

1.5

160

min

max

Disable Voltage

V

Control Pin Input Bias Current

V_DIS= 0

µA

POWER SUPPLY

Specified Operating Voltage

Maximum Operating Voltage Range

Maximum Quiescent Current

Minimum Quiescent Current

Power-Supply Rejection Ratio (–PSRR)

±5

V

typ

max

min

C

A

±6

5.3

4.9

52

±6

5.5

4.5

50

±6

5.8

4.25

49

V

V_S= ±5V

5.1

58

mA

dB

Input Referred

TEMPERATURE RANGE

Specification: D, DBV

–40 to +85

°C

typ

C

Thermal Resistance, θ_JA

D

SO-8

125

150

°C/W

typ

C

DBV SOT23-6

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C

at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by

characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V_CMis the input common-mode voltage.

OPA692

4

SBOS236C

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= +5V

Boldface limits are tested at +25°C.

G = +2 (–IN grounded though 0.1µF) and R_L= 100Ω to V_S/2 (see Figure 2 for AC performance only), unless otherwise noted.

OPA692ID, IDBV

TYP

MIN/MAX OVER TEMPERATURE

0

°

C to –40 C to

°

MIN/

TEST

MAX LEVEL^{(2 )}

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C

+85°C

UNITS

AC PERFORMANCE (see Figure 2)

Small-Signal Bandwidth (V_O< 0.5Vp-p)

G = +1

G = +2

240

190

195

90

MHz

dB

typ

min

typ

C

B

C

B

C

B

C

168

160

140

G = –1

Bandwidth for 0.1dB Gain Flatness

Peaking at a Gain of +1

Large-Signal Bandwidth

Slew Rate

G = +2, V_O< 0.5Vp-p

V_O< 0.5Vp-p

40

1

30

25

3

min

max

typ

0.2

210

830

2.0

2.3

14

2.5

G = +2, V_O= 2Vp-p

G = +2, 2V Step

G = +2, V_O= 0.5V Step

G = +2, V_O= 2V Step

G = +2, f = 5MHz, V_O= 2Vp-p

R_L= 100Ω to V_S/2

R_L≥ 500Ω to V_S/2

R_L= 100Ω to V_S/2

R_L≥ 500Ω to V_S/2

f > 1MHz

MHz

V/µs

ns

600

575

550

min

typ

Rise-and-Fall Time

ns

typ

Settling Time to 0.02%

0.1%

ns

typ

10

ns

typ

Harmonic Distortion

2nd-Harmonic

–66

–73

–72

–77

1.7

12

–58

–65

–68

–72

2.5

14

–57

–63

–67

–70

2.9

15

–56

–62

–65

–69

3.1

15

dBc

max

B

3rd-Harmonic

dBc

Input Voltage Noise

nV/√Hz

pA/√Hz

Noninverting Input Current Noise

Inverting Input Current Noise

f > 1MHz

15

17

18

19

DC PERFORMANCE⁽³⁾

Gain Error

G = +1

G = +2

G = –1

±0.2

±0.3

±0.2

%

typ

C

A

B

±1.5

±1.6

±1.7

max

Internal R_Fand R_G

Maximum

402

457

347

0.13

±3

462

342

464

340

Ω

max

min

B

A

B

A

B

A

B

Minimum

Average Drift

0.13

±3.6

±12

0.13

±4.3

±20

%/C°

mV

max

Input Offset Voltage

V_CM= 2.5V

±0.5

+20

±5

Average Offset Voltage Drift

Noninverting Input Bias Current

Average Noninverting Input Bias Current Drift

Inverting Input Bias Current

Average Inverting Input Bias Current Drift

µV/°C

µA

+40

+46

+56

–250

±30

–250

±40

nA/°C

µA

±25

±112

±200

nA°C

INPUT

Least Positive Input Voltage

Most Positive Input Voltage

Noninverting Input Impedance

1.5

3.5

1.6

3.4

1.7

3.3

1.8

3.2

V

max

min

typ

B

C

100 || 2

kΩ || pF

OUTPUT

Most Positive Output Voltage

No Load

R_L= 100Ω

No Load

4.0

3.9

3.8

3.7

3.6

3.5

3.4

1.5

1.6

+80

–80

V

min

max

min

typ

A

C

Least Positive Output Voltage

1.0

1.2

1.3

V

R_L= 100Ω

1.1

1.3

1.4

V

Current Output, Sourcing

Sinking

+160

–160

±250

+120

–120

+100

–100

mA

Short-Circuit Current

V_O= V_S/2

Output Impedance

G = +2, f = 100kHz

0.12

Ω

typ

C

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C

at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by

characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V_CMis the input common-mode voltage.

OPA692

SBOS236C

5

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= +5V (Cont.)

Boldface limits are tested at +25°C.

G = +2 (–IN grounded though 0.1µF) and R_L= 100Ω to V_S/2 (see Figure 2 for AC performance only), unless otherwise noted.

OPA692ID, IDBV

TYP

MIN/MAX OVER TEMPERATURE

0

°

C to –40 C to

°

MIN/

TEST

MAX LEVEL^{(2 )}

PARAMETER

CONDITIONS

+25°C⁽¹⁾

+25°C

–300

70°C

+85°C

UNITS

DISABLE/POWER DOWN (DIS Pin)

Power-Down Supply Current (+V_S)

Off Isolation

V_DIS= 0

–150

65

–350

–400

µA

dB

pF

mV

V

typ

C

B

C

G = +2, 5MHz

Output Capacitance in Disable

Turn-On Glitch

4

typ

G = +2, R_L= 150Ω, V_IN= 2.5V

±50

±20

3.3

1.8

75

typ

Turn-Off Glitch

typ

Enable Voltage

3.5

1.7

130

3.6

1.6

150

3.7

1.5

160

min

max

typ

Disable Voltage

V

Control Pin Input Bias Current (DIS

)

V_DIS= 0

µA

POWER SUPPLY

Specified Single-Supply Operating Voltage

Maximum Single-Supply Operating Voltage

Maximum Quiescent Current

5

V

typ

max

min

typ

C

A

C

12

4.8

4.1

12

5.0

3.8

12

5.2

3.7

V_S= +5V

4.5

55

mA

dB

Minimum Quiescent Current

Power-Supply Rejection Ratio (+PSRR)

Input Referred

TEMPERATURE RANGE

Specification: D, DBV

–40 to +85

°C

typ

C

Thermal Resistance, θ_JA

D

SO-8

125

150

°C/W

typ

C

DBV SOT23-6

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C

at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by

characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V_CMis the input common-mode voltage.

OPA692

6

SBOS236C

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V

T_A= +25°C, G = +2, and R_L= 100Ω (see Figure 1 for DC performance only), unless otherwise noted.

SMALL-SIGNAL FREQUENCY RESPONSE

LARGE-SIGNAL FREQUENCY RESPONSE

1

0

7

6

5

4

3

2

1

0

V_O= 1Vp-p

V_O= 2Vp-p

G = +1

G = –1

–1

–2

–3

–4

–5

–6

–7

–8

V_O= 4Vp-p

V_O= 7Vp-p

G = +2

0

250MHz

500MHz

0

125MHz

250MHz

Frequency (50MHz/div)

Frequency (25MHz/div)

SMALL-SIGNAL PULSE RESPONSE

LARGE-SIGNAL PULSE RESPONSE

4

3

400

300

V_O= 5Vp-p

G = +2

V_O= 0.5Vp-p

G = +2

2

200

1

100

0

–1

–2

–3

–4

–100

–200

–300

–400

Time (5ns/div)

COMPOSITE VIDEO dG/dP

DISABLED FEEDTHROUGH vs FREQUENCY

V_DIS= 0

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

+5V

DIS

No Pull-Down

With 1.3kΩ Pull-Down

Video In

Video Loads

OPA692

dG

Optional

1.3kΩ

Pull-Down

–5V

dG

Reverse

Forward

dP

1

2

3

4

0.5

1

10

100

Frequency (MHz)

Number of 150Ω Loads

OPA692

SBOS236C

7

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, and R_L= 100Ω (see Figure 1 for DC performance only), unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE

–60

–65

–50

–55

–60

–65

–70

–75

–80

–85

–90

V_O= 2Vp-p

f = 5MHz

V_O= 2Vp-p

R_L= 100Ω

f = 5MHz

–70

2nd-Harmonic

3rd-Harmonic

–75

2nd-Harmonic

–80

–85

–90

–95

–100

–105

–110

3rd-Harmonic

100

1000

2

2.5

3

3.5

4

4.5

5

5.5

6

Load Resistance (Ω)

Supply Voltage (±V_S)

HARMONIC DISTORTION vs OUTPUT VOLTAGE

HARMONIC DISTORTION vs FREQUENCY (G = +2)

V_O= 2Vp-p

–65

–70

–75

–80

–85

–50

–60

R_L= 100Ω

f = 5MHz

dBc = dB Below Carrier

2nd-Harmonic

R_L= 100Ω

2nd-Harmonic

–70

–80

3rd-Harmonic

–90

–100

0.1

1

5

0.1

1

10

20

Output Voltage Swing (Vp-p)

Frequency (MHz)

HARMONIC DISTORTION vs FREQUENCY (G = –1)

HARMONIC DISTORTION vs FREQUENCY (G = +1)

V_O= 2Vp-p

–50

–60

–50

–60

V_O= 2Vp-p

dBc = dB Below Carrier

R_L= 100Ω

2nd-Harmonic

–70

3rd-Harmonic

–80

3rd-Harmonic

–90

2nd-Harmonic

–100

0.1

1

10

20

0.1

1

10

20

Frequency (MHz)

OPA692

8

SBOS236C

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, and R_L= 100Ω (see Figure 1 for DC performance only), unless otherwise noted.

2-TONE, 3RD-ORDER

INPUT VOLTAGE AND CURRENT NOISE DENSITY

INTERMODULATION SPURIOUS

100

10

1

–30

–40

–50

–60

–70

–80

–90

dBc = dB below carriers

50MHz

Inverting Input Current Noise (15pA/√Hz)

Noninverting Current Noise (12pA/√Hz)

Voltage Noise (1.7nV/√Hz)

20MHz

10MHz

Load Power at Matched 50Ω Load

100

1k

10k

100k

1M

10M

–8

–6

–4

–2

0

2

4

6

8

10

Frequency (Hz)

Single-Tone Load Power (dBm)

RECOMMENDED R_Svs CAPACITIVE LOAD

FREQUENCY RESPONSE vs CAPACITIVE LOAD

60

50

40

30

20

10

0

9

6

C_L= 10pF

3

C_L= 47pF

0

C_L= 22pF

–3

–6

–9

V_IN

C_L= 100pF

R_S

V_O

OPA692

402Ω

C_L

1kΩ

402Ω

1kΩ is optional.

1

10

100

1k

0

125MHz

Frequency (25MHz/div)

250MHz

Capacitive Load (pF)

PSRR vs FREQUENCY

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

65

60

55

50

45

40

35

30

25

20

10

8

250

200

150

100

50

Sourcing Output Current

Sinking Output Current

+PSRR

–PSRR

6

4

Quiescent Supply Current

2

0

1k

10k

100k

1M

10M

100M

–50

–25

0

25

50

75

100

125

Frequency (Hz)

Ambient Temperature (°C)

OPA692

SBOS236C

9

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TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +2, and R_L= 100Ω (see Figure 1 for DC performance only), unless otherwise noted.

TYPICAL DC DRIFT OVER TEMPERATURE

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

2

1.5

1

40

5

4

Output Current Limited

1W Internal

Power Limit

Noninverting Input Bias Current

30

3

20

2

0.5

0

10

1

Inverting Input Bias Current

25Ω

Load Line

0

–1

–2

–3

–4

–5

–0.5

–1

–10

–20

–30

–40

50Ω Load Line

100Ω Load Line

1W Internal

Input Offset Voltage

–1.5

–2

Power Limit

Output Current Limit

–50

–25

0

25

50

75

100

125

–300 –250 –200 –150 –100 –50

0

50 100 150 200 250 300

Ambient Temperature (°C)

I_O(mA)

LARGE-SIGNAL DISABLE/ENABLE RESPONSE

V_DIS

DISABLE/ENABLE GLITCH

V_DIS

6.0

4.0

2.0

0

6.0

4.0

2.0

0

2.0

1.6

1.2

0.8

0.4

0

30

20

Output Voltage

(0V Input)

Output Voltage

10

0

–10

–20

V_IN= +1V

Time (200ns/div)

Time (20ns/div)

CLOSED-LOOP OUTPUT IMPEDANCE

10

+5V

OPA692

50Ω

Z_O

–5V

402Ω

1

402Ω

0.1

10k

100k

1M

10M

100M

Frequency (Hz)

OPA692

10

SBOS236C

www.ti.com

TYPICAL CHARACTERISTICS: V_S= +5V

T_A= +25°C, G = +2, and R_L= 100Ω (see Figure 2 for AC performance only), unless otherwise noted.

SMALL-SIGNAL FREQUENCY RESPONSE

LARGE-SIGNAL FREQUENCY RESPONSE

V_O= 0.5Vp-p

1

0

7

6

5

4

3

2

1

0

G = +1

–1

–2

–3

–4

–5

–6

–7

–8

V_O= 1Vp-p

G = –1

V_O= 2Vp-p

G = +2

R_L= 100Ω to 2.5V

0

250M

500M

0

125M

Frequency (Hz)

250M

Frequency (Hz)

SMALL-SIGNAL PULSE RESPONSE

LARGE-SIGNAL PULSE RESPONSE

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

4.1

3.7

3.3

2.9

2.5

2.1

1.7

1.3

0.9

G = +2

_O= 0.5Vp-p

G = +2

V_O= 2Vp-p

V

Time (5ns/div)

RECOMMENDED R_Svs CAPACITIVE LOAD

FREQUENCY RESPONSE vs CAPACITIVE LOAD

C_L= 10pF

70

60

50

40

30

20

10

0

9

6

C_L= 22pF

3

C_L= 47pF

0

+5V

–3

–6

–9

806Ω

0.1µF

57.6Ω

V

IN

R

C_L= 100pF

S

V

O

OPA692

C

1kΩ

L

402Ω

0.1µF

(1kΩ is optional)

1

10

100

1k

0

125MHz

Frequency (25MHz/div)

250MHz

Capacitive Load (pF)

OPA692

SBOS236C

11

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TYPICAL CHARACTERISTICS: V_S= +5V (Cont.)

T_A= +25°C, G = +2, and R_L= 100Ω (see Figure 2 for AC performance only), unless otherwise noted.

HARMONIC DISTORTION vs FREQUENCY

HARMONIC DISTORTION vs LOAD RESISTANCE

–60

–65

–70

–75

–80

–50

–60

–70

–80

–90

V_O= 2Vp-p

f = 5MHz

V_O= 2Vp-p

_L= 100Ω to 2.5V

R

2nd-Harmonic

3rd-Harmonic

0.1

1

10

20

100

1k

Frequency (MHz)

Load Resistance (Ω)

2-TONE, 3RD-ORDER

INTERMODULATION SPURIOUS

HARMONIC DISTORTION vs OUTPUT VOLTAGE

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–60

–65

–70

–75

–80

dBc = dB Below Carriers

R_L= 100Ω to 2.5V

f = 5MHz

50MHz

2nd-Harmonic

20MHz

10MHz

3rd-Harmonic

Load Power at Matched 50Ω Load

–6 –4 –2

Single-Tone Load Power (dBm)

–14

–12

–10

–8

0

2

0.1

1

2

3

Output Voltage Swing (Vp-p)

OPA692

12

SBOS236C

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Figure 2 shows the AC-coupled, gain of +2, single-supply

circuit configuration used as the basis of the +5V Electrical

and Typical Characteristics. Though not a rail-to-rail design,

the OPA692 requires minimal input and output voltage head-

room compared to other very wideband current-feedback op

amps. It will deliver a 3Vp-p output swing on a single +5V

supply with greater than 150MHz bandwidth. The key re-

quirement of broadband single-supply operation is to main-

tain input and output signal swings within the usable voltage

ranges at both the input and the output. The circuit of Figure

2 establishes an input midpoint bias using a simple resistive

divider from the +5V supply (two 806Ω resistors). The input

signal is then AC-coupled into this midpoint voltage bias. The

input voltage can swing to within 1.5V of either supply pin,

giving a 2Vp-p input signal range centered between the

supply pins. The input impedance matching resistor (57.6Ω)

used for testing is adjusted to give a 50Ω input match when

the parallel combination of the biasing divider network is

included. The gain resistor (R_G) is AC-coupled, giving the

circuit a DC gain of +1—which puts the input DC bias voltage

(2.5V) on the output as well. Again, on a single +5V supply,

the output voltage can swing to within 1V of either supply pin

while delivering more than 120mA output current. A demand-

ing 100Ω load to a midpoint bias is used in this characteriza-

tion circuit. The new output stage used in the OPA692 can

deliver large bipolar output currents into this midpoint load

with minimal crossover distortion, as shown by the +5V

supply, 3rd-harmonic distortion typical characteristics.

APPLICATIONS INFORMATION

WIDEBAND BUFFER OPERATION

The OPA692 gives the exceptional AC performance of a

wideband current-feedback op amp with a highly linear, high-

power output stage. It features internal R_Fand R_Gresistors

that make it easy to select a gain of +2, +1, or –1 without any

external resistors. Requiring only 5.1mA quiescent current, the

OPA692 will swing to within 1V of either supply rail and deliver

in excess of 160mA at room temperature. This low output

headroom requirement, along with supply voltage indepen-

dent biasing, gives remarkable single (+5V) supply operation.

The OPA692 will deliver greater than 200MHz bandwidth

driving a 2Vp-p output into 100Ω on a single +5V supply.

Previous boosted output stage amplifiers have typically suf-

fered from very poor crossover distortion as the output current

goes through zero. The OPA692 achieves a comparable

power gain with much better linearity. The primary advantage

of a current-feedback op amp over a voltage-feedback op amp

is that AC performance (bandwidth and distortion) is relatively

independent of signal gain.

Figure 1 shows the DC-coupled, gain of +2, dual power-supply

circuit configuration used as the basis of the ±5V Electrical and

Typical Characteristics. For test purposes, the input imped-

ance is set to 50Ω with a resistor to ground and the output

impedance is set to 50Ω with a series output resistor. Voltage

swings reported in the specifications are taken directly at the

input and output pins while load powers (dBm) are defined at

a matched 50Ω load. For the circuit of Figure 1, the total

effective load will be 100Ω || 804Ω = 89Ω. The disable control

line (DIS) is typically left open to ensure normal amplifier

operation. In addition to the usual power-supply decoupling

capacitors to ground, a 0.1µF capacitor can be included

between the two power-supply pins. This optional added

capacitor will typically improve the 2nd-harmonic distortion

performance by 3dB to 6dB.

+V_S

+5V

+

0.1µF

6.8µF

50Ω Source

0.1µF

806Ω

DIS

V_IN

V_O100Ω

57.6Ω

+5V

V_S/2

OPA692

DIS

R_F

402Ω

+

0.1µF

6.8µF

50Ω Source

R_G

402Ω

V_IN

50Ω Load

50Ω

0.1µF

OPA692

R_F

402Ω

FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification

and Test Circuit.

R_G

SINGLE-SUPPLY ADC INTERFACE

402Ω

0.1µF

6.8µF

Most modern, high-performance ADCs (such as the Texas

Instruments ADS8xx and ADS9xx series) operate on a single

+5V (or lower) power supply. It has been a considerable

challenge for single-supply op amps to deliver a low-distor-

tion input signal at the ADC input for signal frequencies

+

–5V

FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-

tion and Test Circuit.

OPA692

SBOS236C

13

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exceeding 5MHz. The high slew rate, exceptional output

swing, and high linearity of the OPA692 make it an ideal

single-supply ADC driver. Figure 3 shows an example input

interface to a very high performance 10-bit, 60MSPS CMOS

converter.

the output, centering the output voltage swing as well. Tested

performance at a 20MHz analog input frequency and a 60MSPS

clock rate on the converter gives > 58dBc SFDR.

WIDEBAND VIDEO MULTIPLEXING

The OPA692 in the circuit of Figure 3 provides 190MHz

bandwidth operating at a signal gain of +2 with a 2Vp-p output

swing. The noninverting input bias voltage is referenced to the

midpoint of the ADC signal range by dividing off the top and

bottom of the internal ADC reference ladder. With the gain

resistor (R_G) AC-coupled, this bias voltage has a gain of +1 to

One common application for video speed amplifiers that

include a disable pin is to wire multiple amplifier outputs

together, then select which one of several possible video

inputs to source onto a single line. This simple wired-OR

video multiplexer can be easily implemented using the

OPA692, as shown in Figure 4.

+5V

R_F

402Ω

R_G

ADS826

10-Bit

60MSPS

0.1µF

Clock

402Ω

50Ω

Input

OPA692

2Vp-p

DIS

22pF

Input

1Vp-p

0.1µF

CM

2kΩ

+3.5V

REFT

0.1µF

+2.5V DC Bias

2kΩ

+1.5V

REFB

0.1µF

FIGURE 3. Wideband, AC-Coupled, Single-Supply ADC Driver.

+5V

2kΩ

|V_OUT| < 2.6V

V_DIS

+5V

Video 1

DIS

OPA692

75Ω

68.1Ω

–5V

402Ω

75Ω Cable

RG-59

V_OUT

+5V

68.1Ω

OPA692

Video 2

DIS

75Ω

–5V

2kΩ

FIGURE 4. 2-Channel Video Multiplexer.

OPA692

14

SBOS236C

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Typically, channel switching is performed either on sync or

retrace time in the video signal. The two inputs are approxi-

mately equal at this time. The make-before-break disable

characteristic of the OPA692 ensures that there is always

one amplifier controlling the line when using a wired-OR

circuit (see Figure 4). Since both inputs may be on for a short

period during the transition between channels, the outputs

are combined through the output impedance matching resis-

tors (68.1Ω in this case). When one channel is disabled, its

feedback network forms part of the output impedance and

slightly attenuates the signal in getting out onto the cable.

The matching resistors have been set to get a signal gain of

+1 at the load while providing > 20dB return loss at the load.

4-CHANNEL FREQUENCY CHANNELIZER

The circuit of Figure 5 is a 4-channel multiplexer. In this

circuit the OPA691 provides the drive for all four channels.

Each channel includes a bandpass filter and each bandpass

filter is set for a different frequency band. This allows the

channelizing part of this circuit. The role of the OPA692 is to

provide impedance isolation. This is done through the use of

four matching resistances (59Ω in this case). These match-

ing resistors ensure that the signals will combine during the

transition between channels. They have been used to get a

gain of +1 at the load.

This circuit may be used with a different number of channels.

Its limitation comes from the drive requirement for each

channel, as well as the minimum acceptable return loss.

The video multiplexer connection (see Figure 4) also insures

that the maximum differential voltage across the inputs of the

unselected channel do not exceed the rated ±1.2V maximum

for standard video signal levels. In any case, V_OUTmust be

< ±2.6Vp-p in order to not exceed the absolute maximum

differential input voltage (±1.2V) on the disabled channel.

The output resistor value (R_O) to keep a gain of +1 at the

load, depends on the number of channels. For the OPA692,

Equation 1 gives:

(1)

The Disable Operation section shows the turn-on and turn-off

switching glitches using a grounded input for a single chan-

nel is typically less than ±50mV. Where two outputs are

switched (see Figure 4), the output line is always under the

control of one amplifier or the other due to the make-before-

break disable timing. In this case, the switching glitches for

two 0V inputs drops to < 20mV.

75Ω • n – 2 + 804Ω

(

)

[

]

241200Ω

R_O

=

•

1+

–1

2

75Ω • n − 2 + 804Ω

(

)

[

]

Where n = number of devices in multiplexer.

+5V

DIS 1

DIS 2

DIS 3

DIS 4

75Ω

R_O

59Ω

#1

OPA692

75Ω

–5V

+5V

75Ω

R_O

59Ω

#2

OPA692

+5V

75Ω

75Ω Cable

–5V

V_OUT

OPA691

+5V

RG-59

75Ω

R_O

75Ω Load

59Ω

#3

–5V

OPA692

75Ω

–5V

+5V

75Ω

R_O

59Ω

#4

OPA692

75Ω

–5V

G = +2 Stages

FIGURE 5. 4-Channel Frequency Channelizer.

OPA692

SBOS236C

15

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DELAY-EQUALIZED LOW-PASS FILTER

The circuit in Figure 6 realizes a 5th-order Butterworth low-

pass filter with a –3dB bandwidth of 20MHz and group delay

equalization. This filter is based on the KRC active filter

topology using amplifiers with a fixed positive gain ≥ 1.

V_IN

200Ω

V_OUT

OPA692

+5V

The OPA692 makes a good amplifier for this type of filter. The

first stage is the group delay equalizer, which is based on a

gain of –1. The second stage has a high-Q pole, uses a gain

of +2 for minimum component sensitivity, and also produces a

real pole. The last stage has a low-Q pole, and uses a gain of

+1 for minimum component sensitivity.

80.6kΩ

200Ω

402Ω

2.7nF

OPA227

–5V

2.7nF

The component values have been predistorted to compensate

for the op amps parasitic effects. The low-Q pole section was

placed last to minimize noise peaking in the passband, while

maintaining good dynamic range performance.

FIGURE 7. Precision Wideband, Unity-Gain Buffer.

PRECISION VOLTAGE BUFFER

DESIGN-IN TOOLS

The precision buffer in Figure 7 combines the DC precision

and low 1/f noise of the OPA227 with the high-speed perfor-

mance of the OPA692. The 80.6kΩ resistor makes the high-

frequency and low-frequency nominal gains equal. The

OPA692 takes over from the OPA227 at approximately 32kHz.

DEMONSTRATION BOARDS

Two PC boards are available to assist in the initial evaluation

of circuit performance using the OPA692 in its two package

styles. All of these are available free as an unpopulated PC

56pF

402Ω

49.9Ω

105Ω

226Ω

V_IN

OPA692

220pF

27pF

115Ω

OPA692

402Ω

100pF

402Ω

68pF

95.3Ω

226Ω

V_OUT

OPA692

39pF

402Ω

(Open)

FIGURE 6. Butterworth LP Filter with Delay Equalization.

OPA692

16

SBOS236C

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board delivered with descriptive documentation. The sum-

mary information for these boards is shown in the table

below.

over-temperature specifications because the output stage

junction temperatures are higher than the minimum specified

operating ambient.

DRIVING CAPACITIVE LOADS

BOARD

PART

NUMBER

LITERATURE

REQUEST

NUMBER

One of the most demanding and yet very common load

conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an ADC—including additional

external capacitance which may be recommended to improve

ADC linearity. A high-speed amplifier like the OPA692 can be

very susceptible to decreased stability and frequency re-

sponse peaking when a capacitive load is placed directly on

the output pin. When the amplifier’s open-loop output resis-

tance is considered, this capacitive load introduces an addi-

tional pole in the signal path that can decrease the phase

margin. Several external solutions to this problem have been

suggested. When the primary considerations are frequency

response flatness, pulse response fidelity, and/or distortion,

the simplest and most effective solution is to isolate the

capacitive load from the feedback loop by inserting a series

isolation resistor between the amplifier output and the capaci-

tive load. This does not eliminate the pole from the loop

response, but rather shifts it and adds a zero at a higher

frequency. The additional zero acts to cancel the phase lag

from the capacitive load pole, thus increasing the phase

margin and improving stability.

PRODUCT

PACKAGE

OPA692ID

OPA692IDBV

SO-8

SOT23-6

DEM-OPA68xU

DEM-OPA6xxN

SBOU009

SBOU010

To request any of these boards, check the Texas Instruments

web site at www.ti.com.

OPERATING SUGGESTIONS

GAIN SETTING

Setting the gain with the OPA692 is very easy. For a gain of

+2, ground the –IN pin and drive the +IN pin with the signal.

For a gain of +1, leave the –IN pin open and drive the +IN pin

with the signal. For a gain of –1, ground the +IN pin and drive

the –IN pin with the signal. As the internal resistor values (not

their ratio) change over temperature and process, external

resistors should not be used to modify the gain.

OUTPUT CURRENT AND VOLTAGE

The OPA692 provides output voltage and current capabilities

that are unsurpassed in a low-cost monolithic op amp. Under

no-load conditions at +25°C, the output voltage typically

swings closer than 1V to either supply rail; the tested swing

limit is within 1.2V of either rail. Into a 15Ω load (the minimum

tested load), it is specified to deliver more than ±160mA.

The Typical Characteristics show the recommended “R_Svs

Capacitive Load” and the resulting frequency response at the

load. Parasitic capacitive loads greater than 2pF can begin to

degrade the performance of the OPA692. Long PC board

traces, unmatched cables, and connections to multiple de-

vices can easily cause this value to be exceeded. Always

consider this effect carefully, and add the recommended

series resistor as close as possible to the OPA692 output pin

(see the Board Layout Guidelines section).

The specifications described previously, though familiar in

the industry, consider voltage and current limits separately. In

many applications, it is the voltage times current, or V-I

product, which is more relevant to circuit operation. Refer to

the “Output Voltage and Current Limitations” plot in the

Typical Characteristics. The X- and Y-axes of this graph show

the zero-voltage output current limit and the zero-current

output voltage limit, respectively. The four quadrants give a

more detailed view of the OPA692 output drive capabilities,

noting that the graph is bounded by a safe operating area of

1W maximum internal power dissipation. Superimposing

resistor load lines onto the plot shows that the OPA692 can

drive ±2.5V into 25Ω, or ±3.5V into 50Ω without exceeding

the output capabilities or the 1W dissipation limit. A 100Ω

load line (the standard test circuit load) shows the full ±3.9V

output swing capability (see the Electrical Characteristics).

DISTORTION PERFORMANCE

The OPA692 provides good distortion performance into a

100Ω load on ±5V supplies. Relative to alternative solutions, it

provides exceptional performance into lighter loads and/or

operating on a single +5V supply. Generally, until the funda-

mental signal reaches very high-frequency or power levels, the

2nd-harmonic will dominate the distortion with a negligible 3rd-

harmonic component. Focusing then on the 2nd-harmonic,

increasing the load impedance improves distortion directly.

Remember that the total load includes the feedback network—

in the noninverting configuration (see Figure 1) this is the sum

of R_F+ R_G, while in the inverting configuration, it is just R_F.

Also, providing an additional supply decoupling capacitor

(0.1µF) between the supply pins (for bipolar operation) im-

proves the 2nd-order distortion slightly (3dB to 6dB).

The minimum specified output voltage and current over

temperature are set by worst-case simulations at the cold

temperature extreme. Only at cold startup will the output

current and voltage decrease to the numbers shown in the

Electrical Characteristics. As the output transistors deliver

power, their junction temperatures increase, decreasing their

In most op amps, increasing the output voltage swing increases

harmonic distortion directly. The Typical Characteristics show the

2nd-harmonic increasing at a little less than the expected 2x rate

while the 3rd-harmonic increases at a much lower rate than the

expected 3x. Where the test power doubles, the difference

between it and the 2nd-harmonic decreases less than the

V

_BEs (increasing the available output voltage swing), and

increasing their current gains (increasing the available output

current). In steady-state operation, the available output volt-

age and current is always greater than that shown in the

OPA692

SBOS236C

17

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expected 6dB, while the difference between it and the 3rd

decreases by less than the expected 12dB. This also shows up

in the 2-tone, 3rd-order intermodulation spurious (IM3) response

curves. The 3rd-order spurious levels are extremely low at low

output power levels. The output stage continues to hold them low

even as the fundamental power reaches very high levels. As the

Typical Characteristics show, the spurious intermodulation pow-

ers do not increase as predicted by a traditional intercept model.

As the fundamental power level increases, the dynamic range

does not decrease significantly. For two tones centered at

20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2Vp-p

for each tone at the load, which requires 8Vp-p for the overall

2-tone envelope at the output pin), the Typical Characteristics

show 58dBc difference between the test-tone power and the 3rd-

order intermodulation spurious levels. This exceptional perfor-

mance improves further when operating at lower frequencies.

square root of the sum of all squared output noise voltage

contributors. Equation 2 shows the general form for the output

noise voltage using the terms shown in Figure 8.

(2)

2

E_O

=

E_NI+ I_BNR_S+ 4kTR_SNG²+ I R

+ 4kTR_FNG

(

)

(

)

BI

F

Dividing this expression by the noise gain (NG = (1 + R_F/R_G))

will give the equivalent input-referred spot noise voltage at the

noninverting input, as shown in Equation 3.

(3)

2

I_BIR_F

NG

4kTR_F

NG

2

E_N

=

E_NI+ I_BNR_S+ 4kTR_S

+

(

)

Evaluating these two equations for the OPA692 circuit and

component values (see Figure 1) will give a total output spot

noise voltage of 8.2nV/√Hz and a total equivalent input spot

noise voltage of 4.1nV/√Hz. This total input-referred spot

noise voltage is higher than the 1.7nV/√Hz specification for

the op amp voltage noise alone. This reflects the noise added

to the output by the inverting current noise times the feed-

back resistor.

NOISE PERFORMANCE

The OPA692 offers an excellent balance between voltage and

current noise terms to achieve low output noise. The inverting

current noise (15pA/√Hz) is significantly lower than earlier

solutions while the input voltage noise (1.7nV√Hz) is lower

than most unity-gain stable, wideband, voltage-feedback op

amps. This low input voltage noise was achieved at the price

of higher noninverting input current noise (12pA/√Hz). As long

as the AC source impedance looking out of the noninverting

node is less than 100Ω, this current noise will not contribute

significantly to the total output noise. The op amp input voltage

noise and the two input current noise terms combine to give

low output noise for the gain settings, available using the

OPA692. Figure 8 shows the op amp noise analysis model

with all the noise terms included. In this model, all noise terms

are taken to be noise voltage or current density terms in either

DC ACCURACY

The OPA692 provides exceptional bandwidth in high gains,

giving fast pulse settling but only moderate DC accuracy. The

Electrical Characteristics show an input offset voltage com-

parable to high-speed voltage-feedback amplifiers. However,

the two input bias currents are somewhat higher and are

unmatched. Bias current cancellation techniques will not

reduce the output DC offset for OPA692. As the two input

bias currents are unrelated in both magnitude and polarity,

matching the source impedance looking out of each input to

reduce their error contribution to the output is ineffective.

Evaluating the configuration of Figure 1, using worst-case

+25°C input offset voltage and the two input bias currents,

gives a worst-case output offset range equal to:

nV/√Hz or pA/√Hz

.

The total output spot noise voltage can be computed as the

±(NG • V_OS(max)) + (I_BN• R_S/2 • NG) ± (I_BI• R_F)

where NG = noninverting signal gain

= ±(2 • 2.5mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA)

= ±5mV + 1.75mV ± 10.05mV

E_NI

E_O

OPA692

R_S

I_BN

= –13.3mV → +16.80mV

Minimizing the resistance seen by the noninverting input will

give the best DC offset performance.

E_RS

R_F

√4kTR_S

For significantly improved DC accuracy, consider the preci-

sion buffer circuit (see Figure 7).

√4kTR_F

I_BI

R_G

4kT

R_G

4kT = 1.6E –20J

at 290°K

DISABLE OPERATION

The OPA692 provides an optional disable feature that may be

used either to reduce system power or to implement a simple

channel multiplexing operation. If the DIS control pin is left

unconnected, the OPA692 will operate normally. To disable,

FIGURE 8. Noise Model.

OPA692

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the control pin must be asserted LOW. Figure 9 shows a

simplified internal circuit for the disable control feature.

THERMAL ANALYSIS

Due to the high output power capability of the OPA692,

heatsinking or forced airflow may be required under extreme

operating conditions. Maximum desired junction temperature

will set the maximum allowed internal power dissipation, as

described below. In no case should the maximum junction

temperature be allowed to exceed 175°C.

In normal operation, base current to Q1 is provided through

+V_S

Operating junction temperature (T_J) is given by T_A+ P_D• θ_JA.

The total internal power dissipation (P_D) is the sum of

quiescent power (P_DQ) and additional power dissipated in the

output stage (P_DL) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total

supply voltage across the part. P_DLdepends on the required

output signal and load but would, for a grounded resistive

load, be at a maximum when the output is fixed at a voltage

equal to 1/2 either supply voltage (for equal bipolar supplies).

15kΩ

Q1

110kΩ

25kΩ

–V_S

I_S

2

V_DIS

Under this condition P_DL= V_S/(4 • R_L), where R_Lincludes

Control

feedback network loading.

Note that it is the power in the output stage and not in the

load that determines internal power dissipation.

FIGURE 9. Simplified Disable Control Circuit.

As a worst-case example, compute the maximum T_Jusing an

OPA692IDBV (SOT23-6 package) in the circuit of Figure 1

operating at the maximum specified ambient temperature of

the 110kΩ resistor while the emitter current through the 15kΩ

resistor sets up a voltage drop that is inadequate to turn on

the two diodes in Q1’s emitter. As V_DISis pulled LOW,

additional current is pulled through the 15kΩ resistor eventu-

ally turning on these two diodes (≈ 75µA). At this point, any

further current pulled out of V_DISgoes through those diodes

holding the emitter-base voltage of Q1 at approximately 0V.

This shuts off the collector current out of Q1, turning the

amplifier off. The supply current in the disable mode is only

that required to operate the circuit of Figure 8. Additional

circuitry ensures that turn-on time occurs faster than turn-off

time (make-before-break).

+85°C and driving a grounded 20Ω load to +2.5V_DC

:

P_D= 10V • 5.8mA + 5²/(4 • (20Ω || 800Ω)) = 378mW

Maximum T_J= +85°C + (0.39W • 150°C/W) = 142°C

Although this is still well below the specified maximum

junction temperature, system reliability considerations may

require lower junction temperatures. Remember, this is a

worst-case internal power dissipation—use your actual sig-

nal and load to compute P_DL. The highest possible internal

dissipation occurs if the load requires current to be forced

into the output for positive output voltages or sourced from

the output for negative output voltages. This puts a high

current through a large internal voltage drop in the output

transistors. The “Output Voltage and Current Limitations” plot

shown in the Typical Characteristics include a boundary for

1W maximum internal power dissipation under these condi-

tions.

When disabled, the output and input nodes go to a high-

impedance state. If the OPA692 is operating in a gain of +1,

this will show a very high impedance (4pF || 1MΩ) at the

output and exceptional signal isolation. If operating at a gain

of +2, the total feedback network resistance (R_F+ R_G) will

appear as the impedance looking back into the output, but

the circuit will still show very high forward and reverse

isolation. If configured at a gain of –1, the input and output

will be connected through the feedback network resistance

(R_F+ R_G) giving relatively poor input to output isolation.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-

plifier like the OPA692 requires careful attention to board

layout parasitics and external component types. Recommen-

dations that will optimize performance include:

One key parameter in disable operation is the output glitch

when switching in and out of the disabled mode. The Typical

Characteristics show these glitches for the circuit of Figure 1

with the input signal set to 0V. The glitch waveform at the

output pin is plotted along with the DIS pin voltage.

a) Minimize parasitic capacitance to any AC ground for

all of the signal I/O pins. Parasitic capacitance on the

output pin can cause instability: on the noninverting input, it

can react with the source impedance to cause unintentional

bandlimiting. To reduce unwanted capacitance, a window

around the signal I/O pins should be opened in all of the

ground and power planes around those pins. Otherwise,

ground and power planes should be unbroken elsewhere on

the board.

The transition edge rate (dV/dt) of the DIS control line will

influence this glitch. Slowing this edge can be achieved by

adding a simple RC filter into the V_DISpin from a higher

speed logic line. If extremely fast transition logic is used, a

2kΩ series resistor between the logic gate and the DIS input

pin will provide adequate bandlimiting using just the parasitic

input capacitance on the DIS pin while still ensuring an

adequate logic level swing.

OPA692

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b) Minimize the distance (< 0.25") from the power-supply

pins to high-frequency 0.1µF decoupling capacitors. At

the device pins, the ground and power-plane layout should

not be in close proximity to the signal I/O pins. Avoid narrow

power and ground traces to minimize inductance between

the pins and the decoupling capacitors. The power-supply

connections (on pins 4 and 7) should always be decoupled

with these capacitors. An optional supply decoupling capaci-

tor across the two power supplies (for bipolar operation) will

improve 2nd-harmonic distortion performance. Larger (2.2µF

to 6.8µF) decoupling capacitors, effective at lower frequen-

cies, should also be used on the main supply pins. These

may be placed somewhat further from the device and may be

shared among several devices in the same area of the PC

board.

and the input impedance of the destination device; this total

effective impedance should be set to match the trace imped-

ance. The high output voltage and current capability of the

OPA692 allows multiple destination devices to be handled as

separate transmission lines, each with their own series and

shunt terminations. If the 6dB attenuation of a doubly-termi-

nated transmission line is unacceptable, a long trace can be

series-terminated at the source end only. Treat the trace as

a capacitive load in this case and set the series resistor value

as shown in the plot of “R_Svs Capacitive Load.” This will not

preserve signal integrity as well as a doubly-terminated line.

If the input impedance of the destination device is low, there

will be some signal attenuation due to the voltage divider

formed by the series output into the terminating impedance.

e) Socketing a high-speed part like the OPA692 is not

recommended. The additional lead length and pin-to-pin

capacitance introduced by the socket can create an ex-

tremely troublesome parasitic network which can make it

almost impossible to achieve a smooth, stable frequency

response. Best results are obtained by soldering the OPA692

onto the board.

c) Careful selection and placement of external compo-

nents will preserve the high-frequency performance of

the OPA692. Any external resistors should be a very low

reactance type. Surface-mount resistors work best and allow

a tighter overall layout. Metal-film and carbon composition,

axially-leaded resistors can also provide good high-frequency

performance. Again, keep their leads and PC-board trace

length as short as possible. Never use wirewound type

resistors in a high-frequency application. All external compo-

nents should also be placed close to the package.

INPUT AND ESD PROTECTION

The OPA692 is built using a very high-speed complementary

bipolar process. The internal junction breakdown voltages

are relatively low for these very small geometry devices.

These breakdowns are reflected in the Absolute Maximum

Ratings table. All device pins have limited ESD protection

using internal diodes to the power supplies, as shown in

Figure 10.

d) Connections to other wideband devices on the board

may be made with short direct traces or through onboard

transmission lines. For short connections, consider the

trace and the input to the next device as a lumped capacitive

load. Relatively wide traces (50mils to 100mils) should be

used, preferably with ground and power planes opened up

around them. Estimate the total capacitive load and set R_S

from the plot of recommended “R_Svs Capacitive Load.” Low

parasitic capacitive loads (< 5pF) may not need an R_S

because the OPA692 is nominally compensated to operate

with a 2pF parasitic load. If a long trace is required, and the

6dB signal loss intrinsic to a doubly-terminated transmission

line is acceptable, implement a matched impedance trans-

mission line using microstrip or stripline techniques (consult

an ECL design handbook for microstrip and stripline layout

techniques). A 50Ω environment is normally not necessary

on board, and in fact, a higher impedance environment will

improve distortion as shown in the “Distortion vs Load” plots.

With a characteristic board trace impedance defined based

on board material and trace dimensions, a matching series

resistor into the trace from the output of the OPA692 is used

as well as a terminating shunt resistor at the input of the

destination device. Remember also that the terminating im-

pedance will be the parallel combination of the shunt resistor

+V_CC

External

Internal

Circuitry

–V_CC

FIGURE 10. Internal ESD Protection.

These diodes provide moderate protection to input overdrive

voltages above the supplies as well. The protection diodes

can typically support 30mA continuous current. Where higher

currents are possible (e.g., in systems with ±15V supply parts

driving into the OPA692), current-limiting series resistors

should be added into the two inputs. Keep these resistor

values as low as possible since high values degrade both

noise performance and frequency response.

OPA692

20

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PACKAGE DRAWINGS

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.020 (0,51)

0.014 (0,35)

0.050 (1,27)

8

0.010 (0,25)

5

0.244 (6,20)

0.228 (5,80)

0.008 (0,20) NOM

0.157 (4,00)

0.150 (3,81)

Gage Plane

1

4

0.010 (0,25)

0°– 8°

A

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

0.069 (1,75) MAX

0.004 (0,10)

PINS **

8

14

16

DIM

A MAX

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

4040047/E 09/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

OPA692

SBOS236C

21

www.ti.com

PACKAGE DRAWINGS (Cont.)

DBV (R-PDSO-G6)

PLASTIC SMALL-OUTLINE

0,50

0,25

M

0,20

0,95

6

6X

4

0,15 NOM

1,70

1,50

3,00

2,60

1

3

Gage Plane

3,00

2,80

0,25

0 –8

0,55

0,35

Seating Plane

0,10

1,45

0,95

0,05 MIN

4073253-5/G 01/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.

OPA692

22

SBOS236C

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

1-Feb-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

OPA692ID

OPA692IDBVR

OPA692IDBVT

OPA692IDR

ACTIVE

SOIC

D

8

6

8

100

3000

250

None

CU NIPDAU Level-3-240C-168 HR

CU NIPDAU Level-3-235C-168 HR

CU NIPDAU Level-3-240C-168 HR

SOT-23

SOIC

DBV

D

2500

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	OPA692ID
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOIC-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
Factory Lead Time：	1 week
风险等级：	1.58
放大器类型：	BUFFER
标称带宽 (3dB)：	280 MHz
最大输入失调电压：	3900 µV
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	2
负供电电压上限：	-6.5 V
标称负供电电压 (Vsup)：	-5 V
功能数量：	1
端子数量：	8
最小输出电流：	10 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TUBE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.75 mm
标称压摆率：	1350 V/us
子类别：	Buffer Amplifier
最大压摆率：	5.1 mA
供电电压上限：	6.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

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