P82B96DR各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

P82B96

DUAL BIDIRECTIONAL BUS BUFFER

www.ti.com

SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

FEATURES

•

Operating Power-Supply Voltage Range

of 2 V to 15 V

Can Interface Between I²C Buses Operating

at Different Logic Levels (2 V to 15 V)

Supports Bidirectional Data Transfer of I²C

Bus Signals

•

400-kHz Fast I²C Bus Operation Over at Least

20 Meters of Wire

•

Low Standby Current Consumption

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

– 3500-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

Allows Bus Capacitance of 400 pF on the

Main I²C Bus (Sx/Sy Side) and 4000 pF on the

Transmission Side (Tx/Ty)

– 1000-V Charged-Device Model (C101)

•

Outputs on the Transmission Side (Tx/Ty)

Have High Sink Capability for Driving

Low-Impedance or High-Capacitive Buses

I²C Bus Signals Can Be Split Into Pairs of

Forward (Tx/Ty) and Reverse (Rx/Ry) Signals

for Interface With Optoelectrical Isolators and

Similar Devices That Need Unidirectional

Input and Output Signal Paths

P PACKAGE

(TOP VIEW)

D PACKAGE

(TOP VIEW)

PW PACKAGE

(TOP VIEW)

DGK PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

V_CC

Sy

Ry

Ty

1

2

3

4

8

7

6

5

Sx

Rx

Sx

Rx

Tx

V_CC

Sy

Ry

Ty

Sx

Rx

Tx

1

2

3

8

7

6

V_CC

Sx

Rx

8

7

1

2

V_CC

Sy

Ry

Ty

Tx

GND

4

5

GND

Ry

Ty

3

4

6

5

Tx

GND

DESCRIPTION/ORDERING INFORMATION

The P82B96 is a bipolar device that supports bidirectional data transfer between the normal I²C bus and a range

of other bus configurations with different voltage and current levels. It can function as the interface without any

limitations on the normal I²C operation and clock speed.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

P82B96P

TOP-SIDE MARKING

PDIP – P

SOIC – D

Tube of 50

P82B96P

Reel of 2000

Tube of 75

P82B96DR

P82B96D

PG96

–40°C to 85°C

Reel of 2000

Tube of 150

Reel of 2500

P82B96PWR

P82B96PW

P82B96DGKR

TSSOP – PW

VSSOP – DGK

PG96

7DS

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

P82B96

DUAL BIDIRECTIONAL BUS BUFFER

www.ti.com

SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devices

and trace lengths) of the new bus or remote I²C nodes are not apparent to other I²C buses (or nodes). This

device also adds minimal loading to I²C node where it is positioned. Any restrictions on the number of I²C

devices in a system, or the physical separation between them, are virtually eliminated.

The P82B96 easily can transmit SDA/SCL signals via balanced transmission lines (twisted pairs) or with

galvanic isolation (optocoupling), because separate directional Tx and Rx signals are provided. The Tx and Rx

signals may be connected directly (without causing bus latching), to provide an alternative bidirectional signal

line with I²C properties.

Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration.

Bidirectional I²C signals do not allow any direction control pin so, instead, slightly different logic low-voltage

levels are used at Sx/Sy to avoid latching of this buffer. A regular I²C low applied at the Rx/Ry of a P82B96 is

propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied

to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a regular I²C bus low and does

not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely

on special logic thresholds for their operation, such as the PCA9515A.

The Sx/Sy side is intended only for, and compatible with, the normal I²C logic voltage levels of I²C master and

slave devices or Tx/Rx signals of a second P82B96, if required. The Tx/Rx and Ty/Ry I/O pins use the standard

I²C logic voltage levels of all I²C parts. If Rx and Tx are connected, Sx can function as either the SDA or SCL

line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no

restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or

multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected

to the line-card slave devices.

TERMINAL FUNCTIONS

NO.

1

NAME

Sx

DESCRIPTION

Serial data bus or SDA. Connect to V_CCof I²C master through a pullup resistor.

Receive signal. Connect to V_CCof P82B96 through a pullup resistor.

Transmit signal. Connect to V_CCof P82B96 through a pullup resistor.

Ground

2

Rx

3

Tx

4

GND

Ty

5

Transmit signal. Connect to V_CCof P82B96 through a pullup resistor.

Receive signal. Connect to V_CCof P82B96 through a pullup resistor.

Serial clock bus or SCL. Connect to V_CCof I²C master through a pullup resistor.

Supply voltage

6

Ry

7

Sy

8

V_CC

2

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P82B96

DUAL BIDIRECTIONAL BUS BUFFER

www.ti.com

SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

FUNCTIONAL BLOCK DIAGRAM

V_CC(2–15 V)

8

3

2

1

7

Sx (SDA)

Tx (TxD, SDA)

Rx (RxD, SDA)

5

6

Ty (TxD, SCL)

Ry (RxD, SCL)

Sy (SCL)

P82B96

4

GND

Functional Description

Sx and Sy

The I²C pins, Sx and Sy, are designed to interface with a normal I²C bus. The logic threshold-voltage levels on

the I²C bus are independent of the supply V_CC. The maximum I²C bus supply voltage is 15 V, and the specified

static sink current is 3 mA.

Sx and Sy have two identical buffers. Each buffer is made up of two logic signal paths. The first one, named Tx

or Ty, is a forward path from the I²C interface pin, which drives the buffered bus. The second one, named Rx or

Ry, is a reverse signal path from the buffered bus input to drive the I²C bus interface.

There are two purposes for these paths: to sense the voltage state of the I²C pin (Sx or Sy) and transmit this

state to Tx or Ty, respectively, and to detect the state of the Rx or Ry and pull the I²C pin low when Rx or Ry is

low.

Tx and Ty

Tx and Ty are open-collector outputs without ESD protection diodes to V_CC. Each pin may be connected via a

pullup resistor to a supply voltage in excess of V_CC, as long as the 15-V rating is not exceeded. Tx and Ty have

a larger current-sinking capability than a normal I²C device and can sink a static current of greater than 30 mA.

They also have dynamic pulldown capability of 100-mA, typically.

A logic low is transmitted to Tx or Ty only when the voltage at the I²C pin (Sx or Sy) is below 0.6 V. A logic low

at Rx or Ry causes the I²C bus (Sx or Sy) to be pulled to a logic low level in accordance with I²C requirements

(maximum 1.5 V in 5-V applications), but not low enough to be looped back to the Tx or Ty output and cause the

buffer to latch low.

The minimum low level that the P82B96 can achieve on the I²C bus by a low at Rx or Ry typically is 0.8 V.

If V_CCfails, neither the I²C pins nor the Tx or Ty outputs are held low. Their open-collector configuration allows

them to be pulled up to the rated maximum of 15 V without V_CCpresent. The input configuration on Sx, Sy, Rx,

and Ry also presents no loading of external signals when V_CCis not present.

The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 4 pF for

all bus voltages and supply voltages, including V_CC= 0 V.

3

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P82B96

DUAL BIDIRECTIONAL BUS BUFFER

www.ti.com

SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

MAX UNIT

V_CC

V_I

Supply voltage range

18

V

Sx or Sy (SDA or SCL)

Rx or Ry

Voltage range on buffered input

V

18

Sx or Sy (SDA or SCL)

Tx or Ty

18

V_O

Voltage range on buffered output

V

18

Sx or Sy

250

97

I_O

Continuous output current

mA

Tx or Ty

I_CC

Continuous current through V_CCor GND

D package

P package

85

θ_JA

Package thermal impedance⁽²⁾

°C/W

PW package

DGK package

149

172

125

85

T_stg

T_A

Storage temperature range

–55

–40

°C

Operating free-air temperature range

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions

MIN

MAX UNIT

V_CC

I_OL

Supply voltage

2

15

3

V

Sx, Sy

Tx, Ty

Sx, Sy

Tx, Ty

Sx, Sy

V_Sx, V_Sy= 1 V, V_Rx, V_Ry≤ 0.42 V

V_Sx, V_Sy= 0.4 V, V_Tx, V_Ty= 0.4 V

V_Tx, V_Ty= 0.4 V

Low-level output current

mA

30

15

0.4

85

V_IOmax

Maximum input/output voltage level

V

V_Sx, V_Sy= 0.4 V

V_ILdiff

T_A

Low-level input voltage difference

Operating free-air temperature

V

–40

°C

4

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P82B96

DUAL BIDIRECTIONAL BUS BUFFER

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SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

Electrical Characteristics

V_CC= 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted)

T_A= 25°C

TYP⁽¹⁾

T_A= –40°C to 85°C

TEST

CONDITIONS

PARAMETER

UNIT

mV/°C

V

MIN

MAX

MIN

MAX

Temperature coefficient of

input thresholds

∆V/∆T_IN

Sx, Sy

–2

(2)

I_Sx, I_Sy= 3 mA

0.8

0.88

0.73

1

V_OL

Low-level output voltage

I_Sx, I_Sy= 0.2 mA

0.67

0.79

Temperature coefficient of

output low levels⁽³⁾

∆V/∆T_OUT

I_CC

I_Sx, I_Sy= 0.2 mA

Sx = Sy = V_CC

–1.8

0.9

mV/°C

mA

Quiescent supply current

1.8

2

3

Additional supply current

per pin low

∆I_CC

Tx, Ty

Sx, Sy

1.7

2.75

mA

Dynamic output sink

capability on I²C bus

V_Sx, V_Sy> 2 V,

V_Rx, V_Ry= low

7

18

5.5

60

mA

I_IOS

V_Sx, V_Sy= 2.5 V,

V_Rx, V_Ry= high

Leakage current on I²C bus

0.1

1

µA

V_Tx, V_Ty> 1 V,

V_Sx, V_Sy= low on

I²C bus = 0.4 V

Dynamic output sink

capability on buffered bus

Tx, Ty

60

100

0.1

mA

I_IOT

V_Tx, V_Ty= V_CC

2.5 V,

V_Sx, V_Sy= high

=

Leakage current

on buffered bus

1

µA

Bus low, V_Rx

V_Ry= high

,

Input current from I²C bus

Sx, Sy

Rx, Ry

–1

1

Input current

from buffered bus

Bus low, V_Rx

V_Ry= 0.4 V

,

I_I

µA

Leakage current

on buffered bus input

V_Rx, V_Ry= V_CC

1.5

Input logic level high

threshold⁽⁴⁾

(2)

0.65

0.7

on normal I²C bus

Sx, Sy

Input logic level low

threshold⁽⁴⁾

0.6

V_IT

Input threshold

V

on normal I²C bus

Input logic level high 0.58 V_CC

0.58 V_CC

Rx, Ry Input threshold

Input logic level low

(V_Sxoutput low

0.5 V_CC

0.42 V_CC

Input/output logic level

difference⁽⁵⁾

at 3 mA) –

V_IOdiff

Sx, Sy

100

1

150

100

1

mV

V

(V_Sxinput high max)

for I²C applications

Sx, Sy are low, V_CC

V_CCvoltage at which all

buses are released

Sx, Sy

Tx, Ty

ramping, voltage on

Tx, Ty lowered until

released

V_IOrel

Temperature coefficient of release

voltage

∆V/∆T_REL

–4

mV/°C

C_in

Input capacitance

Rx, Ry

2.5

4

pF

(1) Typical value is at V_CC= 2.5 V, T_A= 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The input logic threshold is independent of the supply voltage.

(5) The minimum value requirement for pullup current, 200 µA, ensures that the minimum value for V_SXoutput low always exceeds the

minimum V_Sxinput high level to eliminate any possibility of latching. The specified difference is specified by design within any device.

While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices should never be linked,

because the resulting system would be very susceptible to induced noise and would not support all I²C operating modes.

5

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P82B96

DUAL BIDIRECTIONAL BUS BUFFER

www.ti.com

SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

Electrical Characteristics

V_CC= 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

UNIT

mV/°C

V

MIN

TYP⁽¹⁾

MAX

MIN

MAX

Temperature

coefficient of

input thresholds

∆V/∆T_IN

Sx, Sy

–2

(2)

I_Sx, I_Sy= 3 mA

0.8

0.88

0.73

1

Low-level output

voltage

V_OL

I_Sx, I_Sy= 0.2 mA

0.67

0.79

Temperature

coefficient of

output low

levels⁽³⁾

∆V/∆T_OUT

Sx, Sy

I_Sx, I_Sy= 0.2 mA

Sx = Sy = V_CC

–1.8

mV/°C

I_CC

Quiescent supply current

Additional supply

current per pin

low

0.9

1.7

1.8

2

3

mA

∆I_CC

Tx, Ty

2.75

Dynamic output

sink capability

on I²C bus

V_Sx, V_Sy> 2 V,

V_Rx, V_Ry= low

7

18

0.1

5.7

60

mA

µA

I_IOS

Sx, Sy

Leakage current

on I²C bus

V_Sx, V_Sy= 5 V,

V_Rx, V_Ry= high

1

Dynamic output

sink capability

on buffered bus

V_Tx, V_Ty> 1 V,

V_Sx, V_Sy= low on I²C

bus = 0.4 V

60

100

mA

µA

I_IOT

Tx, Ty

Sx, Sy

Rx, Ry

Leakage current

on buffered bus

V_Tx, V_Ty= V_CC

3.3 V, V_Sx, V_Sy= high

=

0.1

–1

1

Input current

from I²C bus

Bus low, V_Rx

V_Ry= high

,

Input current

from buffered bus

Bus low, V_Rx

V_Ry= 0.4 V

I_I

µA

Leakage current

on buffered bus

input

V_Rx, V_Ry= V_CC

1

0.65

1.5

Input logic-level high

threshold⁽⁴⁾

(2)

0.7

on normal I²C bus

Sx, Sy

Input logic-level low

threshold⁽⁴⁾

(2)

0.6

V_IT

Input threshold

V

on normal I²C bus

Input logic level high

0.58 V_CC

Rx, Ry Input threshold

Input logic level low

(V_Sxoutput low

0.5 V_CC

0.42 V_CC

Input/output logic

level difference⁽⁵⁾

at 3 mA) –

V_IOdiff

Sx, Sy

100

1

150

100

1

mV

V

(V_Sxinput high max)

for I²C applications

Sx, Sy are low, V_CC

V_CCvoltage at

which all buses

are released

Sx, Sy

Tx, Ty

ramping, voltage on

Tx, Ty lowered until

released

V_IOrel

(1) Typical value is at V_CC= 3.3 V, T_A= 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The input logic threshold is independent of the supply voltage.

(5) The minimum value requirement for pullup current, 200 µA, ensures that the minimum value for V_SXoutput low always exceeds the

minimum V_Sxinput high level to eliminate any possibility of latching. The specified difference is specified by design within any device.

While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,

because the resulting system would be very susceptible to induced noise and would not support all I²C operating modes.

6

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P82B96

DUAL BIDIRECTIONAL BUS BUFFER

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SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

Electrical Characteristics (continued)

V_CC= 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 85°C

MIN MAX

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP⁽¹⁾

MAX

Temperature coefficient of

release voltage

∆V/∆T_REL

–4

mV/°C

C_in

Input capacitance Rx, Ry

2.5

4

pF

7

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P82B96

DUAL BIDIRECTIONAL BUS BUFFER

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SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

Electrical Characteristics

V_CC= 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP⁽¹⁾

MAX

MIN

MAX

Temperature

coefficient of

input thresholds

∆V/∆T_IN

Sx, Sy

–2

mV/°C

(2)

I_Sx, I_Sy= 3 mA

0.8

0.88

0.73

1

Low-level output

voltage

V_OL

V

I_Sx, I_Sy= 0.2 mA

0.67

0.79

Temperature

coefficient of

output low

levels⁽³⁾

∆V/∆T_OUT

Sx, Sy

I_Sx, I_Sy= 0.2 mA

Sx = Sy = V_CC

–1.8

mV/°C

I_CC

Quiescent supply current

Additional supply

current

0.9

1.7

1.8

2

3

mA

∆I_CC

Tx, Ty

2.75

per pin low

Dynamic output

sink capability

on I²C bus

V_Sx, V_Sy> 2 V,

V_Rx, V_Ry= low

7

18

0.1

6

mA

µA

I_IOS

Sx, Sy

Leakage current

on I²C bus

V_Sx, V_Sy= 5 V,

V_Rx, V_Ry= high

1

Dynamic output

sink capability

on buffered bus

V_Tx, V_Ty> 1 V,

V_Sx, V_Sy= low on

I²C bus = 0.4 V

60

100

60

mA

µA

I_IOT

Tx, Ty

Sx, Sy

Rx, Ry

Leakage current

on buffered bus

V_Tx, V_Ty= V_CC

5 V, V_Sx, V_Sy= high

=

0.1

–1

1

Input current

from I²C bus

Bus low, V_Rx

V_Ry= high

,

Input current

from buffered bus

Bus low, V_Rx

V_Ry= 0.4 V

I_I

µA

Leakage current

on buffered bus

input

V_Rx, V_Ry= V_CC

1

0.65

1.5

Input logic-level high

threshold⁽⁴⁾

(2)

0.7

on normal I²C bus

Sx, Sy

Input logic-level low

threshold⁽⁴⁾

(2)

0.6

V_IT

Input threshold

V

on normal I²C bus

Input logic level high

Input threshold

0.58 V_CC

Rx, Ry

Sx, Sy

0.5 V_CC

Input logic level low

0.42 V_CC

(V_Sxoutput low at

3 mA) –

Input/output logic

level difference⁽⁵⁾

V_IOdiff

100

1

150

100

1

mV

V

(V_Sxinput high max)

for I²C applications

Sx, Sy are low, V_CC

ramping, voltage on

Tx, Ty lowered until

released

V_CCvoltage at

which all buses

are released

Sx, Sy

Tx, Ty

V_IOrel

(1) Typical value is at V_CC= 5 V, T_A= 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The input logic threshold is independent of the supply voltage.

(5) The minimum value requirement for pullup current, 200 µA, ensures that the minimum value for V_SXoutput low always exceeds the

minimum V_Sxinput high level to eliminate any possibility of latching. The specified difference is specified by design within any device.

While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,

because the resulting system would be very susceptible to induced noise and would not support all I²C operating modes.

8

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P82B96

DUAL BIDIRECTIONAL BUS BUFFER

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SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

Electrical Characteristics (continued)

V_CC= 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 85°C

MIN MAX

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP⁽¹⁾

MAX

Temperature coefficient of

release voltage

∆V/∆T_REL

–4

mV/°C

C_in

Input capacitance Rx, Ry

2.5

4

pF

9

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DUAL BIDIRECTIONAL BUS BUFFER

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SCPS144A–MAY 2006–REVISED SEPTEMBER 2006

Electrical Characteristics

V_CC= 15 V, voltages are specified with respect to GND (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP⁽¹⁾

MAX

MIN

MAX

Temperature

coefficient of

input thresholds

∆V/∆T_IN

Sx, Sy

–2

mV/°C

(2)

I_Sx, I_Sy= 3 mA

0.8

0.88

0.73

1

Low-level output

voltage

V_OL

V

I_Sx, I_Sy= 0.2 mA

0.67

0.79

Temperature

coefficient of

output low

levels⁽³⁾

∆V/∆T_OUT

Sx, Sy

I_Sx, I_Sy= 0.2 mA

Sx = Sy = V_CC

–1.8

mV/°C

Quiescent supply

current

I_CC

0.9

1.7

1.8

2

3

mA

Additional supply

current

per pin low

∆I_CC

Tx, Ty

Sx, Sy

2.75

Dynamic output

sink capability

on I²C bus

V_Sx, V_Sy> 2 V,

V_Rx, V_Ry= low

7

18

0.1

6.5

60

mA

µA

I_IOS

Leakage current

on I²C bus

V_Sx, V_Sy= 15 V,

V_Rx, V_Ry= high

1

Dynamic output

sink capability

on buffered bus

V_Tx, V_Ty> 1 V,

V_Sx, V_Sy= low on

I²C bus = 0.4 V

60

100

mA

I_IOT

Tx, Ty

V_Tx, V_Ty= V_CC

15 V,

=

Leakage current

on buffered bus

0.1

µA

V_Sx, V_Sy= high

Input current

from I²C bus

Bus low, V_Rx

V_Ry= high

,

Sx, Sy

Rx, Ry

–1

1

Input current

from buffered bus

Bus low, V_Rx

V_Ry= 0.4 V

,

I_I

Leakage current

on buffered bus

input

V_Rx, V_Ry= V_CC

1

0.65

1.5

Input logic-level high

threshold⁽⁴⁾

(2)

0.7

on normal I²C bus

Sx, Sy

Input logic-level high

threshold⁽⁴⁾

(2)

0.6

V_IT

Input threshold

V

on normal I²C bus

Input logic level high

Input threshold

0.58 V_CC

Rx, Ry

Sx, Sy

0.5 V_CC

Input logic level low

0.42 V_CC

(V_Sxoutput low at

3 mA) –

Input/output logic

level difference⁽⁵⁾

V_IOdiff

100

150

100

mV

(V_Sxinput high max)

for I²C applications

(1) Typical value is at V_CC= 15 V, T_A= 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The input logic threshold is independent of the supply voltage.

(5) The minimum value requirement for pullup current, 200 µA, ensures that the minimum value for V_SXoutput low always exceeds the

minimum V_Sxinput high level to eliminate any possibility of latching. The specified difference is specified by design within any device.

While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,

because the resulting system would be very susceptible to induced noise and would not support all I²C operating modes.

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Electrical Characteristics (continued)

V_CC= 15 V, voltages are specified with respect to GND (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP⁽¹⁾

MAX

MIN

MAX

Sx, Sy are low, V_CC

ramping, voltage on

Tx, Ty lowered until

released

V_CCvoltage at

which all buses

are released

Sx, Sy

Tx, Ty

V_IOrel

1

V

Temperature coefficient of

release voltage

∆V/∆T_REL

–4

mV/°C

C_in

Input capacitance Rx, Ry

2.5

4

pF

Switching Characteristics

V_CC= 5 V, T_A= 25°C, no capacitive loads, voltages are specified with respect to GND (unless otherwise noted)

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

TEST CONDITIONS

TYP UNIT

R_Txpullup = 160 Ω,

C_Tx= 7 pF + board

trace capacitance

Buffer delay time on falling

input⁽¹⁾

V_Sx(or V_Sy) = input switching

threshold

V_Tx(or V_Ty) output falling

50% of V_LOAD

t_pzl

t_plz

t_pzl

t_plz

70 ns

R_Txpullup = 160 Ω,

C_Tx= 7 pF + board

trace capacitance

Buffer delay time on rising

input⁽²⁾

V_Sx(or V_Sy) = input switching

threshold

V_Tx(or V_Ty) output

reaching 50% of V_LOAD

90 ns

250 ns

270 ns

R_Sxpullup = 1500 Ω,

C_Tx= 7 pF + board

trace capacitance

Buffer delay time on falling

input⁽³⁾

V_Rx(or V_Ry) = input switching

threshold

V_Sx(or V_Sy) output falling

50% of V_LOAD

R_Sxpullup = 1500 Ω,

C_Tx= 7 pF + board

trace capacitance

Buffer delay time on rising

input⁽⁴⁾

V_Rx(or V_Ry) = input switching

threshold

V_Sx(or V_Sy) output

reaching 50% of V_LOAD

(1) The fall time of V_Txfrom 5 V to 2.5 V in the test is approximately 15 ns.

(2) The fall time of V_Sxfrom 5 V to 2.5 V in the test is approximately 50 ns.

(3) The rise time of V_Txfrom 0 V to 2.5 V in the test is approximately 20 ns.

(4) The rise time of V_Sxfrom 0.9 V to 2.5 V in the test is approximately 70 ns.

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TYPICAL CHARACTERISTICS

V_OLAT Sx

vs

JUNCTION TEMPERATURE

I_OL= 0.2 mA

V_OLAT Sx

vs

JUNCTION TEMPERATURE

I_OL= 3 mA

1000

800

1200

1000

800

Maximum

Typical

Maximum

Typical

600

400

Minimum

600

Minimum

400

-50 –25

0

25 50 75 100 125

T_j– °C

-50 –25

0

25 50 75 100 125

T_j– °C

V_IL(max)AT Sx

vs

JUNCTION TEMPERATURE

V_IH(min)AT Sx

vs

JUNCTION TEMPERATURE

1000

800

1000

800

600

400

200

600

400

200

-50 –25

0

25 50 75 100 125

T_j– °C

-50 –25

0

25 50 75 100 125

T_j– °C

V_CC(max)

vs

JUNCTION TEMPERATURE

1400

1200

1000

800

600

400

-50 –25

0

25 50 75 100 125

T_j– °C

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PARAMETER MEASUREMENT INFORMATION

V

CC

V

CC

V

IN

V

OUT

S1

R_L= 160 to 1500 W

PULSE

GENERATOR

DUT

GND

C_L= Probe and jig capacitance

(see Note A)

R_T

TEST

S1

t /t

PLZ PZL

V

CC

TEST CIRCUIT FOR OPEN-DRAIN OUTPUT

V_CC

0.6 V

0 V

Sx or Sy

t_PZL

t_PLZ

V_CC

0.5 ´ V_CC

Tx or Ty

V_OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

Figure 1. Test Circuit and Voltage Waveforms

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APPLICATION INFORMATION

Typical Applications

Figure 2 through Figure 4 show typical applications for the P82B96.

V_CC(2–15V)

5 V

R1

Tx

(SDA)

I²C

SDA

(New Levels)

Rx

(SDA)

1/2 PB2B96

Figure 2. Interfacing I²C Bus With Different Logic Levels

V_CC1

V_CC

R4

R2

R5

R3

I²C

SDA

5 V

R1

Rx

(SDA)

I²C

SDA

Tx

(SDA)

1/2 P82B96

Figure 3. Galvanic Isolation of I²C Nodes

Main Enclosure

12 V

Remote-Control Enclosure

12 V

3.3–5 V

Long Cables

SCL

3.3–5 V

SCL

3.3–5 V

12 V

SDA

P82B96

Figure 4. Long-Distance I²C Communications

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APPLICATION INFORMATION (continued)

Figure 5 shows how a master I²C bus can be protected against short circuits or failures in applications that

involve plug/socket connections and long cables that may become damaged. A simple circuit is added to

monitor the SDA bus and, if its low time exceeds the design value, disconnect the master bus. P82B96 frees all

of its I/Os if its supply is removed, so one option is to connect its V_CCto the output of a logic gate from, for

example, the LVC family. The SDA and SCL lines could be timed, and V_CCdisabled via the gate, if a line

exceeds a design value of the low period. If the supply voltage of logic gates restricts the choice of V_CCsupply,

the low-cost discrete circuit in Figure 5 can be used. If the SDA line is held low, the 100-nF capacitor charges,

and Ry is pulled toward V_CC. When it exceeds V_CC/2, Ry sets Sy high, which effectively releases it.

V

+V Cable Drive

V_CC1

+V Cable Drive

V_CC

V_CC2

V_CC

BC

847B

Rx

Tx

Rx

Tx

3-m to 20-m Cables

Sx

Sy

Sx

SCL

I²C/DDC

Slave

I²C/DDC

Master

Ty

I²C/DDC

Ty

4700 Ω

Ry

SDA

Sy

470 kΩ

BC

847B

P82B96

470 kΩ

GND

Monitor/Flat TV

GND

PC/TV Receiver/Decoder Box

R

G

B

Video Signals

Figure 5. Extending DCC Bus

In this example, the SCL line is made unidirectional by tying Rx to V_CC. The state of the buffered SCL line

cannot affect the master clock line, which is allowed when clock stretching is not required. It is simple to add an

additional transistor or diode to control the Rx input in the same way as Ry, when necessary. The +V cable drive

can be any voltage up to 15 V, and the bus may be run at a lower impedance by selecting pullup resistors for a

static sink current up to 30 mA. V_CC1and V_CC2may be chosen to suit the connected devices. Because DDC

uses relatively low speeds (<100 kHz), the cable length is not restricted to 20 m by the I²C signaling, but it may

be limited by the video signaling.

Figure 6 and Table 1 show that P82B96 can achieve high clock rates over long cables. While calculating with

lumped wiring capacitance yields reasonable approximations to actual timing; even 25 m of cable is better

treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer

edge, have a characteristic impedance in the range 100–200 Ω. For simplicity, they cannot be terminated in their

characteristic impedance, but a practical compromise is to use the minimum pullup allowed for P82B96 and

place half this termination at each end of the cable. When each pullup is below 330 Ω, the rising-edge

waveforms have their first voltage step level above the logic threshold at Rx, and cable timing calculations can

be based on the fast rise/fall times of resistive loading, plus simple one-way propagation delays. When the

pullup is larger, but below 750 Ω, the threshold at Rx is crossed after one signal reflection. So, at the sending

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APPLICATION INFORMATION (continued)

end, it is crossed after two times the one-way propagation delay and, at the receiving end, after three times that

propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way

propagation delays are about 5 ns/m. The 10% to 90% rise and fall times on the cable are between 20 ns and

50 ns, so their delay contributions are small. There is ringing on falling edges that can be damped, if required,

using Schottky diodes, as shown.

+V Cable Drive

V_CC1

R2

V_CC2

R2

V_CC

R1

Rx

Tx

Rx

Tx

Sx

SCL

SDA

SCL

SDA

C2

I²C

SLAVE(S)

Ty

I²C

MASTER

Sy

Ry

Cable

P82B96

Propagation

Delay = 5 ns/m

C2

GND

BAT54A

Figure 6. Driving Ribbon or Flat Telephone Cables

Table 1. Bus Capabilities

MASTER SCL

BUS

CLOCK

SPEED RESPONSE

MAXIMUM

SLAVE

PULSE

DURATION

(ns)

+V

CABLE

(V)

CABLE

LENGTH

(m)

CABLE

DELAY

(ns)

V_CC1

(V)

V_CC2

(V)

R1

(Ω)

R2

(kΩ)

C2

(pF)

CABLE

CAPACITANCE

(kHz)

DELAY

HIGH

LOW

(1)

(2)

5

12

5

750

330

2.2

1

400

220

100

250

100

25

1250

500

125

15

600

4000

2600

1500

1000

120

185

390

500

5

3.3

1 nF

5

1

3

120 pF

600 ns

(1) Not applicable; calculations are delay based.

(2) Normal 400-kHz bus specification

When the master SCL high and low periods can be programmed separately, the timings can allow for bus

delays. The low period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave

response data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of the

falling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master.

Because the buffer stretches the programmed SCL low period, the actual SCL frequency is lower than

calculated from the programmed clock periods. In the example for the 25-m cable in Table 1, the clock is

stretched 400 ns, the falling edge of SCL is delayed 490 ns, and the SDA rising edge is delayed 570 ns. The

required additional low period is (490 + 570) = 1060 ns and the I²C bus specifications already include an

allowance for a worst-case bus rise time (0% to 70%) of 425 ns. The bus rise time can be 300 ns (30% to 70%),

which means it can be 425 ns (0% to 70%). The 25-m cable delay times include all rise and fall times.

Therefore, the device only needs to be programmed with an additional (1060 – 400 – 425) = 235 ns, making a

total programmed low period 1535 ns. The programmed low is stretched by 400 ns to yield an actual bus low

time of 1935 ns, which, allowing the minimum high period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.

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Note that, in both the 100-m and 250-m examples, the capacitive loading on the I²C buses at each end is within

the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of

a hybrid mode, because it relies on the response delays of Fast mode parts, but uses (allowable) Standard

mode bus loadings with rise times that contribute significantly to the system delays. The cables cause large

propagation delays. Therefore, these systems must operate well below the 400-kHz limit, but illustrate how they

still can exceed the 100-kHz limit, provided all parts are capable of Fast mode operation. The fastest example

illustrates how the 400-kHz limit can be exceeded, provided master and slave parts have delay specifications

smaller than the maximum allowed. Many TI slaves have delays shorter than 600 ns, but none have that

specified.

Calculating System Delays and Bus-Clock Frequency for Fast Mode System

Figure 7 through Figure 9 show the P82B96 used to drive extended bus wiring, with relatively large capacitance,

linking two Fast mode I²C bus nodes. It includes simplified expressions for making the relevant timing

calculations for 3.3-/5-V operation. Because the buffers and the wiring introduce timing delays, it may be

necessary to decrease the nominal SCL frequency below 400 kHz. In most cases, the actual bus frequency is

lower than the nominal master timing, due to bit-wise stretching of the clock periods.

Buffered Expansion Bus

Local Master Bus

Remote Slave Bus

V

CCB

V_CCM

V_CCS

Rm

Rb

Rs

SCL

SLAVE

MASTER

Sx

Tx/Rx

Sx

P82B96

I²C

Cm = Master Bus

Capacitance

Cb = Buffered Bus

Wiring Capacitance

Cs = Slave Bus

Capacitance

GND

Falling edge of SCL at master is delayed by the buffers and bus fall times.

Effective Delay of SCL at Slave = 255 + 17 V_CCM+ (2.5 + 4 × 10⁹Cb) V_CCB(ns)

C = F, V = Volts

Figure 7.

Buffered Expansion Bus

Local Master Bus

V_CCB

V_CCM

Rb

Rm

SCL

MASTER

Sx

Tx/Rx

P82B96

I²C

Cm = Master Bus

Capacitance

Cb = Buffered Bus

Wiring Capacitance

GND

Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times.

Effective delay of SCL at master = 270 + RmCm + 0.7RbCb (ns)

C = F, R = Ω

Figure 8.

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Buffered Expansion Bus

Local Master Bus

Remote Slave Bus

V_CCM

V_CCS

V_CCB

SDA

Rm

Rs

Rb

SLAVE

MASTER

Tx/Rx

Sx

P82B96

I²C

Cm = Master Bus

Capacitance

Cb = Buffered Bus

Wiring Capacitance

Cs = Slave Bus

Capacitance

GND

Rising edge of SDA at slave is delayed by the buffers and bus rise times.

Effective delay of SDA at master = 270 + 0.2RsCs + 0.7(RbCb + RmCm) (ns)

C = F, R = Ω

Figure 9.

The delay factors involved in calculation of the allowed bus speed are:

1. The propagation delay of the master signal through the buffers and wiring to the slave. The important delay

is that of the falling edge of SCL, because this edge requests the data or ACK from a slave.

2. The effective stretching of the nominal low period of SCL at the master, caused by the buffer and bus rise

times.

3. The propagation delay of the slave response signal through the buffers and wiring back to the master. The

important delay is that of a rising edge in the SDA signal. Rising edges always are slower and, therefore, are

delayed by a longer time than falling edges. (The rising edges are limited by the passive pullup, while falling

edges actively are driven.)

The timing requirement in any I²C system is that a slave’s data response (which is provided in response to a

falling edge of SCL) must be received at the master before the end of the corresponding low period of SCL as it

appears on the bus wiring at the master. Because all slaves, as a minimum, satisfy the worst-case timing

requirements of a 400-kHz part, they must provide their response within the minimum allowed clock low period

of 1300 ns. Therefore, in systems that introduce additional delays, it is necessary only to extend that minimum

clock low period by any effective delay of the slave response. The effective delay of the slave's response equals

the total delays in SCL falling edge from the master reaching the slave (A) minus the effective delay (stretch) of

the SCL rising edge (B) plus total delays in the slave response data, carried on SDA, and reaching the master

(C).

The master microcontroller should be programmed to produce

a

nominal SCL low period

of (1300 + A – B + C) ns and should be programmed to produce the nominal minimum SCL high period of

600 ns. Then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If

found to be necessary, increase either clock period.

Due to clock stretching, the SCL cycle time always is longer than (600 + 1300 + A + C) ns.

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Sample Calculations

The master bus has an RmCm product of 100 ns and V_CCM= 5 V.

The buffered bus has a capacitance of 1 nF and a pullup resistor of 160 Ω to 5 V, giving an RbCb product of

160 ns. The slave bus also has an RsCs product of 100 ns.

The master low period should be programmed to be ≥(1300 + 372.5 – 482 + 472) ns, which calculates to

≥1662.5 ns.

The master high period may be programmed to the minimum 600 ns. The nominal master clock period is

≥(1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz.

The

actual

bus-clock

period,

including

the

482-ns

clock

stretch

effect,

is

below

(nominal + stretch) = (2262.5 + 482) ns or ≥2745 ns, equivalent to an allowable frequency of 364 kHz.

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device

P82B96D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

P82B96DG4

P82B96DGKR

P82B96DGKRG4

P82B96DR

SOIC

MSOP

SOIC

D

DGK

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

P82B96DRG4

P82B96P

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PDIP

P

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

P82B96PE4

PDIP

P

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

P82B96PW

TSSOP

PW

150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

P82B96PWG4

P82B96PWR

P82B96PWRG4

150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

M

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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型号:	P82B96DR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	0.69
差分输出：	NO
驱动器位数：	2
输入特性：	STANDARD
接口集成电路类型：	LINE TRANSCEIVER
接口标准：	GENERAL PURPOSE
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	2
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	2/15 V
认证状态：	Not Qualified
最大接收延迟：
接收器位数：	2
座面最大高度：	1.75 mm
子类别：	Other Interface ICs
最大压摆率：	2 mA
最大供电电压：	15 V
最小供电电压：	2 V
标称供电电压：	5 V
电源电压1-最大：	15 V
电源电压1-分钟：	2 V
电源电压1-Nom：	2.5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
Base Number Matches：	1

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