PC82573L各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

82573 Family of GbE Controllers

Datasheet

Product Features

PCIe*

— x1 PCIe* interface on ICH7 or MCH devices

Manageability

— Intel® Active Management Technology (Intel®

AMT) support (82573E only)

— Peak bandwidth: 2 Gb/s per direction

— Power management

— High bandwidth density per pin

— Alerting Standards Format 2.0 and advanced

pass through support (82573E/V only)

— Boot ROM Preboot eXecution Environment

(PXE) Flash interface support

MAC

— Optimized transmit and receive queues

— IEEE 802.3x compliant flow control with

software controlled pause times and threshold

values

— Compliance with PCI Power Management 1.1

and Advanced Configuration and Power

Interface (ACPI) 2.0 register set compliant

— Wake on LAN support

— Caches up to 64 packet descriptors per queue

— Programmable host memory receive buffers

(256 bytes to 16 KB) and cache line size (16

bytes to 256 bytes)

Additional

— Three activity and link indication outputs that

directly drive LEDs

— Programmable LEDs

— 32 KB configurable transmit and receive FIFO

— Internal PLL for clock generation that can use

buffer

a 25 MHz crystal

— Mechanism available for reducing interrupts

generated by transmit and receive operation

— Descriptor ring management hardware for

transmit and receive

— Power saving feature for the 82573L. During

the L1 and L2 link states, the 82573L asserts

the Clock Request signal (CLKREQ#) to

indicate that its PCIe* reference clock can be

gated

— Optimized descriptor fetching and write-back

mechanisms

— On-chip power control circuitry

— Loopback capabilities

— Wide, pipelined internal data path architecture

PHY

— JTAG (IEEE 1149.1) Test Access Port (TAP)

— Integrated PHY for 10/100/1000 Mb/s full and

built in silicon

half duplex operation

Technology

— IEEE 802.3ab auto negotiation support

— IEEE 802.3ab PHY compliance and

compatibility

— Lead-free 196-pin Thin and Fine Pitch Ball Grid

Array (TF-BGA) package

— Operating temperature: 0° C to 70° C (with

external regulators)

— DSP architecture implements digital

adaptive equalization, echo cancellation,

and cross-talk cancellation

— Operating temperature: 0° to 55° C (with on-

die 2.5V regulator)

— Storage temperature -40° C to 125° C

Host Offloading

— Transmit and receive IP, TCP and UDP

checksum off-loading capabilities

— Transmit TCP segmentation, IPv6 offloading,

and advanced packet filtering

— IEEE 802.1q VLAN support with VLAN tag

insertion, stripping and packet filtering for up

to 4096 VLAN tags

— Descriptor ring management hardware for

transmit and receive

Order Number: 315514-002

Revision 2.5

Legal Lines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel

or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

IMPORTANT - PLEASE READ BEFORE INSTALLING OR USING INTEL® PRE-RELEASE PRODUCTS.

Please review the terms at http://www.intel.com/netcomms/prerelease_terms.htm carefully before using any Intel® pre-release product, including any

evaluation, development or reference hardware and/or software product (collectively, “Pre-Release Product”). By using the Pre-Release Product, you

indicate your acceptance of these terms, which constitute the agreement (the “Agreement”) between you and Intel Corporation (“Intel”). In the event

that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different

processor families. See http://www.intel.com/products/processor_number for details.

This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not

finalize a design with this information.

The 82573 GbE Controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available on request.

®

Hyper-Threading Technology requires a computer system with an Intel Pentium 4 processor supporting HT Technology and a HT Technology enabled

chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/

products/ht/Hyperthreading_more.htm for additional information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet—82573

Contents

1.0 Introduction..............................................................................................................7

1.1

1.2

1.3

1.4

Document Scope.................................................................................................8

Reference Documents..........................................................................................8

82573 Architecture .............................................................................................9

Product Codes for the 82573............................................................................... 10

2.0 Signal Descriptions.................................................................................................. 10

2.1

2.2

2.3

2.4

2.5

Signal Type Definitions....................................................................................... 10

PCIe* Data Signals............................................................................................ 11

PCIe* Miscellaneous Signals ............................................................................... 11

Non-Volatile Memory Interface Signals................................................................. 12

Miscellaneous Signals ........................................................................................ 12

2.5.1 Reset and Power-down Signals................................................................. 12

2.5.2 System Management Bus (SMBus) Signals................................................. 13

2.5.3 LED Signals........................................................................................... 13

2.5.4 Other Signals......................................................................................... 13

PHY Analog and Crystal Signals........................................................................... 14

Test Signals...................................................................................................... 15

2.7.1 MAC Test Signals.................................................................................... 15

2.7.2 PHY Test Signals .................................................................................... 15

2.7.3 Other Test Signals.................................................................................. 15

Power Signals................................................................................................... 16

2.8.1 Power Support Signals ............................................................................ 16

2.8.2 Digital and Analog Power Supply Signals ................................................... 16

Grounds and No Connects .................................................................................. 16

2.6

2.7

2.8

2.9

3.0 Voltage, Temperature, and Timing Specifications .................................................... 17

3.1

3.2

3.3

Absolute Maximum Ratings................................................................................. 17

Recommended Operating Conditions.................................................................... 17

Power Supply Connections.................................................................................. 17

3.3.1 External LVR Power Delivery.................................................................... 18

3.3.2 Power Sequencing with External Regulators ............................................... 19

3.3.3 Internally Generated Power Delivery......................................................... 20

3.3.4 Internal LVR Power Sequencing................................................................ 21

DC and AC Specifications.................................................................................... 25

External Interfaces............................................................................................ 28

3.5.1 Crystal.................................................................................................. 28

3.5.2 External Clock Oscillator ......................................................................... 28

3.5.3 Non-Volatile Memory (NVM) Interface: EEPROM ......................................... 29

3.4

3.5

4.0 Package and Pinout Information ............................................................................. 30

4.1

4.2

4.3

Package Information.......................................................................................... 30

Thermal Specifications ....................................................................................... 32

Pinout Information ............................................................................................ 33

4.3.1 PCIe Bus Interface Signals....................................................................... 33

4.3.2 Non-Volatile Memory Interface Signals...................................................... 34

4.3.3 Miscellaneous Signals ............................................................................. 34

4.3.4 PHY Signals........................................................................................... 35

4.3.5 Test Signals........................................................................................... 35

4.3.6 Power Supply Signals.............................................................................. 36

Visual Pin Assignments....................................................................................... 38

4.4

3

82573—Datasheet

Figures

1

2

3

4

5

6

7

8

9

82573 Block Diagram................................................................................................. 9

Minimum Requirements for Power Supply Sequencing ...................................................20

Power Supply Sequencing..........................................................................................21

82573 2.5V and 1.2V LVR Schematic ..........................................................................25

External Clock Oscillator Connectivity to the 82573.......................................................29

82573 Controller TF-BGA Package Ball Pad Dimensions..................................................30

82573 Mechanical Specifications.................................................................................31

82573E and 82573V Gigabit Ethernet Controller Pinout..................................................38

82573L Gigabit Ethernet Controller Pinout....................................................................39

4

Datasheet—82573

Tables

1

2

3

4

5

6

7

8

9

Absolute Maximum Ratings ....................................................................................... 17

Recommended Operating Conditions........................................................................... 17

3.3V External Supply Voltage Ramp and Sequencing Recommendations .......................... 18

2.5V External Supply Voltage Ramp and Sequencing Recommendations .......................... 18

1.2V External Supply Voltage Ramp and Sequencing Recommendations .......................... 19

3.3V Internal Power Supply Parameters ...................................................................... 20

82573 Bill of Materials (BOM) of Components for Internal Regulator................................ 22

2.5V Internal LVR Specification.................................................................................. 22

1.2V Internal LVR Specification.................................................................................. 23

10 PNP Specification ..................................................................................................... 23

11 82573E and 82573V Maximum Measured External Power Characteristics ......................... 25

12 82573E and 82573V Typical Measured External Power Characteristics............................. 26

13 82573E and 82573V 2.5V Internal Power Regulator Numbers......................................... 26

14 82573L Maximum Measured Power Characteristics ....................................................... 27

15 82573L Measured Power Characteristics...................................................................... 27

16 DC Specifications ..................................................................................................... 27

17 LED DC Specifications............................................................................................... 28

18 Crystal Specifications................................................................................................ 28

19 Specification for External Clock Oscillator .................................................................... 29

20 NVM Interface Timing Specifications for EEPROM.......................................................... 29

21 Thermal Resistance Values........................................................................................ 33

22 PCIe Data Signals .................................................................................................... 33

23 PCI Express Miscellaneous Signals.............................................................................. 34

24 Non-Volatile Memory Interface Signals........................................................................ 34

25 Reset and Power-down Signals .................................................................................. 34

26 SMBus Signals......................................................................................................... 34

27 LED Signals............................................................................................................. 34

28 Other Signals .......................................................................................................... 34

29 Analog and Crystal Signals........................................................................................ 35

30 82573E/V MAC Test Signals....................................................................................... 35

31 82573L MAC Test Signals.......................................................................................... 35

32 PHY Test Interface Signals ........................................................................................ 35

33 82573E/V Other Test Signals..................................................................................... 36

34 Power Support Signals.............................................................................................. 36

35 Power Signals.......................................................................................................... 36

36 Ground Signals........................................................................................................ 37

37 82573E/V No Connect Signals.................................................................................... 37

38 82573L No Connect Signals....................................................................................... 37

5

82573—Datasheet

Revision History

Date

Jan 2007

Revision Description

2.5

Updated the PHY_REF signal description in Section 2.6.

Added document order number.

Corrected the AUX_PWR pin (C6) description for the 82573E/V.

Updated Table 18 “Crystal Specifications”.

Updated the visual pin assignments for the 82573L.

Major edit all sections.

Oct 2006

2.4

Chapter 1, Introduction, corrected note.

3.5.1, Removed line item

August 2006

2.3

3.5.2, Corrected title Heading

June 2006

Feb 2006

Sept 2005

June 2005

2.2

2.1

2.0

1.5

Revised Section 3.3, ’PCIe Miscellaneous Signals", updated Intel logo.

Added Section 5.2, ’Thermal Specifications".”

Integrated 82573L information into this document.

Initial public release.

6

Datasheet—82573

1.0

Introduction

Note:

Unless specifically noted, 82573 refers to the Intel® 82573E, 82573V and 82573L GbE

controllers.

82573 GbE controllers are single, compact components with integrated Gigabit

Ethernet Media Access Control (MAC) and Physical Layer (PHY) functions. These

devices use PCIe* architecture (Revision 1.0a). For desktop, workstation, and value

server network designs with critical space constraints, the 82573 enables a GbE

implementation in a very small area.

The 82573 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab, respectively).

In addition to managing MAC and PHY Ethernet layer functions, the 82573 manages

PCIe* packet traffic across its transaction, link, and physical and logical layers.

The 82573E contains a dedicated microcontroller for manageability with an on-board

Intel^®Active Management Technology (Intel^®AMT) enabling network. This enables

manageability implementations required by information technology personnel for out-

of-band management, remote troubleshooting and recovery, asset management, and

non-volatile storage. Intel^®AMT is the first step towards a complete Intel^®Cross-

Platform Manageability Program (Intel® CPMP), which is a business and technology

initiative to deliver consistent management capabilities, protocols, and interfaces

across all Intel platforms.

The 82573E and 82573V GbE controllers have an integrated System Management Bus

(SMBus) port enabling industry standards, such as the Alert Standard Forum (ASF) 2.0.

With SMBus, management packets can be routed to or from a management processor.

In addition, integrated ASF 2.0 circuitry provides alerting and capabilities with

standardized interfaces.

The 82573 with PCIe* architecture is designed for high performance and low memory

latency. The device is optimized to connect to a system I/O Control Hub (ICH7) using

one PCIe* lane. Alternatively, the 82573 is able to connect to a Memory Control Hub

(MCH) device with a PCIe* interface.

Wide internal data paths eliminate performance bottlenecks by efficiently handling

large address and data words. The 82573 efficiently handles packets with minimum

latency by combining a parallel and pipelined logic architecture optimized for GbE and

independent transmit and receive queues. The 82573 also includes advanced interrupt

handling features and uses efficient ring buffer descriptor data structures, with up to 64

packet descriptors per queue cached on chip. A 32-KB on-chip packet buffer maintains

superior performance. In addition, using hardware acceleration, the 82573 offloads

tasks from the host (for example, TCP/UDP/IP checksum calculations and TCP

segmentation).

The 82573L features low power management. During the L1 and L2 link states, the

82573L asserts the Clock Request signal (CLKREQ#) to indicate that its PCIe*

reference clock can be gated.

The 82573 is packaged in a 15 mm X 15 mm, 196-Ball Grid Array (BGA).

7

82573—Datasheet

1.1

1.2

Document Scope

This document contains targeted datasheet specifications for the 82573 GbE controller,

including signal descriptions, DC and AC parameters, packaging data, and pinout

information.

Reference Documents

This application assumes that the designer is acquainted with high-speed design and

board layout techniques. The following documents provide additional information:

• IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers

(IEEE).

• PCI Express Base Specification, Revision 1.0a. PCI Special Interest Group.

• PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special

Interest Group.

• PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special

Interest Group.

• Intel Ethernet Controller Timing Device Selection Guide. Intel Corporation.

• 82573 NVM Map and Programming Information Guide. Intel Corporation.

• 82573/82562 Dual Footprint Design Guide. Intel Corporation.

• PCIe* Family of Gigabit Ethernet Controllers Software Developer’s Manual. Intel

Corporation.

• 82573 Family GbE Controllers Specification Update. Intel Corporation.

8

Datasheet—82573

1.3

82573 Architecture

Figure 1.

82573 Block Diagram

PCIe* Core

NVM

Slave

Access

Logic

DMA Function

Descriptor Management

32 KB

Packet

RAM

Control

Status

Logic

Manage-

ability

(82573E/

Receive

Filters

Transmit

Switch

82573V only)

VLA

N

Statistics

MAC

PHY

Note:

The 82573L does not support manageability.

9

82573—Datasheet

1.4

Product Codes for the 82573

Leaded/

Unleaded

Device

Top Marking

Product Features

82573E with Intel® AMT includes:

•

Intel® AMT

ASF 2.0

Advanced Pass Through (APT)

82573E

RC82573E

Leaded

82573E with Intel® AMT includes:

•

Intel® AMT

ASF 2.0

APT

82573E

PC82573E

Lead Free

82573V Baseline includes:

82573V

82573L

RC82573V

PC82573V

RC82573L

PC82573L

Leaded

•

ASF 2.0

APT

82573V Baseline includes:

•

Lead Free

Leaded

ASF 2.0

APT

82573L:

•

Low-power

No management

82573L:

•

Lead Free

Low-power

No management

2.0

Signal Descriptions

2.1

Signal Type Definitions

The signals of the 82573 are electrically defined as follows:

Name

Definition

Input

I

Standard input only digital signal.

Output

O

Standard output only digital signal.

I/O

TS

Standard I/O digital signal.

Tri-state

Bi-directional three-state digital input/output signal.

Open Drain

Wired-OR with other agents.

OD

The signaling agent asserts the open drain signal, but the signal is returned to the inactive state by

a weak pull-up resistor. The pull-up resistor might require two or three clock periods to fully

restore the signal to the de-asserted state.

Analog

A

P

PCIe, SerDes, or PHY analog signal.

Power

Power connection, voltage reference, or other reference connection.

10

Datasheet—82573

Name

Definition

B

Input Bias

Pull Up

PU

PD

This signal requires a pull-up resistor.

Pull Down

This signal requires a pull-down resistor.

2.2

PCIe* Data Signals

Signal

Type

Name and Function

PCIe Differential Reference Clock

The reference clock is furnished by the system and has a 300 ppm frequency

tolerance. It is used as reference clock for PCIe transmit and receive circuitry

and is used by the PCIe core PLL to generate 125 MHz and 250 MHz clocks for

the PCIe* core logic.

PE_CLKn

PE_CLKp

A(In)

PCIe* Serial Data Output

PE_T0n

PE_T0p

These signals connect to corresponding PERn and PERp signals on a system

motherboard or a PCIe* connector. Series AC coupling capacitors are required

at the 82573 device end. The PCIe* differential outputs are clocked at 2.5 Gb/s.

A(0ut)

A(In)

PCIe Serial Data Input

PE_R0n

PE_R0p

These signals connect to corresponding PETn and PETp signals on a system

motherboard or a PCIe* connector. The PCIe* differential inputs are clocked at

2.5 Gb/s.

2.3

PCIe* Miscellaneous Signals

Signal

PE_RST#

Type

Name and Function

Reset

I

This signal indicates whether or not the PCIe* power and clock are available.

Wake

This signal is driven to zero when it receives a wake-up packet and either the PME

enable bit of the Power Management Control/Status Register is set to 1b or the

Advanced Power Management enabled bit of the Wake Up Control Register equals

1b.

PE_WAKE#

OD

I

Auxiliary Power Present

AUX_

AUX_PRESENT must be pulled up to 3.3V standby power if the 82573 is powered

from standby supplies. This signal must be pulled down if auxiliary power is not

used.

PRESENT

(AUX_PWR)¹

Clock Request.

The Clock Request (CLKREQ#) signal is located at ball P9 of the 82573L. When it is

sampled high, this open-drain signal alerts the system that the 82573L does not

need the PCIe* differential reference clock. During normal operation, the 82573L

keeps CLKREQ# asserted (low), and the system supplies this clock to the device on

the PE_CLKp and PE_CLKn signals. The 82573L deasserts CLKREQ# (high) when it

is in an electrical idle state (L1 and L2), and the system might choose to continue

supplying the reference clock or gate it conserving platform power. The CLKREQ#

signal should be connected to the clock driver that supplies the 82573L PCIe*

clock. If other devices use the same CLKREQ# signal, a pull-up resistor should be

used to ensure that no device pulls this signal low when it is powered off.

CLKREQ#

(82573L only)

OD

1. This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT in the

82573E/V and AUX_PWR in the 82573L.

11

82573—Datasheet

2.4

Non-Volatile Memory Interface Signals

Signal

Type

Name and Function

NVM Serial Data Output

The data output pin is used for input to the non-volatile memory device. This pin is

occasionally used as input during arbitration. This signal has an internal pull-up

resistor.

NVM_SI

I/O

NVM Serial Data Input

NVM_SO

I

The data input pin is used for output from the non-volatile memory device to the

82573. This signal has an internal pull-up resistor.

O

TS

NVM Serial Clock

The serial clock provides the clock rate for the memory interface.

NVM_SK

NVM Chip Enable

NVM_CS#

NVM_REQ

I/O

O

This signal is used to enable the device. This signal has an internal pull-up resistor.

NVM Arbitration Request.

This signal is used to request use of the NVM interface.

NVM Protection Enable.

NVM_PROT

NVM_TYPE

I/PU

This pin should be connected to ground to disable NVM protection; otherwise, NVM

protection is enabled. This signal has an internal pull-up resistor.

NVM Device Type

If the device uses a Flash, this pin should be connected to a pull-down resistor. If

the 82573 is connected to an EEPROM, this pin can be connected to an external

pull-up resistor. This signal has an internal pull-up resistor of 30 KΩ ±50%.

NVM Shared Enable

NVM_SHARED# I/PU

This pin should be connected to a pull-down resistor to enable sharing of SPI Flash

with ICH. This signal has an internal pull-up resistor.

2.5

Miscellaneous Signals

2.5.1

Reset and Power-down Signals

Signal

Type

Name and Function

LAN Power Good

This signal indicates that stable power is available to the 82573. When the signal is

low, LAN_PWR_GOOD acts as a master reset of the entire device. LAN_PWR_GOOD

should be connected to a power supervisor driven from auxiliary power. The signal

should go active approximately 80 ms after all power rails are within their

operating ranges.

LAN_PWR_

GOOD

I

A PCIe* reset must only occur after LAN Power Good is active.

Device Off

DEVICE_OFF#

I

This asynchronously disables the 82573, including voltage regulator control

outputs if selected in external control.

12

Datasheet—82573

1

2.5.2

System Management Bus (SMBus) Signals

Note:

The signals listed in the following table should not be connected when using an 82573L.

Refer to the 82573/82562 Dual Footprint Design Guide reference schematics for more

information.

Signal

SMB_CLK

Type

Name and Function

SMBus Clock

I/O

The SMBus Clock signal is an open drain signal for the serial SMBus interface.

SMBus Data

SMB_DAT

I/O

The SMB Data signal is an open drain signal for the serial SMBus interface.

SMBus Alert/PCI Power Good

The SMBus Alert signal is an open drain signal for serial SMBus interface. In ASF

mode, this signal acts as the PCI Power Good input signal.

SMB_ALRT#/

ASF_PWR_

GOOD

2.5.3

LED Signals

Signal

LED0#

Type

Name and Function

LED0

O

This pin provides a signal for programmable LED indication.

LED1

LED1#

LED2#

This pin provides a signal for programmable LED indication.

LED2

This pin provides a signal for programmable LED indication.

2.5.4

Other Signals

Signal

THERMn

Type

Name and Function

Thermal Test Pins

O

P

THERMp

These pins are used for thermal testing. They can be connected to test points.

Fuse Supply

FUSEV

This should be connected to 2.5V for normal operation.

1. The 82573L does not support the System Management Bus (SMBus).

13

82573—Datasheet

2.6

PHY Analog and Crystal Signals

Signal

Type

Name and Function

Media Dependent Interface [0]

1000BASE-T:

In MDI configuration, MDIp0/MDIn0 corresponds to BI_DA+/-, and in MDI-X

configuration, MDIp0/MDIn0 corresponds to BI_DB+/-.

MDI0n

MDI0p

100BASE-TX:

A

In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X

configuration, MDIp0/MDIn0 is used for the receive pair.

10BASE-T:

In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X

configuration, MDIp0/MDIn0 is used for the receive pair.

Media Dependent Interface [1]

1000BASE-T:

In MDI configuration, MDIp1/MDIn1 corresponds to BI_DB+/-, and in MDI-X

configuration, MDIp1/MDIn1 corresponds to BI_DA+/-.

MDI1n

MDI1p

100BASE-TX:

A

In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X

configuration, MDIp1/MDIn1 is used for the transmit pair.

10BASE-T:

In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X

configuration, MDIp1/MDIn1 is used for the transmit pair.

Media Dependent Interface [2]

1000BASE-T:

In MDI configuration, MDIp2/MDIn2 corresponds to BI_DC+/-, and in MDI-X

configuration, MDIp2/MDIn2 corresponds to BI_DD+/-.

100BASE-TX:

Unused.

MDI2n

MDI2p

A

10BASE-T:

Unused.

Media Dependent Interface [3]

1000BASE-T:

In MDI configuration, MDIp3/MDIn3 corresponds to BI_DD+/-, and in MDI-X

configuration, MDIp3/MDIn3 corresponds to BI_DC+/-.

100BASE-TX:

Unused.

MDI3n

MDI3p

A

10BASE-T:

Unused.

Reference Input

PHY_REF

XTAL1

A

I

This signal is used as the analog reference input for the PHY. It should be

connected to a pull-down, 4.99 K Ω, 1% resistor.

Crystal One

The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel

resonant crystal with a frequency tolerance of 30 ppm. The other end of the crystal

should be connected to XTAL2.

Crystal Two

XTAL2

O

Crystal Two is the output of an internal oscillator circuit used to drive a crystal into

oscillation.

14

Datasheet—82573

2.7

Test Signals

2.7.1

MAC Test Signals

Signal

Type

Name and Function

Factory Test Pin

TEST_EN

I

A 1 KΩ pull-down resistor should be attached to ground from this pin for normal

operation.

Alternate 125 MHz Clock

This signal should not be connected. This signal has an internal pull-up resistor.

ALT_CLK125

JTAG_TCK

NC

I

JTAG Test Access Port Clock

This signal has an internal pull-down resistor.

JTAG Test Access Port Test Data In

This signal has an internal pull-up resistor.

JTAG_TDI

JTAG_TDO

JTAG_TMS

I

O/OD

I

JTAG Test Access Port Test Data Out

JTAG Test Access Port Mode Select

This signal has an internal pull-up resistor.

Clock View

CLK_VIEW

NC

The Clock View signal is an output for the clock signals required for IEEE testing.

This signal has an internal pull-up resistor.

Test Pin[16:0]

TEST[16:0] for

the 82573E/V

TEST[10:0] for

the 82573L

These test pins are for the 82573E/V only. These signals have internal pull-up

resistor. For normal operation, these pins should be left unconnected.

Test Pin[10:0]

These test pins are for the 82573L only. These signals have internal pull-up

resistor. For normal operation, these pins should be left unconnected.

Rsvd

2.7.2

PHY Test Signals

Signal

Type

Name and Function

PHY_HSDACn

PHY_HSDACp

(82573E/V)

PHY Differential Test Port

These signals are used for factory test purposes only.

A(Out)

PHY_TESTn

PHY_TESTp

(82573L only)¹

PHY Test Port

PHY_TSTPT

This signal is used for factory test purposes only. This pin must be left

unconnected for normal operation.

1. These signals are used in all three devices and have the same functionality but are denoted as PHY_HSDACn

and PHY_HSDACp in the 82573E/V and PHY_TESTn and PHY_TESTp in the 82573L.

2.7.3

Other Test Signals

Signal

SDP[3:0]

Type

Name and Function

These signals are used for factory test purposes only and have internal pull-up

resistors.

NC

15

82573—Datasheet

2.8

Power Signals

2.8.1

Power Support Signals

Signal

Type

Name and Function

2.5V Control

This is the voltage control signal for external 2.5V. It is only active when the

EN25REG signal is low (disabled). When external 2.5V and 1.2V supplies are used,

CTRL_25 can be left floating or can be connected to ground through a 3.3 KΩ

resistor.

CTRL_25

P

1.2V Control

This is the voltage control signal for external 1.2V. When external 2.5V and 1.2V

supplies are used, CTRL_12 can be left floating or can be connected to ground

through a 3.3 KΩ resistor.

CTRL_12

EN25REG

P

Enable 2.5V Regulator

When this signal is high, the internal 2.5V regulator is enabled. When it is low, the

internal 2.5V regulator is disables and the CTRL_25 signal is active. This signal

should be pulled up to the 3.3V power rail.

I/PU

2.8.2

Digital and Analog Power Supply Signals

Signal

VCC33

Type

Name and Function

3.3V Power Supply

P

This signal is used for I/O circuits.

2.5V Analog Power Supply

VCC25

VCC12

P

These signals are used for PHY analog, PHY I/O, PCIe* analog and phase lock loop

circuits. All 2.5V pins should be connected to a single power supply.

1.2V Digital Power Supply

These signals are used for core digital, PHY digital, PCIe* digital and clock circuits.

All 1.2V pins should be connected to a single power supply.

IREG25_IN

(82573E/V)

IREG25_IN

P

3.3V power supply for internal 2.5V regulator. When external 2.5V and 1.2V

supplies are used, IREG25_IN should be connected to 3.3V.

VCC3.3_REG25

(82573L only)¹

VCC25_OUT

2.5V output supply from internal power supply. When external 2.5V and 1.2V

supplies are used, VCC25_OUT can be left floating.

1. This signal is used in all three devices and has the same functionality but is denoted as IREG25_IN for the

82573E/V and VCC3.3_REG25 for the 82573L.

2.9

Grounds and No Connects

Signal

Type

Name and Function

Ground

VSS

NC

P

These signals connect to ground.

VSS is also referred to as GND.

No Connect

These pins are reserved by Intel and might have factory test functions. For normal

operation, do not connect any circuitry to these pins. Do not connect pull-up or

pull-down resistors.

16

Datasheet—82573

3.0

Voltage, Temperature, and Timing Specifications

3.1

Absolute Maximum Ratings

Table 1.

Absolute Maximum Ratings¹

Symbol

Tstg

Parameter

Min

Max

Unit

Storage temperature

-40

125

°C

DC supply voltage on 3.3V pins

with respect to VSS

VCC (3.3)

VCC (2.5)

VCC (1.2)

Vin

-0.3

-1.0

6.6

5.0

2.4

V

DC supply voltage on 2.5V pins

with respect to VSS²

DC supply voltage on 1.2V pins

with respect to VSS^b

VCC (3.3) + 0.3

(less than 6.6 V)

Input voltage (digital inputs)

Analog input voltage (digital

inputs)

VCC (2.5) + 0.3

(less than 5.0 V)

AVin

R_PUD

-1.0

15

V

Pull-up/pull-down Resistor Value

50

KΩ

1. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings

in this table are exceeded for an indefinite duration. These values should not be used as the limits for normal

device operations. This specification is not guaranteed by design or simulations.

2. During normal device power up and power down, the 2.5V and 1.2V supplies must not ramp before the 3.3V.

3.2

Recommended Operating Conditions

Table 2.

Recommended Operating Conditions

Symbol

Parameter

Condition

Min

Typical

Max

Units

Operating Temperature with

external regulators

0

70

°C

T_OP

Operating temperature with

on-die 2.5V regulator

0

55

°C

V_PERIF

V_D

Periphery Voltage Range

Core Digital Voltage Range

Analog VDD Range

3.3 V ± 3%

1.2 V ± 5%

2.5 V ± 5%

3.0

1.14

2.375

3.3

1.2

2.5

3.6

1.26

2.625

V

V_A

3.3

Power Supply Connections

There are three options in providing power to the 82573:

• Connecting the 82573 to three external power supplies with nominal voltages of

3.3V, 2.5V, and 1.2V. This is covered in Section 3.3.1.

• Powering the 82573 with only an external 3.3V supply and using internal power

regulators from the 82573 combined with external PNP transistors to supply the

2.5V and 1.2V levels. This is covered in Section 3.3.3.

• Using the 2.5V internal (on-die) regulator combined with an external PNP transistor

to supply the 1.2V level. This is covered in Section 3.3.3.

17

82573—Datasheet

3.3.1

External LVR Power Delivery

The following power supply requirements apply to designs where the 82573 is supplied

by external voltage regulators. These systems do not use the internal regulator logic

built into the 82573 as described in Section 3.3.3.

Table 3.

3.3V External Supply Voltage Ramp and Sequencing Recommendations

Parameter

Rise Time

Description

Rise time from 10% to 90%

Min

Max

Unit

5

100¹

300

ms

Monotonicity

Voltage dip allowed in ramp

mV

Ramp rate at any time between 10% to 90%

Minimum = (0.8 * Vmin) / (Maximum Rise Time)

Maximum = (0.8 * Vmax) / (Minimum Rise Time)

Slope

1500

mV/ms

Operational Range Voltage range for normal operating conditions

3

3.6

100

660

V

mV_pk-pk

mV

Ripple

Maximum voltage ripple at a bandwidth of 50 MHz

Maximum voltage allowed²

Overshoot

Capacitance

Minimum capacitance

25

µF

1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.

2. Excessive overshoot can affect long term reliability.

Table 4.

2.5V External Supply Voltage Ramp and Sequencing Recommendations

Parameter

Rise Time

Description

Rise time from 10% to 90%

Min

Max

Unit

2.5

100¹

200

ms

Monotonicity

Voltage dip allowed in ramp

mV

Ramp rate at any time between 10% to 90%

Minimum = (0.8 * Vmin) / (Maximum Rise Time)

Maximum = (0.8 * Vmax) / (Minimum Rise Time)

Slope

1500

mV/ms

Operational Range Voltage range for normal operating conditions

2.375

-5

2.625

+5

V

%

Ripple

Maximum voltage ripple at a bandwidth of 50 MHz

60

mV_pk-pk

Maximum voltage allowed will not exceed 10% of

nominal supply

Undershoot

Overshoot

Maximum voltage allowed²

480

25

mV

µF

Output

Capacitance

Capacitance range when using a PNP circuit

4.7

Input Capacitance

Capacitance ESR

Capacitance range when using a PNP circuit

µF

Equivalent series resistance of output capacitance³

10

20

mΩ

Maximum output current rating with respect to

CTRL_25

I_CTRL

mA

1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.

2. Excessive overshoot can affect long term reliability.

3. Tantalum capacitors must not be used.

18

Datasheet—82573

Table 5.

1.2V External Supply Voltage Ramp and Sequencing Recommendations

Parameter

Rise Time

Description

Rise time from 10% to 90%

Min

Max

Unit

1.5¹

ms

Monotonicity

Voltage dip allowed in ramp

120

mV

Ramp rate at any time between 10% to 90%

Minimum = (0.8 * Vmin) / (Maximum Rise Time)

Maximum = (0.8 * Vmax) / (Minimum Rise Time)

Slope

1500

mV/ms

Operational Range Voltage range for normal operating conditions

1.14

-5

1.26

+5

V

%

Ripple

Maximum voltage ripple at a bandwidth of 50 MHz

60

mV_pk-pk

Maximum voltage allowed will not exceed 10% of

nominal supply

Undershoot

Overshoot

Maximum voltage allowed²

500

25

mV

µF

Output

Capacitance

Capacitance range when using a PNP circuit

4.7

Input Capacitance

Capacitance ESR

Capacitance range when using a PNP circuit

µF

Equivalent series resistance of output capacitance³

10

20

mΩ

Maximum output current rating with respect to

CTRL_12

I_CTRL

mA

1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.

2. Excessive overshoot can affect long term reliability.

3. Tantalum capacitors must not be used.

3.3.2

Power Sequencing with External Regulators

The following power-on and power-off sequence should be applied when external power

supplies are in use. Designs must comply with the required power sequence to avoid

risk of either latch-up or forward biased internal diodes.

Generally, the 82573 power sequencing should power up the three power rails in the

following order: 3.3V Æ 2.5V Æ 1.2V. However, if this general guideline is not followed,

there are specific requirements that must be adhered to. These requirements are listed

in the following two subsections.

3.3.2.1

External LVR Power Up Sequencing and Tracking

Sequencing of the external supplies during power up might be necessary to ensure that

the 82573 is not electrically overstressed and does not latch-up. These requirements

are shown in Figure 2.

The 82573 core voltage (1.2V) cannot exceed the 3.3V supply by more than 0.5 V at

any time during the power up. The 82573 core voltage (1.2V) cannot exceed the 2.5V

supply by more than 0.5 V at any time during the power up. The core voltage is not

required to begin ramping before the 3.3V or the 2.5V supply.

The 82573 analog voltage (2.5V) can not exceed the 3.3V supply by more than 0.5 V at

any time during the power up. The analog voltage is not required to begin ramping

before the 3.3V supply.

19

82573—Datasheet

Figure 2.

Minimum Requirements for Power Supply Sequencing

3.3V

2.5V

3.3V

2.5V

Max Difference

1.2V (Core Supply)

≤ 0.3 V

Max Difference

≤ 0.3 V

1.2V (Core Supply)

Max Difference ≤ 0.3 V

• If the 1.2V and 2.5V rails power up before 3.3V, they should never exceed the 3.3V

supply by more than 0.3 V.

• At power down, all three supplies should be turned off simultaneously. If the 3.3V

supply powers down first, the 1.2V and 2.5V supplies must never exceed the 3.3V

supply by more than 0.3 V.

3.3.2.2

External LVR Power Down Sequencing

There are no specific power down sequencing and tracking requirements for the 82573

silicon. The risk of latch-up or electrical overstress is small since the only charge storing

in decoupling capacitors is left in the system.

3.3.3

Internally Generated Power Delivery

The 82573 has two internal linear voltage regulator controllers. The controllers use

external transistors to generate 2 of the 3 required voltages: 2.5V (nominal) and 1.2V

(nominal). These two voltages are stepped down from a 3.3V source.

Table 6.

3.3V Internal Power Supply Parameters

Parameter

Rise Time

Description

Min

Max

Units

Time from 10% to 90% mark

Voltage dip allowed in ramp

5

-

ms

Monotonicity

300

mV

Ramp rate at any given time between

10% and 90%

Min: 0.8*V(min)/Rise time (max)

Max: 0.8*V(max)/Rise time (min)

Slope

-

1500

mV/ms

Voltage range for normal operating

conditions

Operational Range

3.0

3.6

V

Ripple¹

Maximum voltage ripple (peak to peak)

Maximum overshoot allowed

-

100

660

mV

Overshoot

Maximum overshoot allowed duration.

Overshoot Settling

Time

(At that time delta voltage should be

lower than 5 mV from steady state

voltage)

-

3

ms

1. The peak to peak output rippled is measured at 20 MHz bandwidth within the operational range.

20

Datasheet—82573

3.3.4

Internal LVR Power Sequencing

All supplies should rise monotonically. Sequencing of the supplies is controlled by the

82573.

3.3.4.1

Power Up Sequencing and Tracking

During power up, the sequencing and tracking of the internally controlled supplies

(2.5V and 1.2V) are controlled by the 82573. No specific motherboard requirements

are necessary to prevent electrical overstress or latch-up.

The 82573 analog voltage (2.5V) never exceeds the 3.3V supply at any time during the

power up. This is because the 2.5V supply is generated from the 3.3V supply when the

internal voltage regulator control logic is being used. Figure 3 shows the internal LVR

circuit. The 2.5V supply tracks the 3.3V ramp.

The 82573 core voltage (1.2V) never exceeds the 3.3V at any time during the power

up. This is because the 2.5V supply is generated from the 3.3V supply when the

internal voltage regulator control logic is being used. Figure 3 shows the internal LVR

circuit. The 1.2V ramp is delayed internally to prevent it from exceeding the 2.5V and

3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.

The delay is approximated by T_ramp(3.3V)*0.25 < T_delay(1.2V) < T_ramp(3.3V)*0.75.

T_rampis defined to the ramp rate of the 3.3V input to the internal voltage regulator

circuit.

Figure 3.

Power Supply Sequencing

Voltage

3.3V

LAN_PWR_GOOD

2.5V

1.2V

0

Time

Minimum 80 ms

• It is recommended that the voltage on a lower voltage rail never exceed the

voltage on a higher voltage rail during power on.

• There are no minimum time requirements between the voltage rails as long as they

power up in sequence: 3.3V → 2.5V → 1.2V.

• All 3 supplies must be stable for at least 80 ms before LAN_PWR_GOOD is

asserted. 100 ms is preferable if possible.

• A PCIe* reset must occur after LAN Power Good is active.

3.3.4.2

Internal LVR Power Down Sequencing

There are no specific power down sequencing and tracking requirements for the 82573

device. The risk of latch-up or electrical overstress is small because the only charge

storing in decoupling capacitors is left in the system.

21

82573—Datasheet

3.3.4.3

Table 7.

Internal Voltage Regulators Components for the 82573

82573 Bill of Materials (BOM) of Components for Internal Regulator

Recommended Component

Description

Quantity

Manufacturer

Philips

Part Number

BCP-69-16

Package

SOT-223

PNP Transistor

For 1.2V LVR

1

PNP Transistor

For 2.5V LVR

Philips

BCP-69-16

3.3.4.4

Table 8.

2.5V Internal LVR Specification

2.5V Internal LVR Specification¹

Value

Parameter

Units

Comments

Minimum Maximum

Input Voltage

3.0

5

3.6

V

Input Voltage Slew Rate

ms

Input Capacitance

4.7

µF

Input Capacitance ESR

10

mΩ

Load Current

1

-

A

V_OUT= 2.500 V

Output Voltage Tolerance

-5

+5

%

Output Capacitance

4.7

µF

Output Capacitance ESR

10

mΩ

mA

Current Consumption During Power Up

0.5

Current Consumption During Power Down

Maximum Undershoot

0.5

mA

%

< 10

of nominal supply

±60 mV at 20 MHz

bandwidth

Peak to Peak Output Ripple

PSRR

120

20

mV

dB

External PNP h_FE

100

1. The use of tantalum capacitors is not recommended.

22

Datasheet—82573

3.3.4.5

Table 9.

1.2V Internal LVR Specification

1.2V Internal LVR Specification¹

Value

Parameter

Units

Comments

Maximu

Minimum

m

Input Voltage

3.0

5

3.6

V

Input Voltage Slew Rate

ms

Input Capacitance

4.7

µF

Input Capacitance ESR

10

mΩ

Load Current

1

-

A

V_OUT= 1.200 V

Output Voltage Tolerance

-5

+5

%

Output Capacitance

4.7

µF

mΩ

mA

Output Capacitance ESR

10

Current Consumption During Power Up

0.5

Current Consumption During Power Down

Maximum Undershoot

0.5

mA

%

< 10

of nominal supply

±60 mV at 20 MHz

bandwidth

Peak to Peak Output Ripple

PSRR

120

20

mV

dB

External PNP h_FE

100

1. The use of tantalum capacitors is not recommended.

3.3.4.6

PNP Transistor Specification for Internal LVR

Table 10.

PNP Specification (Sheet 1 of 2)

Symbol

V_ce,sat

Description

Min

Max

Units

Collector-Emitter Saturation Voltage

Collector Current, Maximum Sustained

Base Current, Maximum Sustained

Base-Emitter on Voltage

-

0.5

1000

10

V

I_c(max)

I_b

mA

V

V_be

1

T_jmax

Maximum Junction Temperature

125

°C

23

82573—Datasheet

Table 10.

PNP Specification (Sheet 2 of 2)

Symbol

Description

Min

Max

Units

Power

Maximum Total Power Dissipation

-

1.35

W

Dissipation

h_FE

DC Current Gain

100

10

-

f_T

Current Gain Product Bandwidth

MHz

3.3.4.7

Internal LVR Board Schematic

When using the internal voltage regulator controllers built into the 82573, resistors

might need to be placed in series with the emitter in order to prevent the PNP

transistors from overheating. These series resistors dissipate a portion of the power

that would otherwise be dissipated by the PNP devices. The value and power rating of

the resistors must be carefully chosen to balance thermal limits against the PNP

characteristics against total current draw. The regulator must never drop below the

minimum V_ceand out of the linear region.

The effective resistance of the pass resistors should equal approximately 1 Ω and have

a combined power dissipation rating of 0.5 Watts for the 82573. Figure 4 shows the

recommended implementation.

24

Datasheet—82573

Figure 4.

82573 2.5V and 1.2V LVR Schematic

2.5V Voltage Regulator

Intel recommends using

40uF at the emitter of Q3

on the 3.3V rail.

Install when using the

Integrated 2.5V Voltage

Regulator with External

Pass Transistor. Do not

Use ceramic capacitors.

install if on-die 2.5V

regulator is used.

Q3 Requires Heat-

Sink surface pad of

0.5'' x 0.5'' min.

1 ohm is not needed for R60 for 82573L.

0 ohm may be used instead. 82573L only

designs may connect C23 directly to 2.5V.

Intel recommends using

40uF at the emitter of Q4

on the 3.3V rail.

1.2V Voltage Regulator

Use ceramic capacitors.

Q4 Requires Heat-Sink surface

pad of 0.5'' x 0.5'' min.

1 ohm is not needed for R61 for 82573L.

0 ohm may be used instead. 82573L only

designs can connect C29 directly to 1.2V.

3.4

DC and AC Specifications

Table 11.

82573E and 82573V Maximum Measured External Power Characteristics¹

System

State

82573E Power (mW)

with Intel® AMT

82573V Power (mW)

without Intel® AMT

Link State

1000 Mbps Active

(Maximum Power)

S0

1548

1426

1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.

25

82573—Datasheet

Table 12.

82573E and 82573V Typical Measured External Power Characteristics¹

3.3V

Current

(mA)

2.5V

Current

(mA)

1.2V

Current

(mA)

82573E/V

System

State

Link State

Power

(mW)^{2 3}

1000 Mb/s:

Intel® AMT

12

297

551

1443.3

(82573E only)

1000 Mb/s Active

1000 Mb/s Idle

100 Mb/s Active

100 Mb/s Idle

12

11

7

297

276

130

107

167

76

490

380

1370.1

1185.6

534.7

425

S0

144.5

101

10 Mb/s Active

10 Mb/s Idle

125.5

82

591.2

311.5

197.5

408.5

292.5

177.3

173.1

7

No Link (SPD)

3

40

73

100 Mb/s Idle (wake)

10 Mb/s Idle (wake)

No Link (no wake)

Device Off

11

7

104

72

93.5

74.5

64.5

48.5

Sx

3

36⁴

42^d

3

1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.

2. For 10/100 Mb/s non-stress mode with Intel® AMT, add 12 mW to this number (for example,

using IDE-R functionality).

3. For 10/100 Mb/s stress mode active Intel® AMT, add 120 mW to this number (for example, using

IDE-R functionality).

4. The current use is slightly higher in the device off state than in the no link state. This occurs since

a PHY reset is required in the device off state, which overrides the PHY power down.

Table 13.

82573E and 82573V 2.5V Internal Power Regulator Numbers

2.5V

3.3V

Current

(mA)

1.2V

Current

(mA)

82573E/V

Power

(mW)

System

State

Current (mA)

(on-die 2.5V

regulator)

Link State

1000 Mb/s: Active with

Full Management

313

Internal

607

1760

1000 Mb/s Active

1000 Mb/s Idle

100 Mb/s Active

100 Mb/s Idle

313

294

142

119

173

84

Internal

506

404

145

101

126

83

1638

1453

642

513

722

376

233

S0

10 Mb/s Active

10 Mb/s Idle

D0 No Link (SPD)

44

73

D3 100 Mb/s Idle

(wake)

116

80

Internal

94

75

493

354

Sx

D3 10 Mb/s Idle

(wake)

D3 No Link (no wake)

Device Off

40

45

Internal

64

49

209

207

26

Datasheet—82573

Table 14.

Table 15.

82573L Maximum Measured Power Characteristics¹

System

State

Link State

82573L (mW)

S0

1000 Mb/s Active (Maximum Power)

1296

1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.

82573L Measured Power Characteristics

System

State

3.3V

2.5V

1.2V

82573L

Power (mW)

Link State

Current (mA) Current (mA) Current (mA)

1000 Mb/s Active

1000 Mb/s Idle

14.8

14.0

14.2

10.5

10.3

6.2

288.5

243.2

121.3

78.8

169

372.5

294.0

111.5

58.5

118

1217

1010

483

314

504

194

53

100 Mb/s Active

S0

Sx

100 Mb/s Idle

10 Mb/s Active

10 Mb/s Idle

143.5

7.0

91.8

12.3

49.3

31.0

12.2

D0 No Link (SPD)

D3 100 Mb/s Idle (wake)

D3 10 Mb/s Idle (wake)

D3 No Link (no wake)

14.2

10.5

6.2

78.8

45.7

7.3

303

186

53

Table 16.

DC Specifications

Symbol

Vih

Parameter

Condition

Min

Max

Unit

Input High Voltage

Input Low Voltage

Input Hysteresis

2.0

V

Vil

0.8

Vhy

Voh

Vol

100

2.4

mV

V

Output High Voltage

Output Low Voltage

Input Leakage Current

0.4

V

Ilkg

0 < Vin < VCCP

±50

µA

Rpup/

Rpdn

Internal Pull Up and Pull

Down Resistor

15

50

KΩ

Cin/out

Cout

Pin Capacitance

Input and bi-directional buffer

Output only buffer

2.5

2.0

pF

Output Pin Capacitance

27

82573—Datasheet

Table 17.

LED DC Specifications

Symbol

Voh

Parameter¹

Condition

Min

Max

Unit

Output High Voltage

Output Low Voltage

at 12 mA

2.4

V

Vol

Ioz

0.4

3-state Output Leakage

Current

Voh = VDD or VSS

±10

mV

VDD = 3.6 V, Vo = VDD,

VDD = 3.6 V, Vo = VSS

Ios

Output Short Current

Pin Capacitance²

µA

pF

Cin/out

Input and bi-directional buffer

2.5

1. Outputs are inputs/outputs in test mode.

2. This parameter is characterized but not tested.

3.5

External Interfaces

Crystal

3.5.1

The quartz crystal is strongly recommended as a low cost and high performance choice

with the 82573 device. Quartz crystals are the mainstay of frequency control

components and are available from numerous vendors in many package types with

various specification options.

Table 18.

Crystal Specifications

Parameter Name

Symbol

Recommended Value

Max/Min Range

Conditions

Frequency

f_o

25.000 MHz

Fundamental

±30 ppm

-

at 25 °C

Vibration mode

-

∆f/f_oat 25 °C

∆f/f_o

-

Frequency Tolerance

Temperature Tolerance

Operating Temperature

at 25 °C

±30 ppm

-

T_opr

0 °C to +70 °C

Equivalent Series

Resistance (ESR)

R_s

40 Ω

50 Ω (max)

at 25 MHz

Load Capacitance

Shunt Capacitance

Max Drive Level

Nominal Drive Level

Aging

C_load

C_o

20 pF

6 pF

-

DL

500 µW

200 µW

±5 ppm per year

4 pF

1 mW

DL

500 µW

f/f_o

C_s

±5 ppm per year

1

Board Capacitance

External Capacitors

Board Resistance

C1, C2

R_s

22 pF

0.1 Ω

1 Ω

1. This value can change up to 10%.

3.5.2

External Clock Oscillator

If an external oscillator is used to provide a clock to the 82573, the connection shown

in the figure below must be used. The XTAL2 output signal of the 82573 must not be

connected. The XTAL1 input signal receives the output of the oscillator directly. AC

coupling is not recommended.

28

Datasheet—82573

Figure 5.

External Clock Oscillator Connectivity to the 82573

82573

82563EB/82564EB

XTAL2

3.3V

XTAL1

Table 19.

Specification for External Clock Oscillator

Parameter Name

Frequency

Symbol

Value

Conditions

f_o

25.0 MHz

3.3 ± 0.3 V

±30 ppm

at 25 °C

Swing

V_p-p

∆f/f_o

T_opr

∆f/f_o

-

Frequency Tolerance

Operating Temperature

Aging

0 °C to +70 °C

-

-20 °C to +70 °C

±5 ppm per year

3.5.3

Non-Volatile Memory (NVM) Interface: EEPROM

Table 20.

NVM Interface Timing Specifications for EEPROM (Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Units

SCK clock

frequency

t_SCK

0

2

2.1

MHz

t_RU

Input rise time

Input fall time

SCK high time¹

SCK low time^a

CS high time

CS setup time

CS hold time

2.5

2

µs

ns

t_FI

t_WH

t_CS

200

250

t_CSS

t_CSH

Data-in setup

time

t_SU

50

ns

Data-in hold

time

t_H

t_V

50

0

ns

Output Valid

200

29

82573—Datasheet

Table 20.

NVM Interface Timing Specifications for EEPROM (Sheet 2 of 2)

Symbol

Parameter

Min

Typ

Max

Units

Output hold

time

t_HO

0

ns

Output disable

time

t_DIS

t_WC

1. 50% duty cycle.

250

10

ns

Write cycle time

ms

4.0

Package and Pinout Information

This section describes the 82573 physical characteristics and pin-to-signal mapping.

4.1

Package Information

The 82573 device is a lead-free 196-pin thin and Fine Pitch Ball Grid Array (TF-BGA)

measuring 15 mm by 15 mm. The nominal ball pitch is 1.0 mm.

Figure 6.

82573 Controller TF-BGA Package Ball Pad Dimensions

Detail Area

0.4 mm

Solder Resist Opening

0.55 mm

Metal Diameter

30

Datasheet—82573

Figure 7.

82573 Mechanical Specifications

31

82573—Datasheet

4.2

Thermal Specifications

The case temperature (T_C) is calculated using the equation:

T_C= T_A+ P (⎝JA - ⎝JC)

Junction temperature (T_J) is calculated using the equation:

T_J= T_A+ P ⎝JA

The power consumption (P) is calculated by using the typical ICC and nominal VCC

where T_Arepresents the ambient temperature. The thermal resistances are listed in

Table 21.

32

Datasheet—82573

Table 21.

Thermal Resistance Values

Value at Specified Airflow (m/s)

Symbol

Parameter

Units

0

1

2

3

TJ

Maximum junction temperature

127.1

122.1

119.3

117.5

C

Thermal resistance, junction-to-

ambient

⎝JA

26.0

6.1

23.7

6.1

22.4

6.1

21.6

6.1

C/Watt

Thermal resistance, junction-to-

case

⎝JC

C/Watt

Thermal resistances are determined empirically with test devices mounted on standard

thermal test boards. Real system designs may have different characteristics due to

board thickness, arrangement of ground planes, and proximity of other components.

The case temperature measurements should be used to assure that the 82573 is

operating under recommended conditions. The use of a heat sink device is not

required.

4.3

Pinout Information

4.3.1

PCIe Bus Interface Signals

Table 22.

PCIe Data Signals

Signal

PE_CLKn

PE_CLKp

G2

G1

PE_T0n

PE_T0p

C1

D1

PE_R0n

PE_R0p

F1

F2

33

82573—Datasheet

Table 23.

PCI Express Miscellaneous Signals

Signal

AUX_PRESENT

(82573E/V) /

AUX_PWR

PE_RST#

P7

P9

PE_WAKE#

P10

C6

(82573L)¹

CLKREQ# (82573L

only)

1. This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT

in the 82573E/V or AUX_PWR in the 82573L.

4.3.2

Non-Volatile Memory Interface Signals

Table 24.

Non-Volatile Memory Interface Signals

Signal

NVM_SI

Signal

NVM_CS#

Signal

NVM_TYPE

A9

B9

C9

B10

B4

A6

D3

NVM_SO

NVM_SK

NVM_REQ

NVM_SHARED#

NVM_PROT

A5

4.3.3

Miscellaneous Signals

Table 25.

Reset and Power-down Signals

Signal

LAN_PWR_GOOD

P5

DEVICE_OFF#

L7

Table 26.

SMBus Signals

Signal

SMB_ALRT#/

ASF_PWR_

GOOD

SMB_CLK

P11

SMB_DAT

M11

N11

Table 27.

Table 28.

LED Signals

Signal

LED1#

Signal

LED0#

B11

C11

LED2#

A12

Other Signals

Signal

THERMp

Signal

THERMn

L2

L3

34

Datasheet—82573

4.3.4

PHY Signals

Table 29.

Analog and Crystal Signals

Signal

MDI0n

Signal

MDI2n

Signal

PHY_REF

C14

C13

E14

E13

F14

F13

H14

H13

D12

K14

J14

MDI0p

MDI1n

MDI1p

MDI2p

MDI3n

MDI3p

XTAL1

XTAL2

4.3.5

Test Signals

Table 30.

82573E/V MAC Test Signals¹

Signal

TEST_EN

Signal

TEST1

Signal

A13

N10

N5

H2

H3

J1

TEST9

M3

N2

P1

ALT_CLK125

JTAG_TCK

JTAG_TDI

JTAG_TDO

TESTPT2

TESTPT3

TESTPT4

TEST5

TEST10

TEST11

TEST12

TEST13

P4

J2

N3

M8

P6

J3

TEST14

(82573E/V only)

JTAG_TMS

CLK_VIEW

TEST0

N4

TEST6

TEST7

TEST8

K1

L1

P9

TEST15

(82573E/V only)

L14

H1

E3

TEST16

(82573E/V only)

M1

A14

1. These test signals do not apply to the 82573L.

Table 31.

82573L MAC Test Signals¹

Signal

TEST_EN

Signal

CLK_VIEW

Signal

A13

N10

N5

L14

TEST5

TEST6

TEST7

TEST8

TEST9

J3

ALT_CLK125

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

TEST0

H1

H2

H3

J1

K1

L1

M1

M3

TEST1

P4

TESTPT2

TESTPT3

TESTPT4

P6

N4

J2

1. These test signals do not apply to the 82573E or 82573V devices.

Table 32.

PHY Test Interface Signals

Signal

PHY_HSDACn

B13

PHY_HSDACp

B12

PHY_TSTPT

B14

35

82573—Datasheet

Table 33.

82573E/V Other Test Signals¹

Signal

SDP[1]

Signal

SDP[2]

SDP[0]

SDP[3]

A8

C7

B8

C8

1. These test signals do not apply to the 82573L.

4.3.6

Power Supply Signals

Table 34.

Power Support Signals

Signal

CTRL_25

Signal

CTRL_12

Signal

EN25REG

A4

P3

B5

Table 35.

Power Signals

Signal

VCC33

IREG25_IN

FUSEV

VCC25

A7

VCC25

VCC25_OUT

VCC12

J12

VCC12

J6

D9

F3

J4

K13

L12

M4

J7

J8

J9

M10

N6

N8

P2

N7

J10

J11

K3

K4

K5

K6

K7

K8

K9

K10

K11

L5

B1

B2

A10

C4

P12

A2

C5

A3

F12

G6

M2

A11

B6

G12

G13

H6

G3

G5

H4

H5

J5

H7

H8

L9

H11

H12

L10

36

Datasheet—82573

Table 36.

Ground Signals

Signal

VSS

A1

VSS

E5

E6

E7

E8

E9

E10

F4

VSS

G4

B3

G7

C2

G8

C10

C12

D2

D4

D5

D6

D7

D8

D13

E2

G9

G10

G11

G14

H9

F5

F6

H10

K2

F7

F8

N1

F9

N12

P8

F10

F11

E4

Table 37.

82573E/V No Connect Signals¹

Signal

NC

B7

NC

K12

L4

NC

M9

C3

M12

M13

M14

N9

D10

D11

D14

E1

L6

L8

L11

L13

M5

M6

M7

N13

N14

P13

P14

E11

E12

J13

1. These test signals do not apply to the 82573L.

Table 38.

82573L No Connect Signals¹(Sheet 1 of 2)

Signal

NC

A8

NC

E12

J13

K12

L4

NC

M9

A14

B7

NC

M12

M13

M14

N2

B8

C3

L6

C7

L8

N3

C8

L11

L13

N9

D10

N13

37

82573—Datasheet

Table 38.

82573L No Connect Signals¹(Sheet 2 of 2)

Signal

NC

D11

D14

E1

NC

M5

M6

M7

M8

NC

N14

P1

P13

P14

E3

E11

1. These test signals do not apply to the 82573E or 82573V devices.

4.4

Visual Pin Assignments

M

A

B

C

D

E

F

G

H

J

K

L

N

P

VCC25_

OUT

VSS

PE_T0n

PE_TR0p

NC

PE_R0n

TEST0

TEST3

TEST6

TEST7

TEST8

FUSEV

TEST9

VCC25

NC

PE_CLKp

VSS

TEST11

1

2

3

4

5

6

VCC25_

OUT

VSS

NC

VSS

PE_R0p

VCC33

VSS

PE_CLKn

VCC25

VSS

TEST1

TEST2

TEST4

TEST5

VCC33

VCC25

VCC12

VCC25

NC

VSS

THERMn

TEST10

VCC33

IREG25_IN

NVM_

SHARED

VSS

TEST15

VSS

VCC12

NC

TEST12

THERMp

NC

CTRL_12

JTAG_TDI

VCC12

CTRL_25

NVM_REQ

EN25REG

VCC25

VSS

VCC25

JTAG_TMS

JTAG_

TCK

NVM_

PROT

LAN_PWR_

GOOD

VSS

VCC25

VCC12

VSS

VCC25

VCC12

VSS

VCC12

NC

AUX_

PRESENT

NVM_

TYPE

JTAG_TDO

VSS

NC

VCC33

VCC25

VCC33

DEVICE_

OFF#

VCC33

SDP[0]

NC

SDP[3]

SDP[2]

NVM_SK

VSS

NC

PE_RST#

VSS

7

8

9

SDP[1]

VSS

NC

TEST13

NC

NVM_SI

VCC12

NVM_SO

NVM_CS#

VCC33

NC

VSS

VCC12

NC

TEST14

PE_WAKE#

VSS

ALT_CLK125

VCC33

SMB_DAT

NC

10

11

12

13

14

SMB_ALRT#/

ASF_PWR_

GOOD

VCC25

LED2#

LED0#

LED1#

VSS

NC

VSS

VCC12

MDI3p

MDI3n

SMB_CLK

VCC33

NC

PHY_

HSDACp

PHY_REF

VSS

NC

VCC12

MDI2p

MDI2n

VCC12

VSS

VCC25

NC

VSS

NC

PHY_

HSDACn

TEST_EN

TEST16

MDI0p

MDI0n

MDI1p

MDI1n

VCC25

XTAL1

NC

PHY_

TSTPT

CLK_VIEW

NC

XTAL2

NC

Figure 8.

82573E and 82573V Gigabit Ethernet Controller Pinout

38

Datasheet—82573

Figure 9.

82573L Gigabit Ethernet Controller Pinout

M

A

B

C

D

E

F

G

H

J

K

L

N

P

VCC25_

OUT

VSS

PE_T0n

PE_TR0p

NC

PE_R0n

TEST0

TEST3

TEST6

TEST7

TEST8

VSS

NC

PE_CLKp

1

2

3

4

5

6

VCC3.3_

REG25

VCC25_

OUT

VSS

PE_R0p

VCC33

PE_CLKn

VCC25

TEST1

TEST2

TEST4

TEST5

VSS

THERMn

FUSEV

TEST10

NC

VCC33

VCC3.3_

REG25

NVM_

SHARED

VSS

NC

VCC12

TEST9

VCC25

THERMp

NC

CTRL_12

JTAG_TDI

VCC12

CTRL_25

NVM_REQ

EN25REG

VSS

VCC25

VCC33

VCC25

VCC12

JTAG_TMS

JTAG_

TCK

NVM_

PROT

LAN_PWR_

GOOD

VSS

VCC25

VCC12

NC

NVM_

TYPE

JTAG_TDO

VCC25

NC

AUX_PWR

NC

VSS

VCC12

VSS

VCC12

NC

VCC33

VCC25

VCC33

DEVICE_

OFF#

VCC33

PE_RST#

VSS

7

8

9

NC

VSS

NC

NVM_SI

VCC12

NVM_SO

NVM_CS#

NVM_SK

VCC33

NC

VSS

VCC12

NC

CLK_REQ#

PE_WAKE#

VSS

ALT_CLK125

VCC33

RSVD

10

11

12

13

14

VCC25

LED0#

LED1#

NC

VSS

VCC12

NC

RSVD

PHY_

HSDACp

LED2#

VSS

PHY_REF

VSS

NC

VCC12

MDI2p

VCC12

MDI3p

VCC25

NC

VCC25

NC

VSS

NC

VCC33

NC

PHY_

HSDACn

TEST_EN

MDI0p

MDI1p

VCC25

PHY_

TSTPT

CLK_VIEW

NC

MDI0n

NC

MDI1n

MDI2n

VSS

MDI3n

XTAL2

XTAL1

NC

39

型号:	PC82573L
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	BGA
包装说明：	LBGA, BGA196,14X14,40
针数：	196
Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01
风险等级：	5.76
地址总线宽度：
边界扫描：	YES
总线兼容性：	PCI
最大时钟频率：	25 MHz
数据编码/解码方法：	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率：	125 MBps
外部数据总线宽度：
JESD-30 代码：	S-PBGA-B196
JESD-609代码：	e1
长度：	15 mm
低功率模式：	YES
串行 I/O 数：	1
端子数量：	196
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA
封装等效代码：	BGA196,14X14,40
封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	260
电源：	1.2,2.5,3.3 V
认证状态：	Not Qualified
座面最大高度：	1.6 mm
子类别：	Serial IO/Communication Controllers
最大供电电压：	1.26 V
最小供电电压：	1.14 V
标称供电电压：	1.2 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN SILVER COPPER
端子形式：	BALL
端子节距：	1 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40
宽度：	15 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：	1

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