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PCA9511A

Hot swappable I²C-bus and SMBus bus buffer

Rev. 01 — 15 August 2005

Product data sheet

1. General description

The PCA9511A is a hot swappable I²C-bus and SMBus buffer that allows I/O card

insertion into a live backplane without corrupting the data and clock buses. Control

circuitry prevents the backplane from being connected to the card until a stop command or

bus idle occurs on the backplane without bus contention on the card. When the

connection is made, the PCA9511A provides bidirectional buffering, keeping the

backplane and card capacitances isolated.

The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up

currents while still meeting rise time requirements. The PCA9511A incorporates a digital

ENABLE input pin, which enables the device when asserted HIGH and forces the device

into a low current mode when asserted LOW, and an open-drain READY output pin, which

indicates that the backplane and card sides are connected together (HIGH) or not (LOW).

During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize

the current required to charge the parasitic capacitance of the chip.

2. Features

■ Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and

SCL corruption during live board insertion and removal from multi-point backplane

systems

■ Compatible with I²C-bus standard mode, I²C-bus fast mode, and SMBus standards

■ Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.6 V threshold)

■ Active HIGH ENABLE input

■ Active HIGH READY open-drain output

■ High-impedance SDA and SCL pins for V_CC= 0 V

■ 1 V precharge on all SDA and SCL lines

■ Supporting clock stretching and multiple master arbitration/synchronization

■ Operating power supply voltage range: 2.7 V to 5.5 V

■ 0 kHz to 400 kHz clock frequency

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■ Packages offered: SO8, TSSOP8 (MSOP8)

3. Applications

■ cPCI, VME, AdvancedTCA cards and other multi-point backplane cards that are

required to be inserted or removed from an operating system

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

4. Feature selection

Table 1:

Feature

idle detect

Feature selection chart

PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A

yes

-

yes

-

yes

-

yes

-

high-impedance SDA, SCL pins for V_CC= 0 V

rise time accelerator circuitry on SDAn and SCLn lines

rise time accelerator circuitry hardware disable pin for

lightly loaded systems

-

rise time accelerator threshold 0.8 V versus 0.6 V

improves noise margin

-

yes

ready open-drain output

yes

-

yes

-

yes

-

yes

-

two V_CCpins to support 5 V to 3.3 V level translation with

improved noise margins

yes

1 V precharge on all SDA and SCL lines

in only

-

yes

-

yes

-

92 µA current source on SCLIN and SDAIN for PICMG

yes

applications

5. Ordering information

Table 2:

Ordering information

T_amb= −40 °C to +85 °C

Type number

Topside

mark

Package

Name

SO8

Description

plastic small outline package; 8 leads; body width 3.9 mm

Version

SOT96-1

PCA9511AD

PA9511A

PCA9511ADP 9511A

TSSOP8^[1]plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

[1] Also known as ‘MSOP8’.

Standard packing quantities and other packaging data are available at

www.standardics.philips.com/packaging/.

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

2 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

6. Block diagram

PCA9511A

2 mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

V

CC

BACKPLANE-TO-CARD

CONNECTION

SDAOUT

SDAIN

CONNECT

ENABLE

100 kΩ

RCH1

RCH3

1 VOLT

PRECHARGE

100 kΩ

RCH2

RCH4

2 mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

BACKPLANE-TO-CARD

CONNECTION

SCLOUT

SCLIN

CONNECT

0.55V

0.45V

/

CC

STOP BIT AND

BUS IDLE

0.5 µA

0.55V

/

CC

CONNECT

0.45V

CC

20 pF

READY

GND

UVLO

100 µs

DELAY

RD

ENABLE

QB

S

CONNECT

0.5 pF

002aab580

Fig 1. Block diagram of PCA9511A

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

3 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

7. Pinning information

7.1 Pinning

1

2

3

4

8

7

6

5

ENABLE

SCLOUT

SCLIN

V

CC

1

2

3

4

8

7

6

5

ENABLE

SCLOUT

SCLIN

V

CC

SDAOUT

SDAIN

SDAOUT

SDAIN

PCA9511AD

PCA9511ADP

GND

READY

GND

READY

002aab578

002aab577

Fig 2. Pin conﬁguration for SO8

Fig 3. Pin conﬁguration for TSSOP8

7.2 Pin description

Table 3:

Symbol

Pin description

Pin Description

ENABLE

1

Chip enable. Grounding this input puts the part in a low current (< 1 µA)

mode. It also disables the rise time accelerators, isolates SDAIN from

SDAOUT and isolates SCLIN from SCLOUT.

SCLOUT

SCLIN

GND

2

3

4

5

serial clock output to and from the SCL bus on the card

serial clock input to and from the SCL bus on the backplane

Ground. Connect this pin to a ground plane for best results.

READY

open-drain output which pulls LOW when SDAIN and SCLIN are

disconnected from SDAOUT and SCLOUT, and goes HIGH when the two

sides are connected

SDAIN

SDAOUT

V_CC

6

7

8

serial data input to and from the SDA bus on the backplane

serial data output to and from the SDA bus on the card

power supply

8. Functional description

Refer to Figure 1 “Block diagram of PCA9511A”.

8.1 Start-up

An undervoltage/initialization circuit holds the parts in a disconnected state which

presents high-impedance to all SDA and SCL pins during power-up. A LOW on the

ENABLE pin also forces the parts into the low current disconnected state when the I_CCis

essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is

powered and the ENABLE is taken from LOW to HIGH it enters an initialization state

where the internal references are stabilized and the precharge circuit is enabled. At the

end of the initialization state the ‘Stop Bit And Bus Idle’ detect circuit is enabled. With the

ENABLE pin HIGH long enough to complete the initialization state (t_en) and remaining

HIGH when all the SDA and SCL pins have been HIGH for the bus idle time or when all

pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is

connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

4 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

is activated during the initialization and is deactivated when the connection is made. The

precharge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 kΩ

nominal resistors. This precharges the pins to 1 V to minimize the worst case

disturbances that result from inserting a card into the backplane where the backplane and

the card are at opposite logic levels.

8.2 Connect circuitry

Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as

SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that

isolates the input capacitance from the output bus capacitance while communicating the

logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be

driven to a LOW by the part. The same is also true for the SCL pins. Noise between

0.7V_CCand V_CCis generally ignored because a falling edge is only recognized when it

falls below 0.7V_CCwith a slew rate of at least 1.25 V/µs. When a falling edge is seen on

one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small

voltage above the falling pin. The driver will pull the pin down at a slew rate determined by

the driver and the load initially, because it does not start until the ﬁrst falling pin is below

0.7V_CC. The ﬁrst falling pin may have a fast or slow slew rate, if it is faster than the pull

down slew rate then the initial pull-down rate will continue. If the ﬁrst falling pin has a slow

slew rate then the second pin will be pulled down at its initial slew rate only until it is just

above the ﬁrst pin voltage then they will both continue down at the slew rate of the ﬁrst.

Once both sides are LOW they will remain LOW until all the external drivers have stopped

driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV

by external drivers, which is the case for clock stretching and is typically the case for

acknowledge, and one side external driver stops driving that pin will rise until the internal

driver pulls it down to the offset voltage. When the last external driver stops driving a

LOW, that pin will rise up and settle out just above the other pin as both rise together with

a slew rate determined by the internal slew rate control and the RC time constant. As long

as the slew rate is at least 1.25 V/µs, when the pin voltage exceeds 0.6 V for the

PCA9511A, the rise time accelerator’s circuits are turned on and the pull-down driver is

turned off.

8.3 Maximum number of devices in series

Each buffer adds about 0.1 V dynamic level offset at 25 °C with the offset larger at higher

temperatures. Maximum offset (V_offset) is 0.150 V with a 10 kΩ pull-up resistor. The LOW

level at the signal origination end (master) is dependent upon the load and the only

speciﬁcation point is the I²C-bus speciﬁcation of 3 mA will produce V_OL< 0.4 V, although if

lightly loaded the V_OLmay be 0.1 V. Assuming V_OL= 0.1 V and V_offset= 0.1 V, the level

after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the

rising edge accelerator (about 0.6 V). With great care a system with four buffers may

work, but as the V_OLmoves up from 0.1 V, noise or bounces on the line will result in ﬁring

the rising edge accelerator thus introducing false clock edges. Generally it is

recommended to limit the number of buffers in series to two, and to keep the load light to

minimize the offset.

The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise

time accelerator can be turned off) are a little different with the rise time accelerator turned

off because the rise time accelerator will not pull the node up, but the same logic that turns

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

5 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

on the accelerator turns the pull-down off. If the V_ILis above 0.6 V and a rising edge is

detected, the pull-down will turn off and will not turn back on until a falling edge is

detected.

buffer A

buffer B

buffer C

MASTER

SLAVE B

common

node

SLAVE C

002aab581

Fig 4. System with 3 buffers connected to common node

Consider a system with three buffers connected to a common node and communication

between the Master and Slave B that are connected at either end of buffer A and buffer B

in series as shown in Figure 4. Consider if the V_OLat the input of buffer A is 0.3 V and the

V_OLof Slave B (when acknowledging) is 0.4 V with the direction changing from Master to

Slave B and then from Slave B to Master. Before the direction change you would observe

V_ILat the input of buffer A of 0.3 V and its output, the common node, is 0.4 V. The output

of buffer B and buffer C would be 0.5 V, but Slave B is driving 0.4 V, so the voltage at

Slave B is 0.4 V. The output of buffer C is 0.5 V. When the Master pull-down turns off, the

input of buffer A rises and so does its output, the common node, because it is the only part

driving the node. The common node will rise to 0.5 V before buffer B's output turns on, if

the pull-up is strong the node may bounce. If the bounce goes above the threshold for the

rising edge accelerator 0.6 V the accelerators on both buffer A and buffer C will ﬁre

contending with the output of buffer B. The node on the input of buffer A will go HIGH as

will the input node of buffer C. After the common node voltage is stable for a while the

rising edge accelerators will turn off and the common node will return to 0.5 V because

the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to

0.6 V until Slave B turned off. This would not cause a failure on the data line as long as

the return to 0.5 V on the common node ( 0.6 V at the Master and Slave C) occurred

before the data setup time. If this were the SCL line, the parts on buffer A and buffer C

would see a false clock rather than a stretched clock, which would cause a system error.

8.4 Propagation delays

The delay for a rising edge is determined by the combined pull-up current from the bus

resistors and the rise time accelerator current source and the effective capacitance on the

lines. If the pull-up currents are the same, any difference in rise time is directly

proportional to the difference in capacitance between the two sides. The t_PLHmay be

negative if the output capacitance is less than the input capacitance and would be positive

if the output capacitance is larger than the input capacitance, when the currents are the

same.

The t_PHLcan never be negative because the output does not start to fall until the input is

below 0.7V_CC, and the output turn on has a non-zero delay, and the output has a limited

maximum slew rate, and even if the input slew rate is slow enough that the output catches

up it will still lag the falling voltage of the input by the offset voltage. The maximum t_PHL

occurs when the input is driven LOW with zero delay and the output is still limited by its

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

6 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function

of the internal maximum slew rate which is a function of temperature, V_CCand process, as

well as the load current and the load capacitance.

8.5 Rise time accelerators

During positive bus transitions a 2 mA current source is switched on to quickly slew the

SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9511A is exceeded.

The rising edge rate should be at least 1.25 V/µs to guarantee turn on of the accelerators.

8.6 READY digital output

This pin provides a digital ﬂag which is LOW when either ENABLE is LOW or the start-up

sequence described earlier in this section has not been completed. READY goes HIGH

when ENABLE is HIGH and start-up is complete. The pin is driven by an open-drain

pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of

10 kΩ to V_CCto provide the pull-up.

8.7 ENABLE low current disable

Grounding the ENABLE pin disconnects the backplane side from the card side, disables

the rise-time accelerators, drives READY LOW, disables the bus precharge circuitry, and

puts the part in a low current state. When the pin voltage is driven all the way to V_CC, the

part waits for data transactions on both the backplane and card sides to be complete

before reconnecting the two sides.

8.8 Resistor pull-up value selection

The system pull-up resistors must be strong enough to provide a positive slew rate of

1.25 V/µs on the SDA and SCL pins, in order to activate the boost pull-up currents during

rising edges. Choose maximum resistor value using the formula:

V_CC(min)– 0.6

R ≤800 × 10³

-----------------------------------

C

where R is the pull-up resistor value in Ω, V_CC(min)is the minimum V_CCvoltage in volts,

and C is the equivalent bus capacitance in picofarads (pF).

In addition, regardless of the bus capacitance, always choose R ≤ 16 kΩ for V_CC= 5.5 V

maximum, R ≤ 24 kΩ for V_CC= 3.6 V maximum. The start-up circuitry requires logic HIGH

voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these

pull-up values are needed to overcome the precharge voltage. See the curves in Figure 5

and Figure 6 for guidance in resistor pull-up selection.

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

7 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

002aab582

002aab583

30

20

R

(kΩ)

PU

R

(kΩ)

PU

R

max

= 16 kΩ

R

max

= 24 kΩ

15

20

rise time > 300 ns

10

5

rise time > 300 ns

recommended

pull-up

10

recommended

pull-up

0

100

200

300

400

0

100

200

300

400

C

b

(pF)

C (pF)

b

Fig 5. Bus requirements for 3.3 V systems

Fig 6. Bus requirements for 5 V systems

8.9 Hot swapping and capacitance buffering application

Figure 7 through Figure 10 illustrate the usage of the PCA9511A in applications that take

advantage of both its hot swapping and capacitance buffering features. In all of these

applications, note that if the I/O cards were plugged directly into the backplane, all of the

backplane and card capacitances would add directly together, making rise time and

fall time requirements difﬁcult to meet. Placing a bus buffer on the edge of each card,

however, isolates the card capacitance from the backplane. For a given I/O card, the

PCA9511A drives the capacitance of everything on the card and the backplane must drive

only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and

all additional cards on the backplane.

See Application Note AN10160, ‘Hot Swap Bus Buffer’ for more information on

applications and technical assistance.

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

8 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

POWER SUPPLY

HOT SWAP

V

CC

R1

10 kΩ

R2

10 kΩ

R3

R4

R5

R6

0.01 µF

10 kΩ

V

CC

BD_SEL

SDA

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

CARD1_SDA

CARD1_SCL

SCL

GND

I/O PERIPHERAL CARD 2

C3

POWER SUPPLY

HOT SWAP

R7

R8

R9

10 kΩ

R10

10 kΩ

0.01 µF

10 kΩ

V

CC

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

CARD2_SDA

CARD2_SCL

GND

I/O PERIPHERAL CARD N

C5

POWER SUPPLY

HOT SWAP

R11

R12

R13

10 kΩ

R14

10 kΩ

0.01 µF

10 kΩ

V

CC

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

CARDN_SDA

CARDN_SCL

GND

002aab584

Remark: The PCA9511A can be used in any combination depending on the number of rise time accelerators that are

needed by the system. Normally only one PCA9511A would be required per bus.

Fig 7. Hot swapping multiple I/O cards into a backplane using the PCA9511A in a cPCI, VME, and AdvancedTCA

system

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

9 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

V

CC

R1

10 kΩ

R2

10 kΩ

R4

R5

R6

0.01 µF

10 kΩ

V

CC

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

CARD1_SDA

CARD1_SCL

SDA

SCL

C2

GND

0.01 µF

I/O PERIPHERAL CARD 2

C3

R8

R9

10 kΩ

R10

10 kΩ

0.01 µF

10 kΩ

V

CC

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

CARD2_SDA

CARD2_SCL

C4

0.01 µF

GND

002aab585

Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9511A in a PCI system

2

I C-bus System 1

I C-bus System 2

V

= 5 V

V

CC

R2

1 kΩ

C1

0.01 µF

C2

0.01 µF

R1

10 kΩ

R4

10 kΩ

R5

R6

R7

10 kΩ

R8

10 kΩ

R3

1 kΩ

V

CC

V

CC

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

SDAOUT

SCLOUT

READY

ENABLE

SDAIN

SCLIN

SDA1

SCL1

SDA1

SCL1

to other

System 1

devices

to other

System 2

devices

GND

long

distance

bus

002aab586

Remark: See Application Note AN255, ‘I2C repeaters, hubs, and expanders’ for more information on other devices better

optimized for long distance transmission of the I²C-bus or SMBus.

Fig 9. Repeater/bus extender application using the PCA9511A

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

10 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

R

drop

V

CC_LOW

V

CC

C2

0.01 µF

R1

R4

R2

R3

R5

10 kΩ

1 kΩ

10 kΩ

V

CC

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

SDA2

SCL2

SDA

SCL

GND

002aab587

V_CC> V_{CC_LOW}

R_dropis the line loss of V_CCin the backplane.

Fig 10. System with disparate V_CCvoltages

9. Application design-in information

V

CC

C1

0.01 µF

(2.7 V to 5.5 V)

R1

R2

R5

10 kΩ

R3

10 kΩ

R4

10 kΩ

8

3

2

7

5

SCLIN

SCLOUT

SDAOUT

6

SDAIN

1

ENABLE

READY

GND

4

002aab579

Fig 11. Typical application

10. Limiting values

Table 4:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

+7

Unit

V

[1]

V_CC

V_n

supply voltage

−0.5

voltage on SDAIN, SCLIN, SDAOUT,

SCLOUT, READY, ENABLE

+7

V

T_oper

T_stg

operating temperature

−40

+85

°C

storage temperature

−65

+150

+300

+125

T_sp

solder point temperature

maximum junction temperature

10 s max.

-

T_j(max)

[1] Voltages with respect to pin GND.

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

11 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

11. Characteristics

Table 5:

Characteristics

V_CC= 2.7 V to 5.5 V; T_amb= −40 °C to +85 V; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Power supply

[1]

V_CC

I_CC

supply voltage

supply current

2.7

-

5.5

6

V

V_CC= 5.5 V;

3.5

mA

V

_SDAIN= V_SCLIN= 0 V

Shut-down mode supply V_ENABLE= 0 V; all other pins at

current _CCor GND

Start-up circuitry

I_CC(sd)

-

0.1

-

µA

V

[1]

V_pch

precharge voltage

SDA, SCL ﬂoating

0.8

-

1.1

1.2

V

V_IH(ENABLE)HIGH-state input voltage

on pin ENABLE

0.5 × V_CC0.7 × V_CC

V_IL(ENABLE)LOW-state input voltage

on pin ENABLE

0.3 × V_CC

0.5 × V_CC

±0.1

-

V

I_I(ENABLE)

input current on pin

ENABLE

V_ENABLE= 0 V to V_CC

-

±1

µA

[2]

[1]

t_en

enable time

-

110

105

-

µs

t_idle(READY)bus idle time to READY

active

50

200

t_dis(EN-RDY)disable time (ENABLE to

READY)

-

30

-

ns

µs

µA

pF

V

[3]

t_stp(READY)SDAIN to READY delay

after STOP

1.2

0.8

±0.3

1.9

2.5

-

t_READY

SCLOUT/SDAOUT to

READY

-

I_LZ(READY)off-state leakage current V_ENABLE= V_CC

on pin READY

-

[4]

[1]

C_i(ENABLE)input capacitance on pin V_I= V_CCor GND

ENABLE

4.0

0.4

C_o(READY)output capacitance on

pin READY

V_I= V_CCor GND

V_OL(READY)LOW-state output

voltage on pin READY

I_pu= 3 mA; V_ENABLE= V_CC

Rise time accelerators

[5]

I_trt(pu)

transient boosted pull-up positive transition on SDA, SCL;

current _CC= 2.7 V;

slew rate = 1.25 V/µs

1

2

-

mA

V

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

12 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

Table 5:

Characteristics …continued

V_CC= 2.7 V to 5.5 V; T_amb= −40 °C to +85 V; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input-output connection

[1] [6]

[8]

V_offset

t_PLH

offset voltage

LOW-to-HIGH

10 kΩ to V_CCon SDA, SCL;

0

-

110

0

175

-

mV

ns

V_CC= 3.3 V

10 kΩ to V_CC

;

propagation delay (SCL C_L= 100 pF each side

to SCL and SDA to SDA)

t_PHL

HIGH-to-LOW

10 kΩ to V_CC

;

-

70

-

ns

propagation delay (SCL C_L= 100 pF each side

to SCL and SDA to SDA)

[4]

[1]

C_i(SCL/SDA)SCL and SDA input

capacitance

-

5

-

7

pF

V

V_OL

LOW-state output

voltage

V_I= 0 V; SDAn, SCLn pins;

_sink= 3 mA; V_CC= 2.7 V

0

0.4

+1

I

I_LI

input leakage current

SDAn, SCLn pins; V_CC= 5.5 V

−1

-

µA

System characteristics

f_SCLSCL clock frequency

t_BUF

[4]

0

-

400

-

kHz

bus free time between

STOP and START

condition

1.3

µs

[4]

t_HD;STA

t_SU;STA

t_SU;STO

START condition hold

time

0.6

-

µs

START condition set-up

time

STOP condition set-up

time

[4]

t_HD;DAT

t_SU;DAT

t_LOW

t_HIGH

t_f

data hold time

300

-

ns

µs

ns

data setup time

100

-

[4]

SCL LOW time

1.3

-

[4]

SCL HIGH time

0.6

-

[4] [7]

fall time SDA and SCL

rise time SDA and SCL

20 + 0.1 × C_b

300

t_r

[1] This speciﬁcation applies over the full operating temperature range.

[2] The enable time can slow considerably for some parts when temperature is < −20 °C.

[3] Delays that can occur after ENABLE and/or idle times have passed.

[4] Guaranteed by design, not production tested.

[5] I_trt(pu)varies with temperature and V_CCvoltage, as shown in Section 11.1 “Typical performance characteristics”.

[6] The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function

of the pull-up resistor and V_CCvoltage is shown in Section 11.1 “Typical performance characteristics”.

[7] C_b= total capacitance of one bus line in pF.

[8] Force V_SDAIN= V_SCLIN= 0.1 V, tie SDAOUT and SCLOUT through 10 kΩ resistor to V_CCand measure the SDAOUT and SCLOUT

output.

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PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

11.1 Typical performance characteristics

002aab588

002aab590

3.7

12

V

= 5.5 V

CC

I

trt(pu)

CC

(mA)

3.3 V

2.7 V

V

= 5 V

CC

3.3

8

4

0

2.9

3.0 V

2.7 V

2.5

−40

+25

+90

−40

+25

+90

T

(°C)

T

(°C)

amb

Fig 12. I_CCversus temperature

Fig 13. I_trt(pu)versus temperature

002aab589

002aab591

90

300

V

= 5.5 V

V

= 5 V

CC

t

V − V

O I

PHL

(ns)

(mV)

80

200

100

0

2.7 V

3.3 V

70

3.3 V

60

−40

+25

+90

0

10000

20000

30000

40000

(Ω)

T

(°C)

R

PU

amb

C_i= C_o> 100 pF; R_PU(in)= R_PU(out)= 10 kΩ

Fig 14. Input/output t_PHLversus temperature

Fig 15. Connection circuitry V_O− V_I

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PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

11.2 Timing diagrams

SDAn/SCLn

t

en

ENABLE

READY

t

dis

t

idle(READY)

002aab592

Fig 16. Timing for t_en, t_idle(READY), and t_dis

SDAIN

SCLIN

SCLOUT

SDAOUT

t

en

ENABLE

READY

t

stp(READY)

002aab593

t_stp(READY)is only applicable after the t_endelay.

Fig 17. t_stp(READY)that can occur after t_en

SCLIN, SDAIN

SCLOUT, SDAOUT

t

en

idle(READY)

t

ENABLE

t

stp(READY)

READY

002aab594

t_stp(READY)is only applicable after the t_endelay.

Fig 18. t_stp(READY)delay that can occur after t_enand t_idle(READY)

9397 750 13269

Product data sheet

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PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

12. Test information

V

CC

V

R

10 kΩ

CC

L

V

O

I

PULSE

D.U.T.

GENERATOR

C

L

R

T

100 pF

002aab595

R_L= load resistor

C_L= load capacitance includes jig and probe capacitance

R_T= termination resistance should be equal to the output impedance Z₀of the pulse generators.

Fig 19. Test circuitry for switching times

9397 750 13269

Product data sheet

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PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

13. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

v

c

y

H

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

w

M

detail X

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 20. Package outline SOT96-1 (SO8)

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Product data sheet

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PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT505-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

4

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.05

0.95

0.80

0.45

0.25

0.28

0.15

3.1

2.9

3.1

2.9

5.1

4.7

0.7

0.4

0.70

0.35

6°

0°

mm

1.1

0.65

0.25

0.94

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-04-09

03-02-18

SOT505-1

Fig 21. Package outline SOT505-1 (TSSOP8)

9397 750 13269

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PCA9511A

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Hot swappable I²C-bus and SMBus bus buffer

14. Soldering

14.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

14.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

14.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

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PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

14.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

14.5 Package related soldering information

Table 6:

Package ^[1]

Suitability of surface mount IC packages for wave and reﬂow soldering methods

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

9397 750 13269

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Rev. 01 — 15 August 2005

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PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

15. Abbreviations

Table 7:

Acronym

Abbreviations

Description

AdvancedTCA

CDM

Advanced Telecommunications Computing Architecture

Charged Device Model

cPCI

compact Peripheral Component Interface

Electrostatic Discharge

ESD

HBM

Human Body Model

I²C-bus

Inter IC bus

MM

Machine Model

PCI

Peripheral Component Interface

PCI Industrial Computer Manufacturers Group

System Management Bus

VERSAModule Eurocard

PICMG

SMBus

VME

16. Revision history

Table 8:

Revision history

Document ID

PCA9511A_1

Release date Data sheet status

20050815 Product data sheet

Change notice Doc. number

9397 750 13269

Supersedes

-

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

21 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

17. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

18. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

20. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — wordmark and logo are trademarks of Koninklijke Philips

Electronics N.V.

19. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

21. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 13269

Product data sheet

Rev. 01 — 15 August 2005

22 of 23

PCA9511A

Philips Semiconductors

Hot swappable I²C-bus and SMBus bus buffer

22. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8

Functional description . . . . . . . . . . . . . . . . . . . 4

Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connect circuitry. . . . . . . . . . . . . . . . . . . . . . . . 5

Maximum number of devices in series . . . . . . . 5

Propagation delays. . . . . . . . . . . . . . . . . . . . . . 6

Rise time accelerators . . . . . . . . . . . . . . . . . . . 7

READY digital output . . . . . . . . . . . . . . . . . . . . 7

ENABLE low current disable. . . . . . . . . . . . . . . 7

Resistor pull-up value selection . . . . . . . . . . . . 7

Hot swapping and capacitance buffering

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

9

Application design-in information . . . . . . . . . 11

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11

10

11

11.1

11.2

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 12

Typical performance characteristics . . . . . . . . 14

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 15

12

Test information. . . . . . . . . . . . . . . . . . . . . . . . 16

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

13

14

14.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 19

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 20

Package related soldering information . . . . . . 20

14.2

14.3

14.4

14.5

15

16

17

18

19

20

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Contact information . . . . . . . . . . . . . . . . . . . . 22

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 15 August 2005

Document number: 9397 750 13269

Published in The Netherlands

型号:	PCA9511ADP
是否Rohs认证：	符合
生命周期：	Transferred
包装说明：	TSSOP, TSSOP8,.19
Reach Compliance Code：	unknown
风险等级：	5.64
接口集成电路类型：	INTERFACE CIRCUIT
JESD-30 代码：	R-PDSO-G8
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP8,.19
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3/5 V
认证状态：	Not Qualified
子类别：	Other Interface ICs
最大压摆率：	6 mA
表面贴装：	YES
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子节距：	0.635 mm
端子位置：	DUAL
Base Number Matches：	1

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