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PCA9536

REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

WITH CONFIGURATION REGISTERS

www.ti.com

SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

FEATURES

•

Available in the Texas Instruments

NanoFree™ Package

•

No Glitch on Power Up

Power-Up With All Channels Configured as

Inputs

•

Low Standby Current Consumption of

1 µA Max

I²C to Parallel Port Expander

•

Noise Filter on SCL/SDA Inputs

•

Latched Outputs With High-Current Drive

Operating Power-Supply Voltage Range of

2.3 V to 5.5 V

Maximum Capability for Directly Driving LEDs

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

5-V Tolerant I/O Ports

400-kHz Fast I²C Bus

ESD Protection Exceeds JESD 22

Input/Output Configuration Register

Polarity Inversion Register

Internal Power-On Reset

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

1000-V Charged-Device Model (C101)

D PACKAGE

(TOP VIEW)

DGK PACKAGE

(TOP VIEW)

DCU PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

4 5

GND

P2

P3

IO0

IO1

IO2

GND

1

2

3

4

8

7

6

5

V_CC

SDA

SCL

IO3

V_CC

1

2

3

4

8

7

6

5

P0

P1

3 6

2 7

1 8

SCL

SDA

V_CC

1

8

7

P0

P1

P2

P1

SDA

SCL

P3

P0

P2

2

3

4

SDA

GND

6

5

SCL

P3

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

ORDERING INFORMATION

TOP-SIDE

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

MARKING⁽²⁾

NanoFree™ – WCSP (DSBGA)

Reel of 3000

Reel of 2500

PCA9536YZPR

PREVIEW

0.23-mm Large Bump – YZP (Pb-free)

SOIC – D

PCA9536DR

PCA9536DRG4

PCA9536D

PD536

Tube of 75

–40°C to 85°C

PCA9536DG4

PCA9536DT

Reel of 250

VSSOP – DCU

VSSOP – DGK

Reel of 3000

PCA9536DCUR

PCA9536DGKR

PCA9536DGKRG4

PREVIEW

7C_

Reel of 2500

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCU/DGK: The actual top-side marking has one additional character that designates the assembly/test site.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCA9536

REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

WITH CONFIGURATION REGISTERS

www.ti.com

SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

This 4-bit I/O expander for the two-line bidirectional bus (I²C) is designed for 2.3-V to 5.5-V V_CCoperation. It

provides general-purpose remote I/O expansion for most microcontroller families via the I²C interface [serial

clock (SCL), serial data (SDA)].

The PCA9536 features 4-bit Configuration (input or output selection), Input Port, Output Port, and Polarity

Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs with a weak pullup

to V_CC. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O

configuration bits. If no signals are applied externally to the PCA9536, the voltage level is 1, or high, because of

the internal pullup resistors. The data for each input or output is stored in the corresponding Input Port or Output

Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All

registers can be read by the system master.

The system master can reset the PCA9536 in the event of a timeout or other improper operation by utilizing the

power-on reset feature, which puts the registers in their default state and initializes the I²C/SMBus state

machine.

The device's outputs (latched) have high-current drive capability for directly driving LEDs. It has low current

consumption.

TERMINAL FUNCTIONS

NO.

NAME

DESCRIPTION

D, DGK, AND

YZP PACKAGE

DCU PACKAGE

1

2

3

4

5

6

7

8

4

3

2

1

8

7

6

5

P0

P1

P-port input/output. Push-pull design structure.

Ground

P2

GND

P3

P-port input/output. Push-pull design structure.

Serial clock bus. Connect to V_CCthrough a pullup resistor.

Serial data bus. Connect to V_CCthrough a pullup resistor.

Supply voltage

SCL

SDA

V_CC

2

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PCA9536

REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

LOGIC DIAGRAM

6

SCL

SDA

2

I/O

Port

Input

Filter

I C Bus

4 Bits

P3−P0

Shift

Register

7

Control

Write Pulse

Read Pulse

8

4

Power-On

Reset

V

CC

GND

A. All I/Os are set to inputs at reset.

SIMPLIFIED SCHEMATIC OF P0 TO P3

Data From

Shift Register

Configuration

Output Port

Register Data

Register

V

CC

Data From

Shift Register

Q1

D

Q

FF

K

100 kW

Write Configuration

Pulse

D

C

Q

C

Q

FF

K

P0 to P3

Write Pulse

ESD Protection

Diode

Q2

Output Port

Register

Input Port

Register

GND

Input Port

Register Data

D

Q

FF

K

Read Pulse

C

Q

Data From

Shift Register

Polarity

Register Data

D

C

Q

FF

K

Write Polarity

Pulse

Polarity

Inversion

Register

A. At power-on reset, all registers return to default values.

3

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PCA9536

REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

WITH CONFIGURATION REGISTERS

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak

pullup (100 kΩ typ) to V_CC. The input voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In

this case, there are low-impedance paths between the I/O pin and either V_CCor GND. The external voltage

applied to this I/O pin should not exceed the recommended levels for proper operation.

I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address

byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 2).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)

after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line

high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

SDA

SCL

S

P

Start Condition

Stop Condition

Figure 1. Definition of Start and Stop Conditions

4

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PCA9536

REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

WITH CONFIGURATION REGISTERS

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 2. Bit Transfer

Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

Master

1

2

8

9

S

Start

Clock Pulse for

Condition

Acknowledgment

Figure 3. Acknowledgment on the I²C Bus

Interface Definition

BIT

BYTE

7 (MSB)

6

5

4

3

2

1

0 (LSB)

I²C slave address

Px I/O data bus

H

L

H

R/W

Does not affect operation of the PCA9536

P6 P5

P3

P2

P1

P0

P7

P4

Device Address

Figure 4 shows the address byte of the PCA9536.

Slave Address

1

0

1

R/W

Fixed

Figure 4. PCA9536 Address

5

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REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

WITH CONFIGURATION REGISTERS

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

The slave address equates to 65 (decimal) and 41 (hexadecimal).

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read

is selected, while a low (0) selects a write operation.

Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is

stored in the control register in the PCA9536. Two bits of this data byte state the operation (read or write) and

the internal register (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be

written or read through the I²C bus. The command byte is sent only during a write transmission.

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until

a new command byte has been sent.

0

B1 B0

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND BYTE

(HEX)

POWER-UP

DEFAULT

REGISTER

PROTOCOL

B1

0

B0

0

0x00

0x01

0x02

0x03

Input Port

Output Port

Read byte

1111 XXXX

1111 1111

0000 0000

1111 1111

0

1

Read/write byte

1

0

Polarity Inversion

Configuration

1

6

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REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is

defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these

registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to instruct the I²C device that the

Input Port register will be accessed next.

Register 0 (Input Port Register)

I7

1

I6

I5

I4

BIT

I3

X

I2

X

I1

X

I0

X

Not Used

DEFAULT

1

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Register 1 (Output Port Register)

O7

1

O6

O5

O4

BIT

O3

1

O2

1

O1

1

O0

1

Not Used

DEFAULT

1

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration

register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in

this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Register 2 (Polarity Inversion Register)

N7

N6

N5

N4

BIT

N3

0

N2

0

N1

0

N0

0

Not Used

DEFAULT

0

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,

the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is

cleared to 0, the corresponding port pin is enabled as an output.

Register 3 (Configuration Register)

C7

1

C6

C5

C4

BIT

C3

1

C2

1

C1

1

C0

1

Not Used

DEFAULT

1

Power-On Reset

When power (from 0 V) is applied to V_CC, an internal power-on reset holds the PCA9536 in a reset condition

until V_CChas reached V_POR. At that time, the reset condition is released and the PCA9536 registers and

I²C/SMBus state machine initialize to their default states. After that, V_CCmust be lowered to below 0.2 V and

then back up to the operating voltage for a power-reset cycle.

7

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REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

Bus Transactions

Data is exchanged between the master and PCA9536 through write and read commands.

Writes

Data is transmitted to the PCA9536 by sending the device address and setting the least-significant bit (LSB) to a

logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which

register receives the data that follows the command byte. There is no limitation on the number of data bytes sent

in one write transmission (see Figure 6 and Figure 7).

SCL

1

2

3

4

5

6

7

8

9

Slave Address

Command Byte

Data to Port

Data 1

S

1

0

1

0

A

0

1

A

P

SDA

ACK From Slave

R/W ACK From Slave

Start Condition

Write to Port

Data Out

From Port

Data 1 Valid

t

pv

Figure 6. Write to Output Port Register

<br/>

SCL

1

2

3

4

5

6

7

1

8

0

9

Slave Address

Command Byte

Data to Register

Data

SDA

S

1

0

A

0

1

A

P

Start Condition

R/W ACK From Slave

ACK From Slave

Data to

Register

Figure 7. Write to Configuration or Polarity Inversion Registers

8

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

Reads

The bus master first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 4 for device

address). The command byte is sent after the address and determines which register is accessed. After a

restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined

by the command byte then is sent by the PCA9536 (see Figure 8 and Figure 9). After a restart, the value of the

register defined by the command byte matches the register being accessed when the restart occurred. Data is

clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data

bytes received in one read transmission, but when the final byte is received, the bus master must not

acknowledge the data.

ACK From

Master

ACK From

Slave

ACK From

Slave

ACK From

Slave

Data from Register

Data

Slave Address

Command Byte

A

S

A

1

0

1

A

S

1

0

1

0

A

R/W

At this time, the master-transmitter

becomes master-receiver and

slave-receiver becomes

R/W

slave-transmitter

Data from Register

NACK From Master

Data

P

NA

Last Byte

Figure 8. Read From Register

<br/>

1

2

3

4

5

6

7

8

9

SCL

SDA

Data From Port

Data 1

Slave Address

Data From Port

Data 4

S

1

0

1

0

A

P

NA

A

Start

Condition

NACK From

Master

ACK From

Slave

ACK From

Master

Stop

Condition

R/W

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

t

ph

t

ps

A. This figure assumes that the command byte previously has been programmed with 00h.

B. Transfer of data can be stopped at any moment by a Stop condition.

C. This figure eliminates the command byte transfer, a restart, and the slave address call between the initial slave

address call and actual data transfer from the P-port (see Figure 8).

Figure 9. Read Input Port Register

9

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

UNIT

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Output voltage range⁽²⁾

6

V

6

V

V_O

I_IK

V

Input clamp current

V_I< 0

–20

±20

50

mA

I_OK

I_IOK

I_OL

I_OH

Output clamp current

V_O< 0

Input/output clamp current

Continuous output low current

Continuous output high current

Continuous current through GND

Continuous current through V_CC

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

–50

–200

160

97

I_CC

mA

D package

DCU package

DGK package

YZP package

227

172

102

150

θ_JA

Package thermal impedance⁽³⁾

°C/W

°C

T_stg

Storage temperature range

–65

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions

MIN

2.3

MAX

5.5

UNIT

V_CC

V_IH

Supply voltage

V

SCL, SDA

P3–P0

0.7 × V_CC

2

5.5

High-level input voltage

V

5.5

SCL, SDA

P3–P0

–0.5 0.3 × V_CC

V_IL

Low-level input voltage

–0.5

0.8

–10

25

I_OH

I_OL

T_A

High-level output current

Low-level output current

Operating free-air temperature

P3–P0

mA

°C

P3–P0

–40

85

10

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_I= –18 mA

V_CC

2.3 V to 5.5 V

V_POR

MIN

TYP⁽¹⁾

MAX UNIT

V_IK

Input diode clamp voltage

–1.2

V

V_PORPower-on reset voltage

V_I= V_CCor GND, I_O= 0

1.5

1.65

V

2.3 V

1.8

2.6

4.1

1.7

2.5

4

3 V

I_OH= –8 mA

4.5 V

4.75 V

2.3 V

P-port high-level

V_OH

V

output voltage⁽²⁾

3 V

I_OH= –10 mA

V_OL= 0.4 V

V_OL= 0.5 V

4.5 V

4.75 V

2.3 V to 5.5 V

2.3 V

4

SDA

3

10

14

17

32

13

19

24

44

8

3 V

8

4.5 V

8

I_OL

4.75 V

2.3 V

8

mA

P-port⁽³⁾

10

3 V

V_OL= 0.7 V

4.5 V

4.75 V

2.3 V to 5.5 V

5.5 V

I_I

SCL, SDA

P-port

V_I= V_CCor GND

V_I= V_CC

±1

1

µA

I_IH

I_IL

P-port

V_I= GND

–100

150

50

73

9

V_I= V_CC, I_O= 0,

I/O = inputs, f_scl= 400 kHz

3.6 V

2.7 V

7

30

Operating mode

5.5 V

14

25

V_I= V_CC, I_O= 0,

I/O = inputs, f_scl= 100 kHz

3.6 V

9

20

2.7 V

6

15

I_CC

µA

5.5 V

225

175

125

0.25

0.2

0.1

350

250

200

1

V_I= GND, I_O= 0,

I/O = inputs, f_scl= 0 kHz

3.6 V

2.7 V

Standby mode

5.5 V

V_I= V_CC, I_O= 0,

I/O = inputs, f_scl= 0 kHz

3.6 V

0.9

0.8

2.7 V

One input at V_CC– 0.6 V,

Other inputs at V_CCor GND

2.3 V to 5.5 V

0.35

0.4

Additional current in

standby mode

∆I_CC

mA

Every LED I/O at V_I= 4.3 V,

f_scl= 0 kHz

5.5 V

C_I

SCL

V_I= V_CCor GND

2.3 V to 5.5 V

4

5

6.5

9.5

pF

SDA

P-port

C_io

V_IO= V_CCor GND

2.3 V to 5.5 V

7.5

(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V_CC) and T_A= 25°C.

(2) The total current sourced by all I/Os must be limited to 85 mA.

(3) Each I/O must be limited externally to a maximum of 25 mA, and the P-port (P3–P0) must be limited to a maximum current of 100 mA.

11

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I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)

STANDARD MODE

I²C BUS

FAST MODE

I²C BUS

UNIT

MIN

0

MAX

MIN

0

MAX

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

100

400 kHz

4

0.6

1.3

µs

4.7

50

ns

µs

t_sds

t_sdh

t_icr

250

0

100

0

(1)

1000 20 + 0.1C_b

300 20 + 0.1C_b

300

(1)

t_icf

I²C input fall time

t_ocf

t_buf

t_sts

t_sth

t_sps

I²C output fall time, 10-pF to 400-pF bus

I²C bus free time between Stop and Start

I²C Start or repeated Start condition setup time

I²C Start or repeated Start condition hold time

I²C Stop condition setup time

4.7

4

1.3

0.6

4

t_vd(data)Valid data time, SCL low to SDA output valid

1

0.9

Valid data time of ACK condition, ACK signal from SCL low to SDA

(out) low

t_vd(ack)

µs

C_b

I²C bus capacitive load

400

pF

(1) C_b= Total capacitive load of one bus in pF

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12)

STANDARD MODE

FAST MODE

I²C BUS

MIN

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

Output data valid

UNIT

MAX

MIN

MAX

200

t_pv

t_ps

t_ph

SCL

P3–P0

SCL

200

ns

µs

Input data setup time

Input data hold time

P-port

100

1

100

1

SCL

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TYPICAL CHARACTERISTICS

T_A= 25°C (unless otherwise noted)

SUPPLY CURRENT

vs

TEMPERATURE

QUIESCENT SUPPLY CURRENT

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

vs

TEMPERATURE

55

50

300

70

60

50

40

30

20

10

0

f_SCL= 400 kHz

I/Os unloaded

V_CC= 5 V

45

250

40

35

30

25

f_SCL= 400 kHz

I/Os unloaded

200

V_CC= 3.3 V

150

V_CC= 3.3 V

V_CC= 2.5 V

20

15

10

5

V_CC= 2.5 V

100

50

SCL = V_CC

0

-50

-25

0

25

50

75

100

-25

0

25

50

75

100

2.3

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

T_A– Free-Air Temperature – °C

V_CC– Supply Voltage – V

SUPPLY CURRENT

vs

NUMBER OF I/Os HELD LOW

I/O OUTPUT LOW VOLTAGE

I/O OUTPUT HIGH VOLTAGE

vs

TEMPERATURE

300

275

250

225

200

175

150

125

100

75

300

275

250

225

200

175

150

125

100

75

300

275

250

225

200

175

150

125

100

75

V_CC= 2.5 V, I_SINK= 10 mA

V_CC= 5 V

V_CC= 2.5 V, I_OL= 10 mA

T_A= –40°C

V_CC= 5 V, I_SINK= 10 mA

V_CC= 5 V, I_OL= 10 mA

T_A= 25°C

T_A= 85°C

V_CC= 2.5 V, I_SINK= 1 mA

V_CC= 5 V, I_SINK= 1 mA

50

25

0

-50

-25

0

25

50

75

100

0

1

2

3

4

-50

-25

0

25

50

75

100

T_A– Free-Air Temperature – °C

Number of I/Os Held Low

T_A– Free-Air Temperature – °C

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

30

25

20

15

10

5

60

55

50

45

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

V_CC= 5 V

V_CC= 3.3 V

V_CC= 2.5 V

T_A= –40°C

T_A= 25°C

T_A= –40°C

T_A= 25°C

T_A= 85°C

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_OL– Output Low Voltage – V

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TYPICAL CHARACTERISTICS (continued)

T_A= 25°C (unless otherwise noted)

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

30

70

65

60

55

50

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

V_CC= 5 V

V_CC= 3.3 V

V_CC= 2.5 V

25

T_A= –40°C

20

T_A= –40°C

T_A= 25°C

15

T_A= 25°C

T_A= 85°C

10

T_A= 85°C

5

0

T_A= 85°C

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

(V_CC– V_OH) – Output High Voltage – V

OUTPUT HIGH VOLTAGE

vs

SUPPLY VOLTAGE

6

5

4

3

2

1

0

T_A= 25°C

I_OH= –8 mA

I_OH= –10 mA

2.3

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

V_CC– Supply Voltage – V

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PARAMETER MEASUREMENT INFORMATION

V

CC

R

L

= 1 kΩ

SDA

DUT

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop

Start

Address

Bit 7

(MSB)

R/W

Bit 0

(LSB)

Data

Bit 7

(MSB)

Data

Bit 0 Condition

(LSB)

Stop

Address

Bit 6

Address

Bit 1

ACK

(A)

Condition Condition

(P) (S)

(P)

t

scl

t

sch

0.7 × V

0.3 × V

CC

SCL

SDA

CC

t

icr

t

sts

t

PHL

t

icf

t

buf

t

sp

PLH

0.7 × V

0.3 × V

CC

t

icf

t

icr

t

sdh

t

sps

t

sth

t

sds

Repeat

Start

Condition

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

1

DESCRIPTION

2

I C address

2, 3

P-port data

A. C_Linclude probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 10. I²C Interface Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

V

CC

R

L

= 4.7 kΩ

INT

DUT

C

L

= 100 pF

(see Note A)

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

From Slave

Start

Condition

8 Bits

(One Data Byte)

From Port

R/W

Slave Address

Data From Port

Data 2

S

1

0

1

A

Data 1

A

1

P

1

2

3

4

5

6

7

8

A

t

ir

B

t

ir

INT

A

t

iv

t

sps

A

Data

Into

Port

Address

Data 1

Data 2

0.7 × V

0.3 × V

CC

0.7 × V

0.3 × V

CC

SCL

INT

R/W

A

CC

t

iv

t

ir

0.7 × V

0.3 × V

0.7 × V

0.3 × V

CC

INT

P

n

CC

View A−A

A. C_Linclude probe and jig capacitance.

View B−B

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 11. Interrupt Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

Pn

500 W

DUT

2 × V

CC

C

= 50 pF

L

500 W

(see Note A)

P-PORT LOAD CONFIGURATION

0.7 × V

CC

SCL

SDA

P0

A

P3

0.3 × V

CC

Slave

ACK

t

pv

(see Note B)

P

n

Last Stable Bit

Unstable

Data

WRITE MODE (R/W = 0)

0.7 × V

0.3 × V

CC

SCL

P0

A

P3

CC

t

ph

t

ps

0.7 × V

0.3 × V

CC

P

n

CC

READ MODE (R/W = 1)

A. C_Linclude probe and jig capacitance.

B. t_pvis measured from 0.7 × V_CCon SCL to 50% I/O (Pn) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 12. P-Port Load Circuit and Voltage Waveforms

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SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

PARAMETER MEASUREMENT INFORMATION (continued)

V

CC

Pn

500 W

R

L

= 1 kΩ

DUT

2 × V

CC

SDA

DUT

C

L

= 50 pF

500 W

(see Note A)

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

P-PORT LOAD CONFIGURATION

Start

SCL

ACK or Read Cycle

SDA

0.3 y V

CC

t

RESET

V /2

CC

t

REC

t

w

Px

V /2

CC

(see Note D)

t

RESET

A. C_Linclude probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. I/Os are configured as inputs.

E. All parameters and waveforms are not applicable to all devices.

Figure 13. Reset Load Circuits and Voltage Waveforms

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APPLICATION INFORMATION

Figure 14 shows an application in which the PCA9536 can be used.

V

CC

2 kW

10 kW

V

CC

V

CC

Subsystem 1

(e.g., temperature

sensor)

SCL

SDA

P0

Master

Controller

SDA

INT

P1

P2

PCA9536

RESET

GND

P3

Subsystem 2

(e.g., counter)

A

B

GND

Controlled Device

(e.g., CBT device)

ENABLE

A. Device address is 10000001.

B. P0, P2, and P3 are configured as outputs.

C. P1 is configured as an input.

Figure 14. Typical Application

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APPLICATION INFORMATION (continued)

Minimizing I_CCWhen I/Os Control LEDs

When the I/Os are used to control LEDs, they are normally connected to V_CCthrough a resistor as shown in

Figure 14. The LED acts as a diode so, when the LED is off, the I/O V_INis about 1.2 V less than V_CC. The supply

current, I_CC, increases as V_INbecomes lower than V_CCand is specified as ∆I_CCin Electrical Characteristics.

Designs needing to minimize current consumption, such as battery power applications, should consider

maintaining the I/O pins greater than or equal to V_CCwhen the LED is off. Figure 15 shows a high-value resistor

in parallel with the LED. Figure 16 shows V_CCless than the LED supply voltage by at least 1.2 V. Both of these

methods maintain the I/O V_INat or above V_CCand prevent additional supply-current consumption when the LED

is off.

V

CC

LED

100 kW

V

CC

Pn

Figure 15. High-Value Resistor in Parallel With the LED

5 V

3.3 V

LED

V

CC

Pn

Figure 16. Device Supplied by a Lower Voltage

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PACKAGE OPTION ADDENDUM

www.ti.com

7-Nov-2006

PACKAGING INFORMATION

Orderable Device

PCA9536D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCA9536DG4

PCA9536DGKR

PCA9536DGKRG4

PCA9536DR

SOIC

MSOP

SOIC

D

DGK

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCA9536DRG4

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Low Power Wireless www.ti.com/lpw

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	PCA9536DR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOIC-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.87
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	380741
Samacsys Pin Count：	8
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	D0008A SOIC
Samacsys Released Date：	2020-04-15 02:46:26
Is Samacsys：	N
最大时钟频率：	0.4 MHz
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	1
位数：	4
I/O 线路数量：	4
端口数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	2.5/5 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	Parallel IO Ports
最大压摆率：	0.15 mA
最大供电电压：	5.5 V
最小供电电压：	2.3 V
标称供电电压：	3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.91 mm
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：	1

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