PCM1793现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

ꢊ

ꢦ

ꢠ

ꢉ

ꢊ

ꢠ

ꢟ

ꢯ

ꢝ

ꢀ

ꢠ

ꢟ

ꢫ

ꢦ

ꢥ

ꢣ

ꢤ

ꢞ

ꢠ

ꢟ

ꢡ

ꢌ

ꢧ

ꢮ

ꢢ

ꢤ

ꢋ

ꢝ

ꢤ

ꢣ

ꢠ

ꢦ

ꢡ

ꢧ

ꢝ

ꢣ

ꢤ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

SLES076A − MARCH 2003 − REVISED JANUARY 2004

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢌ

ꢍ

ꢃ

ꢅ

ꢇ

ꢉ

ꢎ

ꢏ

ꢐ

ꢑ

ꢒ

ꢂ

ꢀ

ꢓ

ꢋ

ꢔ

ꢕ

ꢍ

ꢒ

ꢖ

ꢗ

ꢒ

ꢔ

ꢁ

ꢘ

ꢖ

ꢁ

ꢑ

ꢘ

ꢕ

ꢂ

ꢘ

ꢔ

ꢌ

ꢍ

ꢒ

ꢙ

ꢖ

ꢋ

ꢚ

ꢑ

ꢌ

ꢘ

ꢛ

ꢘ

ꢚ

ꢖ

ꢋ

ꢕ

ꢋ

ꢌ

ꢒ

ꢓ

ꢉ

ꢌ

ꢚ

ꢉ

ꢒ

ꢔ

ꢒ

ꢓ

ꢚ

ꢕ

ꢚ

ꢔ

ꢗ

ꢘ

ꢛ

ꢌ

ꢘ

ꢛ

D

5-V Tolerant Digital Inputs

FEATURES

Small 28-Lead SSOP Package, Lead-Free

Product

D

24-Bit Resolution

Analog Performance:

− Dynamic Range: 113 dB

− THD+N: 0.001%

APPLICATIONS

D

A/V Receivers

− Full-Scale Output: 2.1 V rms (at

Postamplifier)

DVD Players

D

Differential Voltage Output: 3.2 V p-p

Musical Instruments

HDTV Receivers

8× Oversampling Digital Filter:

− Stop-Band Attenuation: –82 dB

− Pass-Band Ripple: 0.002 dB

Car Audio Systems

Digital Multitrack Recorders

Other Applications Requiring 24-Bit Audio

D

Sampling Frequency: 10 kHz to 200 kHz

System Clock: 128, 192, 256, 384, 512, or

768 f With Autodetect

S

DESCRIPTION

D

Accepts 16-, 20-, and 24-Bit Audio Data

The PCM1793 is a monolithic CMOS integrated circuit that

includes stereo digital-to-analog converters and support

circuitry in a small 28-lead SSOP package. The data

converters use TI’s advanced segment DAC architecture

to achieve excellent dynamic performance and improved

tolerance to clock jitter. The PCM1793 provides balanced

voltage outputs, allowing the user to optimize analog

performance externally. Sampling rates up to 200 kHz are

supported.

2

D

Data Formats: Standard, I S, and

Left-Justified

D

Digital De-Emphasis

Soft Mute

Zero Flags for Each Output

Dual Supply Operation:

− 5-V Analog, 3.3-V Digital

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to

damage because very small parametric changes could cause the device not to meet its published specifications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢀꢛ ꢚ ꢖꢙ ꢁ ꢌꢋ ꢚꢔ ꢖ ꢒꢌꢒ ꢜꢝ ꢞꢟ ꢠ ꢡꢢ ꢣꢜꢟꢝ ꢜꢤ ꢥꢦ ꢠ ꢠ ꢧꢝꢣ ꢢꢤ ꢟꢞ ꢨꢦꢩ ꢪꢜꢥ ꢢꢣꢜ ꢟꢝ ꢫꢢ ꢣꢧꢬ ꢀꢠ ꢟꢫꢦ ꢥꢣꢤ

ꢥ ꢟꢝ ꢞꢟꢠ ꢡ ꢣꢟ ꢤ ꢨꢧ ꢥ ꢜ ꢞꢜ ꢥ ꢢ ꢣꢜ ꢟꢝꢤ ꢨ ꢧꢠ ꢣꢭꢧ ꢣꢧ ꢠ ꢡꢤ ꢟꢞ ꢌꢧꢮ ꢢꢤ ꢋꢝꢤ ꢣꢠ ꢦꢡ ꢧꢝꢣ ꢤ ꢤꢣ ꢢꢝꢫ ꢢꢠ ꢫ ꢯ ꢢꢠ ꢠ ꢢ ꢝꢣꢰꢬ

ꢀꢠ ꢟ ꢫꢦꢥ ꢣ ꢜꢟ ꢝ ꢨꢠ ꢟ ꢥ ꢧ ꢤ ꢤ ꢜꢝ ꢱ ꢫꢟ ꢧ ꢤ ꢝꢟꢣ ꢝꢧ ꢥꢧ ꢤꢤ ꢢꢠ ꢜꢪ ꢰ ꢜꢝꢥ ꢪꢦꢫ ꢧ ꢣꢧ ꢤꢣꢜ ꢝꢱ ꢟꢞ ꢢꢪ ꢪ ꢨꢢ ꢠ ꢢꢡ ꢧꢣꢧ ꢠ ꢤꢬ

Copyright  2004, Texas Instruments Incorporated

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

ORDERING INFORMATION

OPERATION

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PRODUCT

PACKAGE

PACKAGE CODE

PCM1793DB

Tube

PCM1793DB

28-lead SSOP

28DB

−25°C to 85°C

PCM1793

PCM1793DBR

Tape and reel

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

PCM1793

V

F, V L, V C, V

R

−0.3 V to 6.5 V

−0.3 V to 4 V

0.1 V

CC

DD

CC CC CC

Supply voltage

Supply voltage differences: V F, V L, V C, V

R

CC CC CC CC

Ground voltage differences: AGNDF, AGNDL, AGNDC, AGNDR, DGND

0.1 V

LRCK, DATA, BCK, SCK, DEMP0, DEMP1, FMT0, FMT1, FMT2, RST, MUTE

ZEROL, ZEROR

–0.3 V to 6.5 V

Digital input voltage

Analog input voltage

–0.3 V to (V

+ 0.3 V) < 4 V

DD

+ 0.3 V) < 6.5 V

–0.3 V to (V

CC

Input current (any pins except supplies)

Ambient temperature under bias

Storage temperature

10 mA

–40°C to 125°C

–55°C to 150°C

150°C

Junction temperature

Lead temperature (soldering)

Package temperature (IR reflow, peak)

260°C, 5 s

260°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

all specifications at T = 25°C, V

CC

= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted

DD S S

A

PCM1793DB

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

RESOLUTION

DATA FORMAT

24

Bits

2

Audio data interface format

Audio data bit length

Audio data format

Standard, I S, left justified

16-, 20-, 24-bit selectable

MSB first, 2s complement

f

S

Sampling frequency

System clock frequency

10

200

kHz

128, 192, 256, 384, 512, 768 f

S

DIGITAL INPUT/OUTPUT

Logic family

TTL compatible

2

V

IH

IL

Input logic level

Input logic current

Output logic level

VDC

µA

0.8

10

I

V

= V

DD

= 0 V

IH

IN

–10

IL

V

I

= −2 mA

= 2 mA

2.4

OH

OL

OH

OL

VDC

V

I

0.4

2

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

ELECTRICAL CHARACTERISTICS (Continued)

all specifications at T = 25°C, V

= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted

DD S S

A

CC

PCM1793DB

TYP

PARAMETER

(1)

TEST CONDITIONS

UNIT

MIN

MAX

DYNAMIC PERFORMANCE

f

= 44.1 kHz

0.001%

0.0015%

0.003%

113

0.002%

S

= 96 kHz

THD+N at V

OUT

= 0 dB

= 192 kHz

EIAJ, A-weighted, f = 44.1 kHz

S

110

EIAJ, A-weighted, f = 96 kHz

S

113

Dynamic range

dB

EIAJ, A-weighted, f = 192 kHz

113

S

EIAJ, A-weighted, f = 44.1 kHz

S

EIAJ, A-weighted, f = 96 kHz

S

110

106

113

Signal-to-noise ratio

EIAJ, A-weighted, f = 192 kHz

113

S

f

S

f

S

f

S

= 44.1 kHz

= 96 kHz

110

Channel separation

Level linearity error

dB

= 192 kHz

109

V

OUT

= −120 dB

1

ANALOG OUTPUT

Gain error

–8

–3

–2

3

0.5

3.2

1.4

8

3

2

% of FSR

V p-p

Gain mismatch, channel-to-channel

Bipolar zero error

At BPZ

(2)

Differential output voltage

Full scale (0 dB)

At BPZ

(2)

Bipolar zero voltage

V

(2)

Load impedance

R

1

= R

1.7

kΩ

2

DIGITAL FILTER PERFORMANCE

De-emphasis error

0.1

dB

0.002 dB

–3 dB

0.454 f

0.49 f

S

Pass band

Stop band

0.546 f

S

Pass-band ripple

0.002

dB

s

Stop band = 0.546 f

Stop band = 0.567 f

–75

–82

S

Stop-band attenuation

Delay time

29/f

S

(1)

(2)

Dynamic performance and DC accuracy are specified at the output of the postamplifier as shown in Figure 28. Analog performance specifications

are measured using the System Twot Cascade audio measurement system by Audio Precisiont in the averaging mode. At all sampling

frequency operations, measurement bandwidth is limited with a 20-kHz AES17 filter.

These parameters are defined at the PCM1793 output pin. Load impedance, R1 and R2, are input resistors of the postamplifier. These are defined

as dc loads.

Audio Precision and System Two are trademarks of Audio Precision, Inc.

Other trademarks are the property of their respective owners.

3

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

ELECTRICAL CHARACTERISTICS (Continued)

all specifications at T = 25°C, V

= 5 V, V

DD

= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted

A

CC

PARAMETER

POWER SUPPLY REQUIREMENTS

S

PCM1793DB

TYP

TEST CONDITIONS

UNIT

MIN

MAX

V

3

3.3

5

3.6

5.5

8

DD

CC

Voltage range

VDC

mA

4.5

f

S

f

S

f

S

f

S

f

S

f

S

f

S

f

S

f

S

= 44.1 kHz

6.5

13.5

28

(1)

= 96 kHz

I

Supply current

DD

= 192 kHz

= 44.1 kHz

= 96 kHz

14

16

15

I

Supply current

mA

CC

= 192 kHz

= 44.1 kHz

= 96 kHz

16

90

110

(1)

120

170

Power dissipation

mW

= 192 kHz

TEMPERATURE RANGE

Operation temperature

Thermal resistance

–25

85

°C

θ

28-pin SSOP

100

°C/W

JA

(1)

Input is BPZ data.

PIN ASSIGNMENTS

PCM1793

(TOP VIEW)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

LRCK

FMT2

FMT1

FMT0

DEMP1

DEMP0

ZEROL

ZEROR

2

BCK

DATA

MUTE

SCK

3

4

5

6

RST

7

V

DD

8

DGND

AGNDF

V

F

L

CC

9

CC

V

R

10

11

12

13

14

AGNDL

CC

AGNDR

V

L−

L+

OUT

V

R−

R+

OUT

AGNDC

OUT

V

C

COM

CC

4

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

TERMINAL

SLES076A − MARCH 2003 − REVISED JANUARY 2004

Terminal Functions

I/O

DESCRIPTIONS

NAME

16

9

AGNDC

AGNDF

AGNDL

AGNDR

BCK

−

I

Analog ground (internal bias and current DAC)

Analog ground (DACFF)

19

11

2

Analog ground (L-channel I/V)

Analog ground (R-channel I/V)

(1)

Bit clock input

(1)

DATA

3

I

Serial audio data input

De-emphasis control 0

De-emphasis control 1

Digital ground

DEMP0

DEMP1

DGND

FMT0

24

25

8

I

−

I

(1)

26

27

28

1

Audio data format select 0

Audio data format select 1

Audio data format select 2

FMT1

I

FMT2

I

(1)

Left and right clock (f ) input

S

LRCK

MUTE

RST

I

(1)

4

I

Analog output mute control

(1)

6

I

Reset

System clock input

(1)

SCK

5

I

V

C

F

L

15

21

20

10

14

7

−

O

Analog power supply (internal bias and current DAC), 5 V

Analog power supply (DACFF), 5 V

Analog power supply (L-channel I/V), 5 V

Analog power supply (R-channel I/V), 5 V

Internal bias decoupling pin

CC

R

COM

DD

Digital power supply, 3.3 V

L+

17

18

13

12

23

22

L-channel analog voltage output +

L-channel analog voltage output −

R-channel analog voltage output +

R-channel analog voltage output −

Zero flag for L-channel

OUT

L−

R+

R−

ZEROL

ZEROR

Zero flag for R-channel

(1)

Schmitt-trigger input, 5-V tolerant

5

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

FUNCTIONAL BLOCK DIAGRAM

LRCK

Current

Segment

DAC

V

L−

L+

Audio

BCK

OUT

Data Input

DATA

I/F

OUT

and

I/V Buffer

D/S and Filter

8

Oversampling

Digital

Filter

and

Function

Control

MUTE

RST

Advanced

Segment

DAC

Bias

and

Vref

V

COM

FMT2

FMT1

FMT0

Modulator

Function

Control

I/F

Current

Segment

DAC

and

I/V Buffer

V

R+

R−

OUT

DEMP1

DEMP0

OUT

D/S and Filter

ZEROL

ZEROR

System

Clock

Manager

Zero

Detect

Power Supply

6

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

TYPICAL PERFORMANCE CURVES

DIGITAL FILTER

Digital Filter Response

AMPLITUDE

vs

FREQUENCY

0

−20

3

0.003

2

0.002

−40

1

0.001

−60

−80

0

−100

−120

−140

−160

−1

−0.001

−2

−0.002

−

−0.003

0.0

0

1

2

3

4

0.1

0.2

0.3

0.4

0.5

Frequency[× f ]

S

Figure 1. Frequency Response, Sharp Rolloff

Figure 2. Pass-Band Ripple, Sharp Rolloff

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

0

−20

0

−2

−4

−40

−6

−8

−60

−10

−12

−14

−16

−18

−20

−80

−100

−120

−140

0

1

2

3

4

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Frequency[× f ]

S

Figure 3. Frequency Response, Slow Rolloff

Figure 4. Transition Characteristics, Slow Rolloff

7

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

De-Emphasis Filter

DE-EMPHASIS LEVEL

vs

DE-EMPHASIS ERROR

vs

FREQUENCY

0

0.5

0.4

0.3

0.2

0.1

f

S

= 32 kHz

f

S

= 32 kHz

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−0.0

0.0

−0.1

−0.2

−0.3

−0.4

−0.5

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

f − Frequency − kHz

Figure 5

Figure 6

DE-EMPHASIS LEVEL

vs

DE-EMPHASIS ERROR

vs

FREQUENCY

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

0.5

0.4

f

= 44.1 kHz

f

S

= 44.1 kHz

S

0.3

0.2

0.1

−0.0

−0.1

−0.2

−0.3

−0.4

−0.5

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

f − Frequency − kHz

Figure 7

Figure 8

8

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

De-Emphasis Filter (Continued)

DE-EMPHASIS LEVEL

vs

DE-EMPHASIS ERROR

vs

FREQUENCY

0

0.5

0.4

f

S

= 48 kHz

f

S

= 48 kHz

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

0.3

0.2

0.1

−0.0

−0.1

−0.2

−0.3

−0.4

−0.5

0

2

4

6

8

10 12 14 16 18 20 22

0

2

4

6

8

10 12 14 16 18 20 22

f − Frequency − kHz

Figure 9

Figure 10

9

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

ANALOG DYNAMIC PERFORMANCE

Supply Voltage Characteristics

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE

vs

SUPPLY VOLTAGE

118

116

114

112

110

108

0.01

f

= 192 kHz

= 96 kHz

S

f

= 96 kHz

S

f

S

= 44.1 kHz

0.001

f

S

= 44.1 kHz

f

S

= 192 kHz

0.0001

4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00

V

CC

− Supply Voltage − V

V

CC

− Supply Voltage − V

Figure 11

Figure 12

SIGNAL-to-NOISE RATIO

vs

CHANNEL SEPARATION

vs

SUPPLY VOLTAGE

118

116

114

112

110

108

114

112

110

108

106

104

102

f

= 44.1 kHz

S

f

S

= 96 kHz

f

= 96 kHz

S

f

S

= 192 kHz

f

S

= 192 kHz

f

S

= 44.1 kHz

4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00

V

CC

− Supply Voltage − V

V

CC

− Supply Voltage − V

Figure 13

Figure 14

NOTE: PCM mode, T = 25°C, V

= 3.3 V.

A

DD

10

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

Temperature Characteristics

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE

vs

FREE-AIR TEMPERATURE

118

116

114

112

110

108

0.01

f

= 192 kHz

S

f

= 96 kHz

S

f

= 96 kHz

S

f

= 44.1 kHz

S

f

S

= 192 kHz

0.001

f

= 44.1 kHz

S

0.0001

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

Figure 15

Figure 16

SIGNAL-to-NOISE RATIO

vs

CHANNEL SEPARATION

vs

FREE-AIR TEMPERATURE

118

116

114

112

110

108

114

112

110

108

106

104

f

= 44.1 kHz

S

f

= 44.1 kHz

S

f

= 96 kHz

S

f

S

= 96 kHz

f = 192 kHz

S

f

S

= 192 kHz

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

Figure 17

Figure 18

NOTE: PCM mode, V

DD

= 3.3 V, V = 5 V.

CC

11

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

AMPLITUDE vs FREQUENCY

−50

AMPLITUDE vs FREQUENCY

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−150

−160

−100

−110

−120

−130

−140

−150

−160

0

5

10

15

20

0

10 20 30 40 50 60 70 80 90 100

f − Frequency − kHz

Figure 19. −60-dB Output Spectrum, BW = 20 kHz Figure 20. −60-dB Output Spectrum, BW = 100 kHz

NOTE: PCM mode, f = 44.1 kHz, 32768 points, 8 average, T = 25°C, V

DD

= 3.3 V, V = 5 V.

CC

S

A

TOTAL HARMONIC DISTORTION + NOISE

vs

INPUT LEVEL

100

10

1

0.1

0.01

0.001

0.0001

−100

−80

−60

−40

−20

0

Input Level − dBFS

Figure 21. THD+N vs Input Level, PCM Mode

NOTE: PCM mode, f = 44.1 kHz, T = 25°C, V

DD

= 3.3 V, V = 5 V.

CC

S

A

12

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

SYSTEM CLOCK AND RESET FUNCTIONS

System Clock Input

The PCM1793 requires a system clock for operating the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input (pin 5). The PCM1793 has a system clock detection circuit

that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock

frequencies for common audio sampling rates.

Figure 22 shows the timing requirements for the system clock input. For optimal performance, it is important to use

a clock source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators

is an excellent choice for providing the PCM1793 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SYSTEM CLOCK FREQUENCY (F

) (MHZ)

512 f

SCK

SAMPLING FREQUENCY

128 f

192 f

256 f

384 f

768 f

S

32 kHz

44.1 kHz

48 kHz

4.096

5.6488

6.144

8.4672

9.216

8.192

11.2896

12.288

24.576

49.152

12.288

16.9344

18.432

36.864

73.728

16.384

22.5792

24.576

33.8688

36.864

96 kHz

12.288

24.576

18.432

36.864

49.152

(1)

73.728

(1)

192 kHz

(1)

This system clock rate is not supported for the given sampling frequency.

t

(SCKH)

H

2.0 V

0.8 V

System Clock (SCK)

L

t

(SCY)

(SCKL)

PARAMETERS

MIN MAX UNITS

t

System clock pulse cycle time

13

5

ns

(SCY)

t

System clock pulse duration, HIGH

System clock pulse duration, LOW

(SCKH)

t

5

(SCKL)

Figure 22. System Clock Input Timing

Power-On and External Reset Functions

The PCM1793 includes a power-on reset function. Figure 23 shows the operation of this function. With V

> 2 V,

DD

the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time

> 2 V.

V

DD

The PCM1793 also includes an external reset capability using the RST input (pin 6). This allows an external controller

or master reset circuit to force the PCM1793 to initialize to its default reset state.

Figure 24 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The

RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock

periods. The external reset is especially useful in applications where there is a delay between the PCM1793 power

up and system clock activation.

13

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

V

DD

2.4 V (Max)

2.0 V (Typ)

1.6 V (Min)

Reset

Reset Removal

Internal Reset

System Clock

1024 System Clocks

Figure 23. Power-On Reset Timing

RST (Pin 6)

1.4 V

t

(RST)

Reset

Reset Removal

Internal Reset

System Clock

1024 System Clocks

PARAMETERS

Reset pulse duration, LOW

MIN

MAX UNITS

t

20

ns

(RST)

Figure 24. External Reset Timing

14

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

AUDIO DATA INTERFACE

Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes LRCK (pin 1), BCK (pin 2), and DATA (pin 3). BCK is the

serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio

interface. Serial data is clocked into the PCM1793 on the rising edge of BCK. LRCK is the serial audio left/right word

clock.

The PCM1793 requires the synchronization of LRCK and the system clock, but does not need a specific phase

relation between LRCK and the system clock.

If the relationship between LRCK and the system clock changes more than 6 BCK, internal operation is initialized

within 1/f and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the

S

system clock is completed.

PCM Audio Data Formats and Timing

2

The PCM1793 supports industry-standard audio data formats, including standard right-justified, I S, and

left-justified. The data formats are shown in Figure 26. Data formats are selected using the format bits,

FMT2 (pin 28), FMT1 (pin27), and FMT0 (pin26) as shown in Table 2. All formats require binary 2s complement,

MSB-first audio data. Figure 25 shows a detailed timing diagram for the serial audio interface.

Table 2. Audio Data Format Selection

FMT2

FMT1

FMT0

FORMAT

PIN 28 PIN 27

PIN 26

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

16-bit standard format, right-justified

20-bit standard format, right-justified

24-bit standard format, right-justified

24-bit MSB-first, left-justified format

2

16-bit I S format

2

24-bit I S format

Reserved

15

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

1.4 V

LRCK

t

(BCL)

t

(BCH)

(LB)

1.4 V

BCK

t

(BCY)

(BL)

DATA

t

(DS)

(DH)

PARAMETERS

MIN MAX UNITS

t

BCK pulse cycle time

BCK pulse duration, LOW

BCK pulse duration, HIGH

BCK rising edge to LRCK edge

LRCK edge to BCK rising edge

DATA setup time

70

30

10

ns

(BCY)

(BCL)

(BCH)

(BL)

(LB)

(DS)

DATA hold time

(DH)

—

LRCK clock duty

50% 2 bit clocks

Figure 25. Timing of Audio Interface

16

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

(1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW

1/f

S

LRCK

R-Channel

L-Channel

BCK

Audio Data Word = 16-Bit

14 15 16

1

2

15 16

LSB

1

2

15 16

DATA

MSB

Audio Data Word = 20-Bit

18 19 20

1

2

19 20

LSB

1

2

19 20

23 24

DATA

MSB

Audio Data Word = 24-Bit

22 23 24

1

2

23 24

LSB

1

2

DATA

MSB

(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW

1/f

S

LRCK

BCK

R-Channel

L-Channel

Audio Data Word = 24-Bit

DATA

1

2

23 24

LSB

1

2

23 24

1

2

MSB

2

(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH

1/f

S

LRCK

L-Channel

R-Channel

BCK

Audio Data Word = 16-Bit

DATA

1

2

15 16

LSB

1

2

15 16

1

2

MSB

Audio Data Word = 24-Bit

DATA

23 24

LSB

1

23 24

Figure 26. Audio Data Input Formats

17

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

FUNCTION DESCRIPTIONS

Zero Detect

When the PCM1793 detects that the audio input data in the L-channel or R-channel is continuously zero for 1024

f , the PCM1793 sets ZEROL (pin 23) or ZEROR (pin 22) to HIGH.

S

Soft Mute

The PCM1793 supports mute operation. When MUTE (pin 4) is set to HIGH, both analog outputs are transitioned

to the bipolar zero level in −0.5-dB steps with a transition speed of 1/f per step. This system provides pop-free muting

S

of the DAC output.

De-Emphasis

The PCM1793 has de-emphasis filters for sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz. DEMP1 (pin 25)

and DEMP0 (pin 24) select the sampling frequency for which de-emphasis filtering is performed, as shown in Table 3.

Table 3. De-Emphasis Control

DEMP1 DEMP0

DE-EMPHASIS FUNCTION

PIN 25

PIN 24

LOW

Disabled

LOW

HIGH

LOW

48 kHz

44.1 kHz

32 kHz

HIGH

18

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

TYPICAL CONNECTION DIAGRAM

L/R Clock (f )

S

LRCK

BCK

FMT2

FMT1

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Bit Clock

Audio Data

DATA

MUTE

SCK

FMT0

3

Controller

DEMP1

DEMP0

ZEROL

ZEROR

4

System Clock

3.3 V

5

RST

6

V

DD

7

+

PCM1793

DGND

V

F

L

8

CC

AGNDF

9

CC

V R

CC

AGNDL

L−

10

11

12

13

14

Analog

Output Stage

(See Figure 28)

Analog

AGNDR

V

OUT

Output Stage

(See Figure 28)

V

R−

V

L+

OUT

AGNDC

R+

OUT

V C

CC

COM

Figure 27. Typical Application Circuit

19

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

APPLICATION INFORMATION

ANALOG OUTPUTS

LRCK

BCK

FMT2

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

FMT1

FMT0

DATA

MUTE

SCK

3

DEMP1

DEMP0

ZEROL

ZEROR

4

5

RST

6

V

DD

7

PCM1793

DGND

V

F

L

8

0.1 µF

CC

5 V

+

AGNDF

9

CC

10 µF

R L

4

V R

CC

AGNDL

10

11

12

13

14

C L

3

R L

6

2

AGNDR

V

L−

L+

OUT

C L

1

V

R−

V

OUT

−

+

V

OUT

L-Channel

R L

1

R L

5

AGNDC

R+

OUT

V C

CC

C L

2

COM

R L

3

+

1 µF

R R

4

C R

3

R R

2

R R

6

C R

1

−

+

V

OUT

R-Channel

R R

1

R R

5

C R

2

R R

3

NOTE: Example R and C values for f = 77 kHz – R , R : 1.8 kΩ, R ,R : 3.3 kΩ, R ,R : 680 Ω, C : 1800 pF, C , C : 560 pF.

C

1

2

3

4

5

6

1

2

3

Figure 28. Typical Application for Analog Output Stage

Analog Output Level and LPF

The signal level of the DAC differential-voltage output {(V

L+)–(V

L–), (V

R+)–(V

R–)} is 3.2 Vp-p

OUT

at 0 dB (full scale). The voltage output of the LPF is given by following equation:

V

= 3.2 Vp-p × (R /R )

OUT

f

i

Here, R is the feedback resistor in the LPF, and R = R in a typical application circuit. R is the input resistor

f

3

4

i

in the LPF, and R = R in a typical application circuit.

1

2

Op Amp for LPF

An OPA2134 or 5532 type op amp is recommended for the LPF circuit to obtain the specified audio

performance. Dynamic performance such as gain bandwidth, settling time, and slew rate of the op amp largely

determines the audio dynamic performance of the LPF section. The input noise specification of the op amp

should be considered to obtain a 113-dB S/N ratio.

20

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

Analog Gain of Balanced Amplifier

The DAC voltage outputs are followed by balanced amplifier stages, which sum the differential signals for each

channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a third-order

low-pass filter function, which band limits the audio output signal. The cutoff frequency and gain are determined

by external R and C component values. In this case, the cutoff frequency is 77 kHz with a gain of 1.83. The

output voltage for each channel is 5.9 Vp-p, or 2.1 V rms.

THEORY OF OPERATION

Upper

0−62

6 Bit

Level

ICOB

Decoder

0−66

Current

Segment

DAC

Analog

Voltage

Output

Digital

Input

Advanced

DWA

I/V

Converter

24 Bit

8 f

rd

3 -Order

S

5-Level

Sigma-Delta

0−4

Level

MSB

and

Lower 18 Bit

Figure 29. Advanced Segment DAC With I/V Converter

The PCM1793 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and

improved tolerance to clock jitter. The PCM1793 provides balanced voltage outputs.

Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted

to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed

by a five-level third-order delta-sigma modulator operated at 64 f by default. The 1 level of the modulator is equivalent

S

to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order

delta-sigma modulator are summed together to an up-to-66-level digital code, and then processed by data-weighted

averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is

converted to an analog output in the differential-current segment section.

This architecture has overcome the various drawbacks of conventional multibit processing and also achieves

excellent dynamic performance.

21

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

CONSIDERATIONS FOR APPLICATION CIRCUITS

PCB Layout Guidelines

A typical PCB floor plan for the PCM1793 is shown in Figure 30. A ground plane is recommended, with the analog

and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1793 must be

oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital

audio interface and control signals originating from the digital section of the board. Separate power supplies are

recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital

supply from contaminating the analog power supply and degrading the dynamic performance of the D/A converters.

In cases where a common 5-V supply would be used for the analog and digital sections, an inductance (RF choke,

ferrite bead) must be placed between the analog and digital 5-V supply connections to avoid coupling of the digital

switching noise into the analog circuitry. Figure 31 shows the recommended approach for single-supply applications.

Digital Power

+V DGND

Analog Power

AGND +5VA

+V

S

−V

S

D

REG

V

CC

Digital Logic

and

Audio

Processor

V

DD

DGND

Output

Circuits

PCM1793

AGND

Digital

Ground

Analog

Ground

Digital Section

Analog Section

Return Path for Digital Signals

Figure 30. Recommended PCB Layout

22

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

Power Supplies

+5V AGND +V

RF Choke or Ferrite Bead

−V

S

REG

V

CC

V

DD

V

DD

DGND

Output

Circuits

PCM1793

AGND

Common

Ground

Digital Section

Analog Section

Figure 31. Single-Supply PCB Layout

Bypass and Decoupling Capacitor Requirements

Various-sized decoupling capacitors can be used, with no special tolerances being required. All capacitors must be

located as close as possible to the appropriate pins of the PCM1793 to reduce noise pickup from surrounding circuitry.

Aluminum electrolytic capacitors that are designed for hi-fi audio applications are recommended for larger values,

while metal film or monolithic ceramic capacitors are used for smaller values.

Post-LPF Design

By proper choice of the op amp and resistors used in the post-LPF circuit, excellent performance of the PCM1793

should be achieved. To obtain 0.001% THD+N, 113 dB signal-to-noise-ratio audio performance, the THD+N and input

noise performance of the op amp must be considered. This is because the input noise of the op amp contributes

directly to the output noise level of the application. The V

post-LPF circuit must be connected as closely as possible.

pins of the PCM1793 and the input resistor of the

OUT

Out-of-band noise level and attenuated sampling spectrum level are much lower than for typical delta-sigma type

DACs due to the combination of a high-performance digital filter and advanced segment DAC architecture. The use

of a second-order or third-order post-LPF is recommended for the post-LPF of the PCM1793. The cutoff frequency

of the post-LPF depends on the application. For example, there are many sampling-rate operations such as

f = 44.1 kHz on CDDA, f = 96 kHz on DVD-M, f = 192 kHz on DVD-A, f = 64 f on DSD (SACD).

S

23

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ

www.ti.com

SLES076A − MARCH 2003 − REVISED JANUARY 2004

MECHANICAL DATA

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°−ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

14

16

20

24

28

30

38

6,50

5,90

7,50

6,90

8,50

7,90

10,50

9,90

10,50

9,90

12,90

12,30

A MAX

A MIN

5,90

4040065/E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

24

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

电子百科

产品导航

产品型号PCM1793的概述

产品型号PCM1793的Datasheet PDF文件预览

PCM1793相关产品..

PCM1793相关文章