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  • PCM1796DBR图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • PCM1796DBR 现货库存
  • 数量20800 
  • 厂家BB量大发货 
  • 封装SSOP28 
  • 批号2020+ 
  • 全新进口原装
  • QQ:1220223788QQ:1220223788 复制
    QQ:1327510916QQ:1327510916 复制
  • 86-0755-28767101 QQ:1220223788QQ:1327510916
  • PCM1796DB图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • PCM1796DB 现货库存
  • 数量22000 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • PCM1796DBR图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • PCM1796DBR 现货库存
  • 数量3550 
  • 厂家TI/BB 
  • 封装SSOP-28 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • PCM1796DB图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • PCM1796DB 现货库存
  • 数量32560 
  • 厂家TI 
  • 封装SSOP28 
  • 批号2024+ 
  • 【原装优势★★★绝对有货】
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • PCM1796DB图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • PCM1796DB 现货库存
  • 数量92000 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
  • 批号24+ 
  • 原装现货假一罚十!可含税长期供货
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • PCM1796DBR图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • PCM1796DBR 现货库存
  • 数量5000 
  • 厂家TI 
  • 封装SSOP28 
  • 批号24+ 
  • 全新原装现货,低价出售,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084
  • PCM1796DBR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • PCM1796DBR 现货库存
  • 数量5000 
  • 厂家TI 
  • 封装SSOP28 
  • 批号25+ 
  • 全新原装,欢迎查询
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • PCM1796DBR??图
  • 深圳市芯球通科技有限公司

     该会员已使用本站8年以上
  • PCM1796DBR?? 现货库存
  • 数量2000 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
  • 批号19+ 
  • 原装现货,假一赔十,可开原型号发票
  • QQ:591882259QQ:591882259 复制
  • 0755-23816608 QQ:591882259
  • PCM1796DB图
  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • PCM1796DB 现货库存
  • 数量8560 
  • 厂家TI 
  • 封装SSOP28 
  • 批号17+ 
  • 受权代理!全新原装现货特价热卖!
  • QQ:1258645397QQ:1258645397 复制
    QQ:876098337QQ:876098337 复制
  • 0755-83238902 QQ:1258645397QQ:876098337
  • PCM1796DBR图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • PCM1796DBR 现货库存
  • 数量6851 
  • 厂家TI 
  • 封装28SSOP 
  • 批号24+ 
  • 全新原装现货,可开增值税发票,欢迎询购!
  • QQ:1950791264QQ:1950791264 复制
    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
  • PCM1796DB【特价现货】图
  • 齐创科技(上海北京青岛)有限公司

     该会员已使用本站14年以上
  • PCM1796DB【特价现货】 现货库存
  • 数量6800 
  • 厂家TI代理 
  • 封装28SSOP 
  • 批号25+热销 
  • 中国区代理全新热卖原装正品
  • QQ:2394092314QQ:2394092314 复制
    QQ:792179102QQ:792179102 复制
  • 021-62153656 QQ:2394092314QQ:792179102
  • PCM1796DB图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • PCM1796DB 现货库存
  • 数量47 
  • 厂家TI 
  • 封装SSOP (DB) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • PCM1796DBR图
  • 深圳市力拓辉电子有限公司

     该会员已使用本站13年以上
  • PCM1796DBR 现货库存
  • 数量20000 
  • 厂家TI 
  • 封装SSOP-28 
  • 批号1725+ 
  • 专用TI音频芯片热卖
  • QQ:2881140004QQ:2881140004 复制
    QQ:2881140005QQ:2881140005 复制
  • 755-82787180 QQ:2881140004QQ:2881140005
  • PCM1796DBR图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • PCM1796DBR 热卖库存
  • 数量8000 
  • 厂家BB 
  • 封装SMD 
  • 批号24+ 
  • ★★专业IC现货,诚信经营,市场最优价★★
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084
  • PCM1796图
  • 集好芯城

     该会员已使用本站13年以上
  • PCM1796
  • 数量12141 
  • 厂家TI/德州仪器 
  • 封装AN 
  • 批号最新批次 
  • 原厂原装公司现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • PCM1796图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • PCM1796
  • 数量34256 
  • 厂家BB 
  • 封装SSOP 
  • 批号2020+ 
  • 全新原装进口现货特价热卖,长期供应."
  • QQ:1220223788QQ:1220223788 复制
    QQ:1327510916QQ:1327510916 复制
  • 86-0755-28767101 QQ:1220223788QQ:1327510916
  • PCM1796DB图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • PCM1796DB
  • 数量30000 
  • 厂家TI/德州仪器 
  • 封装SSOP 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • PCM1796图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • PCM1796
  • 数量53529 
  • 厂家TI/德州仪器 
  • 封装SSOP-28 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • PCM1796图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • PCM1796
  • 数量22802 
  • 厂家TI 
  • 封装SSOP28 
  • 批号2023+ 
  • 绝对原装正品现货,全新深圳原装进口现货
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • PCM1796DBR图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • PCM1796DBR
  • 数量6500 
  • 厂家TI/BB 
  • 封装SSOP-28 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
  • QQ:1437347957QQ:1437347957 复制
    QQ:1205045963QQ:1205045963 复制
  • 0755-82343089 QQ:1437347957QQ:1205045963
  • PCM1796DB图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • PCM1796DB
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装SSOP-28 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • PCM1796DB图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • PCM1796DB
  • 数量6328 
  • 厂家TI-德州仪器 
  • 封装TSSOP-28 
  • 批号▉▉:2年内 
  • ▉▉¥52.4元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • PCM1796DB图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • PCM1796DB
  • 数量3577 
  • 厂家TI 
  • 封装28-SSOP(0.209,5.30mm 宽) 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • PCM1796DB图
  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • PCM1796DB
  • 数量20000 
  • 厂家TI 
  • 封装原厂封装 
  • 批号23+ 
  • 原装现货热卖!请联系吴先生 13681678667
  • QQ:617677003QQ:617677003 复制
  • 15618836863 QQ:617677003
  • PCM1796DB图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • PCM1796DB
  • 数量5600 
  • 厂家TI 
  • 封装SSOP28 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • PCM1796图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • PCM1796
  • 数量16815 
  • 厂家BB 
  • 封装SSOP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • PCM1796DB图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • PCM1796DB
  • 数量28620 
  • 厂家TI 
  • 封装28-SSOP 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • PCM1796DB图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • PCM1796DB
  • 数量17298 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
  • 批号24+ 
  • 原装原厂 现货现卖
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • PCM1796DB图
  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • PCM1796DB
  • 数量99000 
  • 厂家TI 
  • 封装SSOP28 
  • 批号23+ 
  • 一级代理进口原装现货、假一罚十价格合理
  • QQ:1157099927QQ:1157099927 复制
    QQ:2039672975QQ:2039672975 复制
  • 0755-2870-8773手机微信同号13430772257 QQ:1157099927QQ:2039672975
  • PCM1796图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • PCM1796
  • 数量13815 
  • 厂家BB 
  • 封装SSOP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • PCM1796DB图
  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • PCM1796DB
  • 数量9500 
  • 厂家TI(德州仪器) 
  • 封装28-SSOP(0.209,5.30mm 宽) 
  • 批号23+/24+ 
  • 绝对原装正品,可开13%专票,欢迎采购!!!
  • QQ:3354557638QQ:3354557638 复制
    QQ:3354557638QQ:3354557638 复制
  • 18565729389 QQ:3354557638QQ:3354557638
  • PCM1796DB图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • PCM1796DB
  • 数量660000 
  • 厂家TI(德州仪器) 
  • 封装SSOP-28 
  • 批号23+ 
  • 支持实单/只做原装
  • QQ:3008961398QQ:3008961398 复制
  • 0755-21006672 QQ:3008961398
  • PCM1796DBR图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • PCM1796DBR
  • 数量3300 
  • 厂家TI/德州仪器 
  • 封装SSOP28 
  • 批号2020 
  • 绝对全新原装现货,欢迎来电查询
  • QQ:215672808QQ:215672808 复制
  • 0755-83229772 QQ:215672808
  • PCM1796图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • PCM1796
  • 数量5000 
  • 厂家BB 
  • 封装SSOP 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931 QQ:857273081QQ:1594462451
  • PCM1796DB图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • PCM1796DB
  • 数量68000 
  • 厂家TI 
  • 封装SSOP28 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:18818596997 QQ:84556259
  • QQ:84556259QQ:84556259 复制
    QQ:783839662QQ:783839662 复制
  • 0755- QQ:84556259QQ:783839662
  • PCM1796图
  • 长荣电子

     该会员已使用本站14年以上
  • PCM1796
  • 数量35 
  • 厂家BB 
  • 封装SSOP 
  • 批号06+ 
  • 现货
  • QQ:172370262QQ:172370262 复制
  • 754-4457500 QQ:172370262
  • PCM1796DBRG4图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • PCM1796DBRG4
  • 数量68000 
  • 厂家BB/TI 
  • 封装SSOP28 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • PCM1796图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • PCM1796
  • 数量85000 
  • 厂家TI/德州仪器 
  • 封装10PB 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • PCM1796DBR图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • PCM1796DBR
  • 数量45000 
  • 厂家TI/德州仪器 
  • 封装SSOP-28 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
  • PCM1796DB图
  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • PCM1796DB
  • 数量3003 
  • 厂家TI 
  • 封装原厂封装 
  • 批号22+ 
  • 原装正品★真实库存★价格优势★欢迎来电洽谈
  • QQ:1686616797QQ:1686616797 复制
    QQ:2440138151QQ:2440138151 复制
  • 0755-22655674 QQ:1686616797QQ:2440138151

产品型号PCM1796的概述

PCM1796芯片概述 PCM1796是一款由德州仪器(Texas Instruments,TI)推出的高性能数模转换器(DAC),以其高质量的音频性能而广泛应用于音频设备中。这款DAC以其优良的动态范围和低失真特性,适用于高保真音频系统和专业音频设备。PCM1796采用先进的Delta-Sigma(ΔΣ)调制技术,能够有效地转换数字信号为模拟信号。由于其独特的设计和优异的性能,PCM1796在数字音频播放、音频处理器以及其他高端音频应用中得到了广泛的认可。 PCM1796详细参数 PCM1796的主要参数如下: - 分辨率:24位 - 信号采样率:最高支持192kHz - 动态范围:112dB(典型值) - 总谐波失真(THD+N):0.0015%(典型值) - 工作电源电压:+5V至+15V - 对应的数字音频接口:I2S、左对齐、右对齐、传输接口 - 功耗:约90mW - 温度范...

产品型号PCM1796的Datasheet PDF文件预览

SLES100 − DECEMBER 2003  
ꢋꢕ  
D
D
5-V Tolerant Digital Inputs  
FEATURES  
Small 28-Lead SSOP Package, Lead-Free  
Product  
D
24-Bit Resolution  
D
Analog Performance:  
− Dynamic Range: 123 dB  
− THD+N: 0.0005%  
APPLICATIONS  
D
D
D
D
D
D
D
A/V Receivers  
D
D
Differential Current Output: 4 mA p-p  
SACD Players  
8× Oversampling Digital Filter:  
− Stop-Band Attenuation: –98 dB  
− Pass-Band Ripple: 0.0002 dB  
DVD Players  
HDTV Receivers  
D
D
Sampling Frequency: 10 kHz to 200 kHz  
System Clock: 128, 192, 256, 384, 512, or  
Car Audio Systems  
Digital Multitrack Recorders  
Other Applications Requiring 24-Bit Audio  
768 f With Autodetect  
S
D
Accepts 16-, 20-, and 24-Bit Audio Data  
2
D
PCM Data Formats: Standard, I S, and  
DESCRIPTION  
Left-Justified  
The PCM1796 is a monolithic CMOS integrated circuit that  
includes stereo digital-to-analog converters and support  
circuitry in a small 28-lead SSOP package. The data  
converters use TI’s advanced segment DAC architecture  
to achieve excellent dynamic performance and improved  
tolerance to clock jitter. The PCM1796 provides balanced  
current outputs, allowing the user to optimize analog  
performance externally. The PCM1796 accepts PCM and  
DSD audio data formats, providing easy interfacing to  
audio DSP and decoder chips. The PCM1796 also  
interfaces with external digital filter devices (DF1704,  
DF1706, PMD200). Sampling rates up to 200 kHz are  
supported. A full set of user-programmable functions is  
accessible through an SPI or I2C serial control port, which  
supports register write and readback functions. The  
PCM1796 also supports the time division multiplexed  
command and audio (TDMCA) data format.  
D
D
DSD Format Interface Available  
Interface Available for Optional External  
Digital Filter or DSP  
2
D
TDMCA or Serial Port (SPI/I C)  
D
User-Programmable Mode Controls:  
− Digital Attenuation: 0 dB to –120 dB,  
0.5 dB/Step  
− Digital De-Emphasis  
− Digital Filter Rolloff: Sharp or Slow  
− Soft Mute  
− Zero Flag for Each Output  
D
D
Compatible With PCM1792 (Pins and Mode  
Controls)  
Dual Supply Operation:  
− 5-V Analog, 3.3-V Digital  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate  
precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to  
damage because very small parametric changes could cause the device not to meet its published specifications.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢛ ꢚ ꢖꢙ ꢁ ꢌꢋ ꢚꢔ ꢖ ꢒꢌꢒ ꢜꢝ ꢞꢟ ꢠ ꢡꢢ ꢣꢜꢟꢝ ꢜꢤ ꢥꢦ ꢠ ꢠ ꢧꢝꢣ ꢢꢤ ꢟꢞ ꢨꢦꢩ ꢪꢜꢥ ꢢꢣꢜ ꢟꢝ ꢫꢢ ꢣꢧꢬ ꢀꢠ ꢟꢫꢦ ꢥꢣꢤ  
ꢥ ꢟꢝ ꢞꢟꢠ ꢡ ꢣꢟ ꢤ ꢨꢧ ꢥ ꢜ ꢞꢜ ꢥ ꢢ ꢣꢜ ꢟꢝꢤ ꢨ ꢧꢠ ꢣꢭꢧ ꢣꢧ ꢠ ꢡꢤ ꢟꢞ ꢌꢧꢮ ꢢꢤ ꢋꢝꢤ ꢣꢠ ꢦꢡ ꢧꢝꢣ ꢤ ꢤꢣ ꢢꢝꢫ ꢢꢠ ꢫ ꢯ ꢢꢠ ꢠ ꢢ ꢝꢣꢰꢬ  
ꢀꢠ ꢟ ꢫꢦꢥ ꢣ ꢜꢟ ꢝ ꢨꢠ ꢟ ꢥ ꢧ ꢤ ꢤ ꢜꢝ ꢱ ꢫꢟ ꢧ ꢤ ꢝꢟꢣ ꢝꢧ ꢥꢧ ꢤꢤ ꢢꢠ ꢜꢪ ꢰ ꢜꢝꢥ ꢪꢦꢫ ꢧ ꢣꢧ ꢤꢣꢜ ꢝꢱ ꢟꢞ ꢢꢪ ꢪ ꢨꢢ ꢠ ꢢꢡ ꢧꢣꢧ ꢠ ꢤꢬ  
Copyright 2003, Texas Instruments Incorporated  
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ  
www.ti.com  
SLES100 − DECEMBER 2003  
ORDERING INFORMATION  
OPERATION  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA  
PRODUCT  
PACKAGE  
PACKAGE CODE  
PCM1796DB  
Tube  
PCM1796DB  
28-lead SSOP  
28DB  
−25°C to 85°C  
PCM1796  
PCM1796DBR  
Tape and reel  
ABSOLUTE MAXIMUM RATINGS  
(1)  
over operating free-air temperature range unless otherwise noted  
PCM1796  
V
V
1, V 2L, V 2R  
CC CC  
−0.3 V to 6.5 V  
−0.3 V to 4 V  
0.1 V  
CC  
DD  
Supply voltage  
Supply voltage differences: V 1, V 2L, V 2R  
CC CC CC  
Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND  
0.1 V  
(2) (2)  
(2)  
(2)  
LRCK, DATA, BCK, SCK, MSEL, RST, MS , MDI, MC, MDO , ZEROL , ZEROR  
(3) (3) (3) (3)  
ZEROL , ZEROR , MDO , MS  
–0.3 V to 6.5 V  
Digital input  
voltage  
–0.3 V to (V  
+ 0.3 V) < 4 V  
DD  
+ 0.3 V) < 6.5 V  
Analog input voltage  
–0.3 V to (V  
CC  
Input current (any pins except supplies)  
Ambient temperature under bias  
Storage temperature  
10 mA  
–40°C to 125°C  
–55°C to 150°C  
150°C  
Junction temperature  
Lead temperature (soldering)  
Package temperature (IR reflow, peak)  
260°C, 5 s  
260°C  
(1)  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2)  
(3)  
2
Input mode or I C mode  
2
Output mode except for I C mode  
ELECTRICAL CHARACTERISTICS  
all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V  
= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data unless  
A
CC  
CC  
CC  
DD  
S
S
otherwise noted  
PCM1796DB  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
TYP  
MAX  
RESOLUTION  
24  
Bits  
DATA FORMAT (PCM Mode)  
Audio data interface format  
Audio data bit length  
2
Standard, I S, left-justified  
16-, 20-, 24-bit selectable  
MSB first, twos complement  
Audio data format  
f
S
Sampling frequency  
10  
200  
kHz  
System clock frequency  
128, 192, 256, 384, 512, 768 f  
S
DATA FORMAT (DSD Mode)  
Audio data interface format  
Audio data bit length  
DSD (direct stream digital)  
1 Bit  
f
S
Sampling frequency  
2.8224  
MHz  
MHz  
System clock frequency  
2.8224  
11.2896  
2
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SLES100 − DECEMBER 2003  
ELECTRICAL CHARACTERISTICS (Continued)  
all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V  
= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data unless  
A
CC  
CC  
CC  
DD  
S
S
otherwise noted  
PCM1796DB  
TYP  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
MAX  
DIGITAL INPUT/OUTPUT  
Logic family  
TTL compatible  
V
V
2
IH  
IL  
Input logic level  
Input logic current  
Output logic level  
VDC  
µA  
0.8  
I
IH  
I
IL  
V
V
= V  
DD  
= 0 V  
10  
IN  
IN  
–10  
V
I
I
= −2 mA  
= 2 mA  
2.4  
OH  
OL  
OH  
OL  
VDC  
V
0.4  
(1)(2)  
DYNAMIC PERFORMANCE (PCM MODE)  
f
f
f
= 44.1 kHz  
= 96 kHz  
0.0005%  
0.001%  
0.0015%  
123  
0.001%  
S
S
S
THD+N at V  
OUT  
= 0 dB  
= 192 kHz  
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
120  
120  
116  
123  
Dynamic range  
dB  
dB  
EIAJ, A-weighted, f = 192 kHz  
123  
S
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
123  
123  
Signal-to-noise ratio  
Channel separation  
EIAJ, A-weighted, f = 192 kHz  
123  
S
f
S
f
S
f
S
= 44.1 kHz  
= 96 kHz  
119  
118  
dB  
dB  
= 192 kHz  
117  
Level Linearity Error  
V
OUT  
= −120 dB  
1
(1)(2)(3)  
DYNAMIC PERFORMANCE (MONO MODE)  
f
f
f
= 44.1 kHz  
= 96 kHz  
0.0005%  
0.001%  
0.0015%  
126  
S
S
S
THD+N at V  
OUT  
= 0 dB  
= 192 kHz  
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
126  
Dynamic range  
dB  
dB  
EIAJ, A-weighted, f = 192 kHz  
126  
S
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
126  
126  
Signal-to-noise ratio  
EIAJ, A-weighted, f = 192 kHz  
126  
S
(1)  
Filter condition:  
THD+N: 20-Hz HPF, 20-kHz AES17 LPF  
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF  
Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precisionin the  
averagingmode.  
(2)  
(3)  
Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 36.  
Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 38.  
Audio Precision and System Two are trademarks of Audio Precision, Inc.  
Other trademarks are the property of their respective owners.  
3
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SLES100 − DECEMBER 2003  
ELECTRICAL CHARACTERISTICS (Continued)  
all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V  
= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data unless  
A
CC  
CC  
CC  
DD  
S
S
otherwise noted  
PCM1796DB  
TYP  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
MAX  
(1) (2)  
DSD MODE DYNAMIC PERFORMANCE  
THD+N at FS  
(44.1 KHZ, 64 f )  
S
2 V rms  
0.0007%  
122  
Dynamic range  
–60 dB, EIAJ, A-weighted  
dB  
dB  
Signal-to-noise ratio  
ANALOG OUTPUT  
Gain error  
EIAJ, A-weighted  
122  
–7  
2
0.5  
0.5  
4
7
3
2
% of FSR  
% of FSR  
% of FSR  
mA p-p  
mA  
Gain mismatch, channel-to-channel  
Bipolar zero error  
–3  
–2  
At BPZ  
Output current  
Full scale (0 dB)  
At BPZ  
Center current  
–3.5  
DIGITAL FILTER PERFORMANCE  
De-emphasis error  
0.1  
dB  
FILTER CHARACTERISTICS–1: SHARP ROLLOFF  
0.0002 dB  
–3 dB  
0.454 f  
S
Pass band  
0.49 f  
S
Stop band  
0.546 f  
S
Pass-band ripple  
0.0002  
dB  
dB  
s
Stop-band attenuation  
Delay time  
Stop band = 0.546 f  
–98  
S
38/f  
S
FILTER CHARACTERISTICS–2: SLOW ROLLOFF  
0.001 dB  
–3 dB  
0.21 f  
S
Pass band  
0.448 f  
S
Stop band  
0.79 f  
S
Pass-band ripple  
Stop-band attenuation  
Delay time  
0.001  
dB  
dB  
s
Stop band = 0.732 f  
–80  
S
38/f  
S
(1)  
Filter condition:  
THD+N: 20-Hz HPF, 20-kHz AES17 LPF  
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF  
Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging  
mode.  
(2)  
Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 37.  
4
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SLES100 − DECEMBER 2003  
ELECTRICAL CHARACTERISTICS (Continued)  
all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V  
= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data unless  
A
CC  
CC  
CC  
DD  
S
S
otherwise noted  
PCM1796DB  
TYP  
PARAMETER  
POWER SUPPLY REQUIREMENTS  
TEST CONDITIONS  
UNIT  
MIN  
MAX  
V
V
V
V
3
3.3  
5
3.6  
VDC  
VDC  
DD  
CC  
CC  
CC  
1
Voltage range  
2L  
2R  
4.75  
5.25  
9
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
= 44.1 kHz  
= 96 kHz  
7
13  
I
mA  
mA  
mW  
DD  
= 192 kHz  
= 44.1 kHz  
= 96 kHz  
25  
(1)  
Supply current  
18  
23  
19  
I
CC  
= 192 kHz  
= 44.1 kHz  
= 96 kHz  
20  
115  
140  
180  
150  
(1)  
Power dissipation  
= 192 kHz  
TEMPERATURE RANGE  
Operation temperature  
Thermal resistance  
–25  
85  
°C  
θ
28-pin SSOP  
100  
°C/W  
JA  
(1)  
Input is BPZ data.  
PIN ASSIGNMENTS  
PCM1796  
(TOP VIEW)  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
ZEROL  
V
2L  
CC  
2
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
AGND3L  
3
I
I
L−  
L+  
OUT  
4
OUT  
5
AGND2  
6
V
V
V
1
CC  
7
SCK  
DGND  
L
R
COM  
COM  
REF  
8
9
V
I
DD  
MS  
MDI  
MC  
MDO  
RST  
10  
11  
12  
13  
14  
AGND1  
I
I
R−  
R+  
OUT  
OUT  
AGND3R  
2R  
V
CC  
5
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SLES100 − DECEMBER 2003  
Terminal Functions  
TERMINAL  
I/O  
DESCRIPTIONS  
NAME  
AGND1  
AGND2  
AGND3L  
AGND3R  
BCK  
PIN  
19  
24  
27  
16  
6
Analog ground (internal bias)  
Analog ground (internal bias)  
Analog ground (L-channel DACFF)  
Analog ground (R-channel DACFF)  
(1)  
Bit clock input  
I
(1)  
DATA  
5
I
Serial audio data input  
DGND  
8
Digital ground  
I
I
I
I
I
L+  
L–  
R+  
R–  
25  
26  
17  
18  
20  
4
O
O
O
O
L-channel analog current output+  
L-channel analog current output–  
R-channel analog current output+  
R-channel analog current output–  
Output current reference bias pin  
OUT  
OUT  
OUT  
OUT  
REF  
(1)  
Left and right clock (f ) input  
LRCK  
MC  
I
S
(1)  
12  
11  
13  
10  
3
I
Mode control clock input  
(1)  
Mode control data input  
MDI  
I
(3)  
Mode control readback data output  
MDO  
MS  
I/O  
I/O  
I
(2)  
Mode control chip-select input  
2
(1)  
MSEL  
RST  
SCK  
I C/SPI select  
(1)  
14  
7
I
Reset  
System clock input  
Analog power supply, 5 V  
(1)  
I
V
V
V
V
V
V
1
23  
28  
15  
22  
21  
9
CC  
CC  
CC  
2L  
2R  
Analog power supply (L-channel DACFF), 5 V  
Analog power supply (R-channel DACFF), 5 V  
L-channel internal bias decoupling pin  
R-channel internal bias decoupling pin  
Digital power supply, 3.3 V  
L
COM  
COM  
DD  
R
(2)  
ZEROL  
ZEROR  
1
I/O  
I/O  
Zero flag for L-channel  
Zero flag for R-channel  
(2)  
2
(1)  
(2)  
(3)  
Schmitt-trigger input, 5-V tolerant  
Schmitt-trigger input and output. 5-V tolerant input and CMOS output  
Schmitt-trigger input and output. 5-V tolerant input. In I C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS  
output.  
2
6
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SLES100 − DECEMBER 2003  
FUNCTIONAL BLOCK DIAGRAM  
I
I
L−  
L+  
OUT  
LRCK  
BCK  
Current  
Segment  
DAC  
V
OUT  
L
DATA  
Audio  
Data Input  
I/F  
OUT  
RST  
I/V and Filter  
 8  
V
L
COM  
Oversampling  
Digital  
Advanced  
Segment  
DAC  
Bias  
and  
Vref  
I
REF  
Filter  
and  
Function  
Control  
MDO  
V
COM  
R
Modulator  
MDI  
MC  
I
R−  
OUT  
OUT  
Function  
Control  
I/F  
MS  
Current  
Segment  
DAC  
V R  
OUT  
MSEL  
I
R+  
I/V and Filter  
ZEROL  
ZEROR  
System  
Clock  
Manager  
Zero  
Detect  
Power Supply  
7
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SLES100 − DECEMBER 2003  
TYPICAL PERFORMANCE CURVES  
DIGITAL FILTER  
Digital Filter Response  
AMPLITUDE  
AMPLITUDE  
vs  
vs  
FREQUENCY  
FREQUENCY  
0
−20  
0.0005  
0.0004  
0.0003  
−40  
0.0002  
−60  
0.0001  
−80  
0
−0.0001  
−100  
−120  
−140  
−160  
−0.0002  
−0.0003  
−0.0004  
−0.0005  
0
1
2
3
4
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
Frequency[× f ]  
Frequency[× f ]  
S
S
Figure 1. Frequency Response, Sharp Rolloff  
Figure 2. Pass-Band Ripple, Sharp Rolloff  
AMPLITUDE  
vs  
AMPLITUDE  
vs  
FREQUENCY  
FREQUENCY  
0
−20  
0
−2  
−4  
−40  
−6  
−60  
−8  
−80  
−10  
−12  
−14  
−16  
−18  
−20  
−100  
−120  
−140  
−160  
0
1
2
3
4
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
Frequency[× f ]  
Frequency[× f ]  
S
S
Figure 3. Frequency Response, Slow Rolloff  
Figure 4. Transition Characteristics, Slow Rolloff  
8
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SLES100 − DECEMBER 2003  
De-Emphasis Filter  
DE-EMPHASIS LEVEL  
DE-EMPHASIS ERROR  
vs  
vs  
FREQUENCY  
FREQUENCY  
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
0.5  
0.4  
0.3  
0.2  
0.1  
f
= 32 kHz  
f
S
= 32 kHz  
S
0.0  
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
0
2
4
6
8
10  
12  
14  
0
2
4
6
8
10  
12  
14  
f − Frequency − kHz  
f − Frequency − kHz  
Figure 5  
Figure 6  
DE-EMPHASIS LEVEL  
vs  
DE-EMPHASIS ERROR  
vs  
FREQUENCY  
FREQUENCY  
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
0.5  
0.4  
0.3  
0.2  
0.1  
f
= 44.1 kHz  
f
S
= 44.1 kHz  
S
0.0  
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
0
2
4
6
8
10 12 14 16 18 20  
0
2
4
6
8
10 12 14 16 18 20  
f − Frequency − kHz  
f − Frequency − kHz  
Figure 7  
Figure 8  
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De-Emphasis Filter (Continued)  
DE-EMPHASIS LEVEL  
vs  
DE-EMPHASIS ERROR  
vs  
FREQUENCY  
FREQUENCY  
0
0.5  
0.4  
0.3  
0.2  
0.1  
f
S
= 48 kHz  
f = 48 kHz  
S
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
0.0  
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
0
2
4
6
8
10 12 14 16 18 20 22  
0
2
4
6
8
10 12 14 16 18 20 22  
f − Frequency − kHz  
f − Frequency − kHz  
Figure 9  
Figure 10  
10  
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SLES100 − DECEMBER 2003  
ANALOG DYNAMIC PERFORMANCE  
Supply Voltage Characteristics  
TOTAL HARMONIC DISTORTION + NOISE  
DYNAMIC RANGE  
vs  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
126  
124  
122  
120  
118  
116  
0.01  
f
= 96 kHz  
= 48 kHz  
S
f
S
f
= 192 kHz  
S
0.001  
f
S
= 192 kHz  
f
S
= 48 kHz  
f
S
= 96 kHz  
5.25  
0.0001  
4.50  
4.75  
5.00  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
V
CC  
− Supply Voltage − V  
V
CC  
− Supply Voltage − V  
Figure 12  
Figure 11  
SIGNAL-to-NOISE RATIO  
vs  
CHANNEL SEPARATION  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
126  
124  
122  
120  
118  
116  
122  
120  
118  
116  
114  
112  
f
= 96 kHz  
S
f
= 96 kHz  
S
f
S
= 48 kHz  
f
S
= 192 kHz  
f
= 48 kHz  
S
f
S
= 192 kHz  
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
V
5.00  
5.25  
5.50  
V
− Supply Voltage − V  
− Supply Voltage − V  
CC  
CC  
Figure 13  
Figure 14  
NOTE: PCM mode, T = 25°C, V  
DD  
= 3.3 V, measurement circuit is Figure 36.  
A
11  
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Temperature Characteristics  
TOTAL HARMONIC DISTORTION + NOISE  
DYNAMIC RANGE  
vs  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
126  
124  
122  
120  
118  
116  
0.01  
f
= 96 kHz  
S
f
= 48 kHz  
S
f
= 192 kHz  
S
f
S
= 96 kHz  
0.001  
f
= 192 kHz  
S
f
S
= 48 kHz  
0.0001  
−50  
−25  
0
25  
50  
75  
100  
−50  
−25  
0
25  
50  
75  
100  
T
A
− Free-Air Temperature − °C  
T
A
− Free-Air Temperature − °C  
Figure 15  
Figure 16  
SIGNAL-to-NOISE RATIO  
vs  
CHANNEL SEPARATION  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
126  
124  
122  
120  
118  
116  
122  
120  
118  
116  
114  
112  
f
= 96 kHz  
S
f
= 96 kHz  
S
f
S
= 192 kHz  
f
= 48 kHz  
S
f
= 48 kHz  
S
f
= 192 kHz  
S
−50  
−25  
0
25  
50  
75  
100  
−50  
−25  
0
25  
50  
75  
100  
T
A
− Free-Air Temperature − °C  
T
A
− Free-Air Temperature − °C  
Figure 17  
Figure 18  
NOTE: PCM mode, V  
= 3.3 V, V = 5 V, measurement circuit is Figure 36.  
CC  
DD  
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AMPLITUDE  
vs  
AMPLITUDE  
vs  
FREQUENCY  
FREQUENCY  
0
−20  
0
−20  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−160  
−100  
−120  
−140  
−160  
0
2
4
6
8
10 12 14 16 18 20  
0
10 20 30 40 50 60 70 80 90 100  
f − Frequency − kHz  
f − Frequency − kHz  
NOTE: PCM mode, f = 48 kHz, 32768 point 8 average, T = 25°C, NOTE: PCM mode, f = 96 kHz, 32768 point 8 average, T = 25°C,  
S
A
S
A
V
DD  
= 3.3 V V  
= 5 V, measurement circuit is Figure 36.  
V
DD  
= 3.3 V V  
= 5 V, measurement circuit is Figure 36.  
CC  
CC  
Figure 19. −60-dB Output Spectrum, BW = 20 kHz Figure 20. −60-dB Output Spectrum, BW = 100 kHz  
AMPLITUDE  
TOTAL HARMONIC DISTORTION + NOISE  
vs  
vs  
FREQUENCY  
INPUT LEVEL  
0
10  
−20  
1
−40  
−60  
0.1  
−80  
0.01  
−100  
−120  
−140  
−160  
0.001  
0.0001  
0
2
4
6
8
10 12 14 16 18 20  
−90 −80 −70 −60 −50 −40 −30 −20 −10  
0
f − Frequency − kHz  
Input Level − dBFS  
NOTE: PCM mode, f = 48 kHz, T = 25°C, V  
DD  
= 3.3 V, V = 5 V, NOTE: DSD mode (FIR-2), 32768 point 8 average, T = 25°C,  
CC A  
S
A
measurement circuit is Figure 36.  
V
= 3.3 V, V = 5 V, measurement circuit is Figure 37.  
DD  
CC  
Figure 21. THD+N vs Input Level, PCM Mode  
Figure 22. −60-dB Output Spectrum, DSD Mode  
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SYSTEM CLOCK AND RESET FUNCTIONS  
System Clock Input  
The PCM1796 requires a system clock for operating the digital interpolation filters and advanced segment DAC  
modulators. The system clock is applied at the SCK input (pin 7). The PCM1796 has a system clock detection circuit  
that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system  
clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected  
as 128 f , the system clock frequency is required to be over 256 f .  
S
S
Figure 23 shows the timing requirements for the system clock input. For optimal performance, it is important to use  
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators  
is an excellent choice for providing the PCM1796 system clock.  
Table 1. System Clock Rates for Common Audio Sampling Frequencies  
SYSTEM CLOCK FREQUENCY (f  
) (MHz)  
SCK  
SAMPLING FREQUENCY  
128 f  
192 f  
256 f  
384 f  
512 f  
768 f  
S
S
S
S
S
S
(1)  
(1)  
32 kHz  
44.1 kHz  
48 kHz  
4.096  
6.144  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9344  
18.432  
36.864  
16.384  
24.576  
33.8688  
36.864  
(1)  
5.6488  
8.4672  
9.216  
22.5792  
24.576  
(1)  
6.144  
(1)  
49.152  
(1)  
73.728  
96 kHz  
12.288  
24.576  
18.432  
36.864  
(1)  
49.152  
(1)  
73.728  
(2)  
(2)  
192 kHz  
(1)  
(2)  
2
This system clock rate is not supported in I C fast mode.  
This system clock rate is not supported for the given sampling frequency.  
t
(SCKH)  
H
2.0 V  
0.8 V  
System Clock (SCK)  
L
t
(SCKL)  
t
(SCY)  
PARAMETERS  
MIN  
MAX UNITS  
t
System clock pulse cycle time  
13  
ns  
ns  
ns  
(SCY)  
t
System clock pulse duration, HIGH  
System clock pulse duration, LOW  
0.4t  
(SCY)  
(SCKH)  
t
0.4t  
(SCY)  
(SCKL)  
Figure 23. System Clock Input Timing  
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SLES100 − DECEMBER 2003  
Power-On and External Reset Functions  
The PCM1796 includes a power-on reset function. Figure 24 shows the operation of this function. With V  
> 2 V,  
DD  
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time  
> 2 V. After the initialization period, the PCM1796 is set to its default reset state, as described in the MODE  
V
DD  
CONTROL REGISTERS section of this data sheet.  
The PCM1796 also includes an external reset capability using the RST input (pin 14). This allows an external  
controller or master reset circuit to force the PCM1796 to initialize to its default reset state.  
Figure 25 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The  
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock  
periods. The external reset is especially useful in applications where there is a delay between the PCM1796 power  
up and system clock activation.  
V
DD  
2.4 V (Max)  
2.0 V (Typ)  
1.6 V (Min)  
Reset  
Reset Removal  
Internal Reset  
System Clock  
1024 System Clocks  
Figure 24. Power-On Reset Timing  
RST (Pin 14)  
1.4 V  
t
(RST)  
Reset  
Reset Removal  
Internal Reset  
System Clock  
1024 System Clocks  
PARAMETERS  
Reset pulse duration, LOW  
MIN  
MAX UNITS  
t
20  
ns  
(RST)  
Figure 25. External Reset Timing  
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AUDIO DATA INTERFACE  
Audio Serial Interface  
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the  
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio  
interface. Serial data is clocked into the PCM1796 on the rising edge of BCK. LRCK is the serial audio left/right word  
clock.  
The PCM1796 requires the synchronization of LRCK and system clock, but does not need a specific phase relation  
between LRCK and system clock.  
If the relationship between LRCK and system clock changes more than 6 BCK, internal operation is initialized within  
1/f and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock  
S
is completed.  
PCM Audio Data Formats and Timing  
2
The PCM1796 supports industry-standard audio data formats, including standard right-justified, I S, and  
left-justified. The data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0],  
2
in control register 18. The default data format is 24-bit I S. All formats require binary 2s complement, MSB-first audio  
data. Figure 26 shows a detailed timing diagram for the serial audio interface.  
1.4 V  
1.4 V  
1.4 V  
LRCK  
BCK  
t
t
(BCL)  
t
(BCH)  
(LB)  
t
t
(BCY)  
(BL)  
DATA  
t
t
(DS)  
(DH)  
PARAMETERS  
MIN MAX UNITS  
t
t
t
t
t
t
t
BCK pulse cycle time  
BCK pulse duration, LOW  
BCK pulse duration, HIGH  
BCK rising edge to LRCK edge  
LRCK edge to BCK rising edge  
DATA setup time  
70  
30  
30  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(BCY)  
(BCL)  
(BCH)  
(BL)  
(LB)  
(DS)  
DATA hold time  
(DH)  
LRCK clock data  
50% 2 bit clocks  
Figure 26. Timing of Audio Interface  
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(1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW  
1/f  
S
LRCK  
R-Channel  
L-Channel  
BCK  
Audio Data Word = 16-Bit  
14 15 16  
1
2
15 16  
LSB  
1
2
15 16  
DATA  
MSB  
Audio Data Word = 20-Bit  
18 19 20  
1
2
19 20  
LSB  
1
2
19 20  
23 24  
DATA  
MSB  
Audio Data Word = 24-Bit  
22 23 24  
1
2
23 24  
LSB  
1
2
DATA  
MSB  
(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW  
1/f  
S
LRCK  
BCK  
R-Channel  
L-Channel  
Audio Data Word = 24-Bit  
DATA  
1
2
23 24  
LSB  
1
2
23 24  
1
2
MSB  
2
(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH  
1/f  
S
LRCK  
L-Channel  
R-Channel  
BCK  
Audio Data Word = 16-Bit  
DATA  
1
1
2
2
15 16  
LSB  
1
2
2
15 16  
1
1
2
2
MSB  
MSB  
Audio Data Word = 24-Bit  
DATA  
23 24  
LSB  
1
23 24  
Figure 27. Audio Data Input Formats  
17  
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SLES100 − DECEMBER 2003  
External Digital Filter Interface and Timing  
The PCM1796 supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which  
allows the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and DF1706, the  
Pacific Microsonics PMD200, or a programmable digital signal processor.  
In the external DF mode, LRCK (pin 4), BCK (pin 6) and DATA (pin 5) are defined as WDCK, the word clock; BCK,  
the bit clock; and DATA, the monaural data. The external digital filter interface is selected by using the DFTH bit of  
control register 20, which functions to bypass the internal digital filter of the PCM1796.  
When the DFMS bit of control register 19 is set, the PCM1796 can process stereo data. In this case, ZEROL (pin 1)  
and ZEROR (pin 2) are defined as L-channel data and R-channel data input, respectively.  
Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL  
DIGITAL FILTER INTERFACE section of this data sheet.  
Direct Stream Digital (DSD) Format Interface and Timing  
The PCM1796 supports the DSD format interface operation, which includes out-of-band noise filtering using an  
internal analog FIR filter. For DSD operation, SCK (pin 7) is redefined as BCK, DATA (pin 5) as DATAL (left channel  
audio data), and LRCK (pin 4) as DATAR (right channel audio data). BCK (pin 6) must be forced low in the DSD mode.  
The DSD format interface is activated by setting the DSD bit of control register 20.  
Detailed information for the DSD mode is provided in the APPLICATION FOR DSD FORMAT (DSD MODE)  
INTERFACE section of this data sheet.  
TDMCA Interface  
The PCM1796 supports the time-division-multiplexed command and audio (TDMCA) data format to enable control  
of and communication with a number of external devices over a single serial interface.  
Detailed information for the TDMCA format is provided in the TDMCA INTERFACE FORMAT section of this data  
sheet.  
FUNCTION DESCRIPTIONS  
Zero Detect  
The PCM1796 has a zero-detect function. When the PCM1796 detects the zero conditions as shown in Table 2, the  
PCM1796 sets ZEROL (pin 1) and ZEROR (pin 2) to HIGH.  
Table 2. Zero Conditions  
MODE  
DETECTING CONDITION AND TIME  
PCM  
DATA is continuously LOW for 1024 LRCKs.  
External DF Mode DATA is continuously LOW for 8 × 1024 WDCKs.  
DZ0  
There are an equal number of 1s and 0s in every 8 bits of DSD  
input data for 23 ms.  
DSD  
DZ1  
The input data is 1001 0110 continuously for 23 ms.  
18  
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SLES100 − DECEMBER 2003  
SERIAL CONTROL INTERFACE  
2
The PCM1796 supports SPI and I C that sets mode control registers as shown in Table 4. This serial control interface  
2
is selected by MSEL (pin 3), SPI is activated when MSEL is set to LOW, and I C is activated when MSEL is set to  
HIGH.  
SPI Interface  
The SPI interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio interface and  
the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The  
control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output,  
used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers;  
MC is the serial bit clock, used to shift data in and out of the control port, and MS is the mode control enable, used  
to enable the internal mode register access.  
Register Read/Write Operation  
All read/write operations for the serial control port use 16-bit data words. Figure 28 shows the control data word  
format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For  
read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or  
address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to,  
or the data that was read from, the register specified by IDX[6:0].  
Figure 29 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1  
state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen  
clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data  
on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on  
MDO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the  
indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to 1 once.  
LSB  
D0  
MSB  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Register Index (or Address)  
Register Data  
Figure 28. Control Data Word Format for MDI  
MS  
MC  
MDI  
MDO  
R/W A6 A5 A4 A3  
A2 A1 A0 D7 D6 D5 D4  
D3 D2 D1 D0  
High Impedance  
D7 D6 D5 D4  
D3 D2 D1 D0  
When Read Mode is Instructed  
NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14−8 are used for the register  
address. Bits 7–0 are used for register data.  
Figure 29. Serial Control Format  
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t
(MHH)  
MS  
1.4 V  
t
t
(MCL)  
(MSS)  
t
t
(MSH)  
(MCH)  
MC  
1.4 V  
1.4 V  
t
(MCY)  
LSB  
MDI  
t
t
(MDS)  
(MOS)  
t
(MDH)  
MDO  
50% of V  
DD  
PARAMETER  
MIN  
100  
40  
MAX UNITS  
t
t
t
t
t
t
t
t
t
MC pulse cycle time  
MC low-level time  
MC high-level time  
MS high-level time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(MCY)  
(MCL)  
(MCH)  
(MHH)  
(MSS)  
(MSH)  
(MDH)  
(MDS)  
(MOS)  
40  
80  
MS falling edge to MC rising edge  
(1)  
15  
MS hold time  
15  
MDI hold time  
15  
MDI setup time  
15  
MC falling edge to MDO stable  
30  
ns  
(1)  
MC rising edge for LSB to MS rising edge  
Figure 30. Control Interface Timing  
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SLES100 − DECEMBER 2003  
2
I C INTERFACE  
2
The PCM1796 supports the I C serial bus and the data transmission protocol for standard and fast mode as a slave  
2
device. This protocol is explained in I C specification 2.0.  
2
In I C mode, the control terminals are changed as follows.  
TERMINAL NAME  
TDMCA NAME  
ADR0  
PROPERTY  
Input  
DESCRIPTION  
2
I C address 0  
MS  
MDI  
MC  
2
I C address 1  
ADR1  
Input  
2
I C clock  
SCL  
Input  
2
I C data  
MDO  
SDA  
Input/output  
Slave Address  
MSB  
1
LSB  
R/W  
0
0
1
1
ADR1  
ADR0  
The PCM1796 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset  
to 10011. The next two bits of the address byte are the device select bits which can be user-defined by the ADR1  
and ADR0 terminals. A maximum of four PCM1796s can be connected on the same bus at one time. Each PCM1796  
responds when it receives its own slave address.  
Packet Protocol  
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data  
if write or acknowledge if read, and stop condition. The PCM1796 supports only slave receivers and slave  
transmitters.  
SDA  
SCL  
St  
1−7  
8
9
1−8  
9
1−8  
9
9
Sp  
Slave Address R/W  
ACK  
DATA  
ACK  
DATA  
ACK  
ACK  
R/W: Read Operation if 1; Otherwise, Write Operation  
ACK: Acknowledgement of a Byte if 0  
NACK: Not Acknowledgement if 1  
DATA: 8 Bits (Byte)  
Start  
Condition  
Stop  
Condition  
Write Operation  
Transmitter  
Data Type  
M
M
M
S
M
S
M
S
S
M
St  
Slave Address  
W
ACK  
DATA  
ACK  
DATA  
ACK  
ACK  
Sp  
Read Operation  
Transmitter  
Data Type  
M
M
M
S
S
M
S
M
M
M
St  
Slave Address  
R
ACK  
DATA  
ACK  
DATA  
ACK  
NACK  
Sp  
M: Master Device  
S: Slave Device  
St: Start Condition  
Sp: Stop Condition  
W: Write  
R: Read  
ACK: Acknowledge  
NACK: Not Acknowledge  
2
Figure 31. Basic I C Framework  
21  
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Write Register  
A master can write to any PCM1796 registers using single or multiple accesses. The master sends a PCM1796 slave  
address with a write bit, a register address, and the data. If multiple access is required, the address is that of the  
starting register, followed by the data to be transferred. When the data are received properly, the index register is  
incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x00. When undefined  
registers are accessed, the PCM1796 does not send an acknowledgement. Figure 32 is a diagram of the write  
operation.  
Transmitter  
M
M
M
M
S
M
S
M
S
M
S
S
Data Type St  
Sp  
Slave Address  
W
ACK  
ACK  
ACK  
ACK  
ACK  
Reg Address  
Write Data 1  
Write Data 2  
M: Master Device  
S: Slave Device  
St: Start Condition  
Sp: Stop Condition ACK: Acknowledge W: Write  
Figure 32. Write Operation  
Read Register  
A master can read the PCM1796 register. The value of the register address is stored in an indirect index register in  
advance. The master sends a PCM1796 slave address with a read bit after storing the register address. Then the  
PCM1796 transfers the data which the index register points to. When the data are transferred during a multiple  
access, the index register is incremented by 1 automatically. (When first going into read mode immediately following  
a write, the index register is not incremented. The master can read the register that was previously written.) When  
the index register reaches 0x7F, the next value is 0x00. The PCM1796 outputs some data when the index register  
is 0x10 to 0x1F, even if it is not defined in Table 4. Figure 33 is a diagram of the read operation.  
Transmitter  
M
M
M
M
S
M
S
M
M
M
S
S
M
M
Data Type St  
Sp  
Slave Address  
W
ACK  
ACK Sr  
R
ACK  
ACK  
NACK  
Reg Address  
Slave Address  
Data  
M: Master Device  
St: Start Condition  
W: Write  
S: Slave Device  
Sr: Repeated Start Condition Sp: Stop Condition  
R: Read  
ACK: Acknowledge  
NACK: Not Acknowledge  
Figure 33. Read Operation  
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Noise Suppression  
The PCM1796 incorporates noise suppression using the system clock (SCK). However, there must be no more than  
two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast  
mode. However, it works incorrectly in the following conditions.  
Case 1:  
1. t  
2. t  
> 120 ns (t  
: period of SCK)  
(SCK)  
(SCK)  
+ t  
< t  
(D−HD)  
× 5  
(HI)  
(SCK)  
3. Spike noise exists on the first half of the SCL HIGH pulse.  
4. Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.  
SCL  
Noise  
SDA  
When these conditions occur at the same time, the data is recognized as LOW.  
Case 2:  
1. t  
2. t  
> 120 ns  
(SCK)  
or t  
< t  
× 5  
(SCK)  
(S−HD)  
(RS−HD)  
3. Spike noise exists on both SCL and SDA during the hold time.  
SCL  
Noise  
SDA  
When these conditions occur at the same time, the PCM1796 fails to detect a start condition.  
Case 3:  
1. t  
2. t  
< 50 ns  
(SCK)  
(SP)  
> t  
(SCK)  
3. Spike noise exists on SCL just after SCL goes LOW.  
4. Spike noise exists on SDA just before SCL goes LOW.  
SCL  
SDA  
Noise  
When these conditions occur at the same time, the PCM1796 erroneously detects a start or stop condition.  
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SLES100 − DECEMBER 2003  
TIMING DIAGRAM  
Start  
Repeated Start  
(D-HD)  
Stop  
t
t
(SDA-F)  
t
t
t
t
(P-SU)  
(BUF)  
(D-SU)  
(SDA-R)  
SDA  
t
t
t
(SP)  
(SCL-R)  
(RS-HD)  
t
(LOW)  
SCL  
t
t
t
(RS-SU)  
(S-HD)  
(HI)  
t
(SCL-F)  
TIMING CHARACTERISTICS  
PARAMETER  
CONDITIONS  
Standard  
Fast  
MIN MAX  
100  
400  
4.7  
UNIT  
f
t
t
t
t
SCL clock frequency  
kHz  
(SCL)  
(BUF)  
(LOW)  
(HI)  
Standard  
Fast  
Bus free time between stop and start conditions  
Low period of the SCL clock  
High period of the SCL clock  
Setup time for (repeated) start condition  
Hold time for (repeated) start condition  
Data setup time  
µs  
µs  
1.3  
Standard  
Fast  
4.7  
1.3  
Standard  
Fast  
4
µs  
ns  
µs  
ns  
µs  
ns  
600  
4.7  
Standard  
Fast  
(RS-SU)  
600  
4
t
t
Standard  
Fast  
(S-HD)  
600  
250  
100  
(RS-HD)  
Standard  
Fast  
t
t
t
t
t
t
t
t
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(D-SU)  
Standard  
Fast  
0
0
900  
900  
Data hold time  
(D-HD)  
Standard  
Fast  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
20 + 0.1 C  
1000  
300  
B
B
B
B
B
B
B
B
B
Rise time of SCL signal  
(SCL-R)  
(SCL-R1)  
(SCL-F)  
(SDA-R)  
(SDA-F)  
(P-SU)  
Standard  
Fast  
1000  
300  
Rise time of SCL signal after a repeated start condition and after an  
acknowledge bit  
Standard  
Fast  
1000  
300  
Fall time of SCL signal  
Rise time of SDA signal  
Fall time of SDA signal  
Setup time for stop condition  
Standard  
Fast  
1000  
300  
Standard  
Fast  
1000  
300  
B
4
Standard  
Fast  
µs  
ns  
pF  
ns  
V
600  
C
Capacitive load for SDA and SCL line  
Pulse duration of suppressed spike  
400  
50  
(B)  
t
Fast  
(SP)  
V
NH  
Noise margin at high level for each connected device (including hysteresis)  
0.2 V  
DD  
2
Figure 34. Timing Definition on the I C Bus  
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MODE CONTROL REGISTERS  
User-Programmable Mode Controls  
The PCM1796 includes a number of user-programmable functions which are accessed via mode control registers.  
The registers are programmed using the serial control interface, which is previously discussed in the SPI Interface  
2
and I C INTERFACE sections of this data sheet. Table 3 lists the available mode-control functions, along with their  
default reset conditions and associated register index.  
Table 3. User-Programmable Function Controls  
DF  
BYPASS  
FUNCTION  
Digital attenuation control  
DEFAULT  
REGISTER  
BIT  
PCM  
DSD  
0 dB  
Attenuation disabled  
Register 16 ATL[7:0] (for L-ch)  
Register 17 ATR[7:0] (for R-ch)  
yes  
0 dB to –120 dB and mute, 0.5 dB step  
Attenuation load control  
Disabled, enabled  
Register 18 ATLD  
yes  
yes  
2
Input audio data format selection  
24-bit I S format  
Register 18 FMT[2:0]  
yes  
16-, 20-, 24-bit standard (right-justified) format  
24-bit MSB-first left-justified format  
2
16-/24-bit I S format  
(1)  
yes  
Sampling rate selection for de-emphasis  
Disabled,44.1 kHz, 48 kHz, 32 kHz  
De-emphasis disabled  
De-emphasis disabled  
Mute disabled  
Register 18 DMF[1:0]  
Register 18 DME  
Register 18 MUTE  
Register 19 REV  
yes  
yes  
yes  
yes  
yes  
yes  
De-emphasis control  
Disabled, enabled  
Soft mute control  
Soft mute disabled, enabled  
Output phase reversal  
Normal, reverse  
Normal  
yes  
yes  
Attenuation speed selection  
×1 f  
Register 19 ATS[1:0]  
S
×1f , ×(1/2)f , ×(1/4)f , ×(1/8)f  
S
S
S
S
DAC operation control  
Enabled, disabled  
DAC operation enabled Register 19 OPE  
yes  
yes  
yes  
Stereo DF bypass mode select  
Monaural, stereo  
Monaural  
Register 19 DFMS  
Register 19 FLT  
Digital filter rolloff selection  
Sharp rolloff, slow rolloff  
Sharp rolloff  
Disabled  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
Infinite zero mute control  
Disabled, enabled  
Register 19 INZD  
Register 20 SRST  
Register 20 DSD  
Register 20 DFTH  
Register 20 MONO  
Register 20 CHSL  
Register 20 OS[1:0]  
yes  
yes  
System reset control  
Reset operation , normal operation  
Normal operation  
Disabled  
yes  
yes  
DSD interface mode control  
DSD enabled, disabled  
Digital-filter bypass control  
DF enabled, DF bypass  
DF enabled  
Stereo  
yes  
yes  
yes  
yes  
yes  
Monaural mode selection  
Stereo, monaural  
yes  
yes  
Channel selection for monaural mode data  
L-channel, R-channel  
L-channel  
(2)  
yes  
Delta-sigma oversampling rate selection  
×64 f  
S
×64 f , ×128 f , ×32 f  
S
S
S
PCM zero output enable  
Enabled  
Disabled  
Register 21 PCMZ  
Register 21 DZ[1:0]  
DSD zero output enable  
yes  
yes  
FUNCTION AVAILABLE ONLY FOR READ  
Zero detection flag  
Not zero, zero detected  
Not zero = 0  
Zero detected = 1  
Register 22 ZFGL (for L-ch)  
ZFGR (for R-ch)  
yes  
yes  
yes  
Device ID (at TDMCA)  
Register 23 ID[4:0]  
(1)  
(2)  
When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.  
When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.  
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Register Map  
The mode control register map is shown in Table 4. Registers 16–21 include an R/W bit, which determines whether  
a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.  
Table 4. Mode Control Register Map  
B15  
Register 16 R/W  
Register 17 R/W  
Register 18 R/W  
Register 19 R/W  
Register 20 R/W  
Register 21 R/W  
B14  
0
B13  
0
B12  
1
B11  
0
B10 B9 B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ATL7 ATL6 ATL5 ATL4  
ATL3  
ATL2  
ATL1  
ATL0  
0
0
1
0
ATR7 ATR6 ATR5 ATR4 ATR3  
ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE  
ATR2 ATR1 ATR0  
0
0
1
0
0
0
1
0
REV ATS1 ATS0 OPE  
RSV  
DFMS  
FLT  
OS1  
DZ0  
INZD  
OS0  
0
0
1
0
RSV SRST DSD DFTH MONO CHSL  
0
0
1
0
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
RSV  
ID4  
RSV  
RSV  
ID3  
DZ1  
RSV  
ID2  
PCMZ  
Register 22  
Register 23  
R
R
0
0
1
0
ZFGR ZFGL  
0
0
1
0
ID1  
ID0  
Register Definitions  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
Register 16 R/W  
0
0
1
0
0
0
0
ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0  
Register 17 R/W  
0
0
1
0
0
0
1
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
ATx[7:0]: Digital Attenuation Level Setting  
These bits are available for read and write.  
Default value: 1111 1111b  
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB  
steps. Alternatively, the attenuator can be set to infinite attenuation (or mute).  
The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control  
register 18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The  
attenuation level can be set using the following formula:  
Attenuation level (dB) = 0.5 dB (ATx[7:0]  
– 255)  
DEC  
where ATx[7:0]  
= 0 through 255  
DEC  
For ATx[7:0]  
levels for various settings:  
= 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation  
DEC  
ATx[7:0]  
1111 1111b  
1111 1110b  
1111 1101b  
L
Decimal Value  
Attenuation Level Setting  
255  
254  
253  
L
0 dB, no attenuation (default)  
–0.5 dB  
–1.0 dB  
L
0001 0000b  
0000 1111b  
0000 1110b  
L
16  
15  
14  
L
–119.5 dB  
–120.0 dB  
Mute  
L
0000 0000b  
0
Mute  
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B15 B14 B13 B12 B11 B10  
Register 18 R/W  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
1
0
0
1
0
ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
ATLD: Attenuation Load Control  
This bit is available for read and write.  
Default value: 0  
ATLD = 0  
ATLD = 1  
Attenuation control disabled (default)  
Attenuation control enabled  
The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0,  
the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and  
17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.  
FMT[2:0]: Audio Interface Data Format  
These bits are available for read and write.  
Default value: 101  
FMT[2:0]  
000  
Audio Data Format Selection  
16-bit standard format, right-justified data  
20-bit standard format, right-justified data  
24-bit standard format, right-justified data  
24-bit MSB-first, left-justified format data  
001  
010  
011  
2
100  
16-bit I S format data  
2
101  
24-bit I S format data (default)  
110  
Reserved  
Reserved  
111  
The FMT[2:0] bits are used to select the data format for the serial audio interface.  
For the external digital filter interface mode (DFTH mode), this register is operated as shown in the APPLICATION  
FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet.  
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function  
These bits are available for read and write.  
Default value: 00  
DMF[1:0]  
De-Emphasis Sampling Frequency Selection  
00  
01  
10  
11  
Disabled (default)  
48 kHz  
44.1 kHz  
32 kHz  
The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is  
enabled by setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES  
section of this data sheet.  
For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter  
response plots are shown in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data  
sheet.  
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DME: Digital De-Emphasis Control  
This bit is available for read and write.  
Default value: 0  
DME = 0  
DME = 1  
De-emphasis disabled (default)  
De-emphasis enabled  
The DME bit is used to enable or disable the de-emphasis function for both channels.  
MUTE: Soft Mute Control  
This bit is available for read and write.  
Default value: 0  
MUTE = 0  
MUTE = 1  
Soft mute disabled (default)  
Soft mute enabled  
The MUTE bit is used to enable or disable the soft mute function for both channels.  
Soft mute is operated as a 256-step attenuator. The speed for each step to dB (mute) is determined by the  
attenuation rate selected in the ATS register.  
B15 B14 B13 B12 B11 B10  
Register 19 R/W  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
1
0
0
1
1
REV ATS1 ATS0 OPE  
RSV DFMS  
FLT  
INZD  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
REV: Output Phase Reversal  
This bit is available for read and write.  
Default value: 0  
REV = 0  
REV = 1  
Normal output (default)  
Inverted output  
The REV bit is used to invert the output phase for both channels.  
ATS[1:0]: Attenuation Rate Select  
These bits are available for read and write.  
Default value: 00  
ATS[1:0]  
Attenuation Rate Selection  
Every LRCK (default)  
LRCK/2  
00  
01  
10  
11  
LRCK/4  
LRCK/8  
The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level  
transitions.  
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OPE: DAC Operation Control  
This bit is available for read and write.  
Default value: 0  
OPE = 0  
OPE = 1  
DAC operation enabled (default)  
DAC operation disabled  
The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces  
them to the bipolar zero level (BPZ) even if audio data is present on the input.  
DFMS: Stereo DF Bypass Mode Select  
This bit is available for read and write.  
Default value: 0  
DFMS = 0  
DFMS = 1  
Monaural (default)  
Stereo input enabled  
The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is set  
to 0, the pin for the input data is DATA (pin 5) only, therefore the PCM1796 operates as a monaural DAC. When DFMS  
is set to 1, the PCM1796 can operate as a stereo DAC with inputs of L-channel and R-channel data on ZEROL (pin 1)  
and ZEROR (pin 2), respectively.  
FLT: Digital Filter Rolloff Control  
This bit is available for read and write.  
Default value: 0  
FLT = 0  
FLT = 1  
Sharp rolloff (default)  
Slow rolloff  
The FLT bit is used to select the digital filter rolloff characteristic. The filter responses for these selections are shown  
in the TYPICAL PERFORMANCE CURVES section of this data sheet.  
INZD: Infinite Zero Detect Mute Control  
This bit is available for read and write.  
Default value: 0  
INZD = 0  
INZD = 1  
Infinite zero detect mute disabled (default)  
Infinite zero detect mute enabled  
The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to 1 forces muted analog outputs  
to hold a bipolar zero level when the PCM1796 detects a zero condition in both channels. The infinite zero detect  
mute function is not available in the DSD mode.  
B15 B14 B13 B12 B11 B10  
Register 20 R/W  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
1
0
1
0
0
RSV SRST DSD DFTH MONO CHSL OS1  
OS0  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
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SRST: System Reset Control  
This bit is available for write only.  
Default value: 0  
SRST = 0  
SRST = 1  
Normal operation (default)  
System reset operation (generate one reset pulse)  
The SRST bit is used to reset the PCM1796 to the initial system condition.  
DSD: DSD Interface Mode Control  
This bit is available for read and write.  
Default value: 0  
DSD = 0  
DSD = 1  
DSD interface mode disabled (default)  
DSD interface mode enabled  
The DSD bit is used to enable or disable the DSD interface mode.  
DFTH: Digital Filter Bypass (or Through Mode) Control  
This bit is available for read and write.  
Default value: 0  
DFTH = 0  
DFTH = 1  
Digital filter enabled (default)  
Digital filter bypassed for external digital filter  
The DFTH bit is used to enable or disable the external digital filter interface mode.  
MONO: Monaural Mode Selection  
This bit is available for read and write.  
Default value: 0  
MONO = 0  
MONO = 1  
Stereo mode (default)  
Monaural mode  
The MONO function is used to change operation mode from the normal stereo mode to the monaural mode. When  
the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel  
selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately  
following.  
CHSL: Channel Selection for Monaural Mode  
This bit is available for read and write.  
Default value: 0  
CHSL = 0  
CHSL = 1  
L-channel selected (default)  
R-channel selected  
This bit is available when MONO = 1.  
The CHSL bit selects L-channel or R-channel data to be used in monaural mode.  
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OS[1:0]: Delta-Sigma Oversampling Rate Selection  
These bits are available for read and write.  
Default value: 00  
OS[1:0]  
00  
Operation Speed Select  
64 times f (default)  
S
01  
32 times f  
S
10  
128 times f  
Reserved  
S
11  
The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the  
designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example,  
programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation  
allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 f oversampling rate is not  
S
available at sampling rates above 100 kHz. If the 128-f oversampling rate is selected, a system clock of more than  
S
256 f is required.  
S
In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter.  
B15 B14 B13 B12 B11 B10  
Register 21 R/W  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
1
0
1
0
1
RSV  
RSV  
RSV  
RSV  
RSV  
DZ1  
DZ0 PCMZ  
R/W: Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
DZ[1:0]: DSD Zero Output Enable  
These bits are available for read and write.  
Default value: 00  
DZ[1:0]  
00  
Zero Output Enable  
Disabled (default)  
Even pattern detect  
96h pattern detect  
01  
1x  
The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode.  
PCMZ: PCM Zero Output Enable  
These bits are available for read and write.  
Default value: 1  
PCMZ = 0  
PCMZ = 1  
PCM zero output disabled  
PCM zero output enabled (default)  
The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode.  
B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
Register 22  
R
0
0
1
0
1
1
0
RSV  
RSV  
RSV  
RSV  
RSV  
RSV ZFGR ZFGL  
R: Read Mode Select  
Value is always 1, specifying the readback mode.  
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ZFGx: Zero-Detection Flag  
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.  
Default value: 00  
ZFGx = 0  
ZFGx = 1  
Not zero  
Zero detected  
These bits show zero conditions. Their status is the same as that of the zero flags at ZEROL (pin 1) and ZEROR  
(pin 2). See Zero Detect in the FUNCTION DESCRIPTIONS section.  
B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
Register 23  
R
0
0
1
0
1
1
1
RSV  
RSV  
RSV  
ID4  
ID3  
ID2  
ID1  
ID0  
R: Read Mode Select  
Value is always 1, specifying the readback mode.  
ID[4:0]: Device ID  
The ID[4:0] bits hold a device ID in the TDMCA mode.  
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APPLICATION INFORMATION  
TYPICAL CONNECTION DIAGRAM IN PCM MODE  
C
f
5 V  
R
R
f
0.1 µF  
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
V
2L  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
10 µF  
CC  
+
AGND3L  
Differential  
to  
I L−  
OUT  
3
C
f
Single  
Converter  
With  
Low-Pass  
Filter  
V
OUT  
L-Channel  
I
L+  
4
OUT  
f
PCM  
Audio  
Data  
5 V  
AGND2  
5
+
V
1
CC  
6
Source  
10 µF  
SCK  
V L  
COM  
7
+
C
f
PCM1796  
DGND  
V
COM  
R
8
R
R
0.1 µF  
47 µF  
10 kΩ  
f
V
DD  
I
REF  
9
+
MS  
AGND1  
10  
11  
12  
13  
14  
Differential  
to  
Single  
Converter  
With  
Low-Pass  
Filter  
MDI  
MC  
I
R−  
R+  
C
OUT  
f
V
OUT  
R-Channel  
Controller  
I
OUT  
f
0.1 µF  
5 V  
AGND3R  
MDO  
RST  
+
V
CC  
2R  
10 µF  
3.3 V  
+
10 µF  
Figure 35. Typical Application Circuit for Standard PCM Audio Operation  
APPLICATION CIRCUIT  
The design of the application circuit is very important in order to actually realize the high S/N ratio of which the  
PCM1796 is capable. This is because noise and distortion that are generated in an application circuit are not  
negligible.  
In the third-order LPF circuit of Figure 36, the output level is 2.1 V rms and 123 dB S/N is achieved.  
Figure 37 shows a circuit for the DSD mode, which is a fourth-order LPF in order to reduce the out-of-band noise.  
I/V Section  
The current of the PCM1796 on each of the output pins (I  
L+, I  
L–, I  
R+, I  
R–) is 4 mA p-p at 0 dB (full  
OUT  
OUT  
OUT  
OUT  
scale). The voltage output level of the I/V converter (Vi) is given by following equation:  
Vi = 4 mA p−p × R (R : feedback resistance of I/V converter)  
f
f
An NE5534 op amp is recommended for the I/V circuit to obtain the specified performance. Dynamic performance  
such as the gain bandwidth, settling time, and slew rate of the op amp affects the audio dynamic performance of the  
I/V section.  
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Differential Section  
The PCM1796 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each  
channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter  
function.  
The op amp recommended for the differential circuit is the low-noise type.  
C
1
2700 pF  
R
1
820 Ω  
V
CC  
V
CC  
C
3
C
11  
0.1 µF  
8200 pF  
R
200 Ω  
5
C
15  
0.1 µF  
C
22 pF  
17  
C
22 pF  
19  
7
5
R
220 Ω  
R
7
7
2
3
8
6
3
+
I −  
OUT  
5
180 Ω  
R
100 Ω  
2
3
8
6
9
+
C
5
U
1
27000 pF  
NE5534  
U
4
3
NE5534  
4
R
4
R
8
180 Ω  
C
12  
0.1 µF  
220 Ω  
R
6
200 Ω  
C
16  
0.1 µF  
C
4
V
EE  
8200 pF  
V
EE  
C
2
2700 pF  
R
2
820 Ω  
V
CC  
C
13  
0.1 µF  
C
22 pF  
18  
7
5
2
3
8
6
+
I +  
OUT  
U
2
NE5534  
4
V
V
= 15 V  
= −15 V  
= 50 kHz  
CC  
EE  
C
14  
0.1 µF  
f
c
V
EE  
Figure 36. Measurement Circuit for PCM  
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C
1
2200 pF  
R
1
820 Ω  
V
CC  
V
CC  
C
5
C
11  
0.1 µF  
8200 pF  
R
150 Ω  
5
C
15  
0.1 µF  
C
22 pF  
17  
C
22 pF  
19  
7
5
R
91 Ω  
R
75 Ω  
R
120 Ω  
7
2
3
8
6
3
8
10  
+
I −  
OUT  
5
R
100 Ω  
2
3
8
6
7
+
C
3
C
4
U
1
22000 pF  
27000 pF  
R
11  
NE5534  
U
4
3
NE5534  
4
R
4
R
9
75 Ω  
C
12  
0.1 µF  
91 Ω  
120 Ω  
R
6
150 Ω  
C
16  
0.1 µF  
C
6
V
EE  
8200 pF  
V
EE  
C
2
2200 pF  
R
2
820 Ω  
V
CC  
C
13  
0.1 µF  
C
22 pF  
18  
7
5
2
3
8
6
+
I +  
OUT  
U
2
NE5534  
4
V
V
= 15 V  
= −15 V  
= 50 kHz  
CC  
EE  
C
14  
0.1 µF  
f
c
V
EE  
Figure 37. Measurement Circuit for DSD  
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I
L− (Pin 26)  
L+ (Pin 25)  
I
I
+
OUT  
OUT  
OUT+  
Figure 36  
Circuit  
I
OUT  
OUT  
3
2
1
I
R− (Pin 18)  
R+ (Pin 17)  
I
I
+
OUT  
OUT  
OUT−  
Figure 36  
Circuit  
Balanced Out  
I
OUT  
OUT  
Figure 38. Measurement Circuit for Monaural Mode  
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APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE  
DFMS = 0  
External Filter Device  
PCM1796  
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
1
2
3
WDCK (Word Clock)  
4
5
6
7
DATA  
BCK  
SCK  
SCK  
DFMS = 1  
External Filter Device  
PCM1796  
DATA_L  
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
1
DATA_R  
2
3
4
5
6
7
WDCK (Word Clock)  
BCK  
SCK  
SCK  
Figure 39. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application  
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Application for Interfacing With an External Digital Filter  
For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it  
can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1796.  
The PCM1796 supports several external digital filters, including:  
D Texas Instruments DF1704 and DF1706  
D Pacific Microsonics PMD200 HDCD filter/decoder IC  
D Programmable digital signal processors  
The external digital filter application mode is accessed by programming the following bits in the corresponding control  
register:  
D DFTH = 1 (register 20)  
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of  
Figure 39. The word clock (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, f .  
S
Pin Assignment When Using the External Digital Filter Interface  
D LRCK (pin 4): WDCK as word clock input  
D BCK (pin 6):  
Bit clock for audio data  
D DATA (pin 5): Monaural audio data input when the DFMS bit is not set to 1  
D ZEROL (pin 1): DATAL as L-channel audio data input when the DFMS bit is set to 1  
D ZEROR (pin 2): DATAR as R-channel audio data input when the DFMS bit is set to 1  
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Audio Format  
The PCM1796 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit,  
and 24-bit audio data, as shown in Figure 40. The audio format is selected by the FMT[2:0] bits of control register18.  
1/4 f or 1/8 f  
S
S
WDCK  
BCK  
Audio Data Word = 16-Bit  
DATA,  
DATAL, DATAR  
15 16  
1
2
3
4
8
5
9
6
7
8
9
10 11 12 13 14 15 16  
LSB  
MSB  
Audio Data Word = 20-Bit  
DATA,  
19 20  
1
5
2
6
3
4
8
5
9
6
7
10 11 12 13 14 15 16 17 18 19 20  
LSB  
DATAL, DATAR  
MSB  
Audio Data Word = 24-Bit  
DATA,  
23 24  
1
2
3
4
7
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24  
LSB  
DATAL, DATAR  
MSB  
Figure 40. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application  
System Clock (SCK) and Interface Timing  
The PCM1796 in an application using an external digital filter requires the synchronization of WDCK and the system  
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL,  
and DATAR is shown in Figure 41.  
1.4 V  
1.4 V  
1.4 V  
WDCK  
BCK  
t
t
t
(LB)  
(BCH)  
(BCL)  
t
t
(BCY)  
(BL)  
DATA  
DATAL  
DATAR  
t
t
(DS)  
(DH)  
PARAMETER  
MIN  
20  
7
MAX UNITS  
t
t
t
t
t
t
t
BCK pulse cycle time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(BCY)  
(BCL)  
(BCH)  
(BL)  
BCK pulse duration, LOW  
BCK pulse duration, HIGH  
7
BCK rising edge to WDCK falling edge  
WDCK falling edge to BCK rising edge  
DATA, DATAL, DATAR setup time  
DATA, DATAL, DATAR hold time  
5
5
(LB)  
5
(DS)  
5
(DH)  
Figure 41. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application  
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FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL FILTER MODE  
The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20. B4).  
The external digital filter mode allows access to the majority of the PCM1796 mode control functions.  
The following table shows the register mapping available when the external digital filter mode is selected, along with  
descriptions of functions which are modified when using this mode selection.  
B15 B14 B13 B12 B11 B10  
B9  
0
B8  
0
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
Register 16 R/W  
Register 17 R/W  
Register 18 R/W  
Register 19 R/W  
Register 20 R/W  
Register 21 R/W  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
FMT2 FMT1 FMT0  
1
1
REV  
SRST  
0
OPE  
DFMS  
INZD  
OS0  
PCMZ  
0
0
1
MONO CHSL OS1  
0
1
Register 22  
R
1
0
ZFGR ZFGL  
NOTE: −: Function is disabled. No operation even if data bit is set  
FMT[2:0]: Audio Data Format Selection  
Default value: 000  
FMT[2:0]  
000  
Audio Data Format Select  
16-bit right-justified format (default)  
20-bit right-justified format  
24-bit right-justified format  
N/A  
001  
010  
Other  
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection  
Default value: 00  
OS[1:0]  
00  
Operation Speed Select  
8 times WDCK (default)  
4 times WDCK  
01  
10  
16 times WDCK  
11  
Reserved  
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and  
the delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects  
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×.  
The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected  
is 16× WDCK, the system clock frequency must be over 256 f .  
S
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APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE  
DSD Decoder  
PCM1796  
ZEROL  
ZEROR  
MSEL  
LRCK  
DATA  
BCK  
1
2
3
DATA_R  
DATA_L  
4
5
6
7
Bit Clock  
SCK  
Figure 42. Connection Diagram in DSD Mode  
Feature  
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications.  
The DSD mode is accessed by programming the following bit in the corresponding control register.  
DSD = 1 (register 20)  
The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure.  
Four FIR responses are available, and are selected by the DMF[1:0] bits of control register 18.  
The DSD bit must be set before inputting DSD data; otherwise, the PCM1796 erroneously detects the TDMCA mode,  
and commands are not accepted through the serial control interface.  
Pin Assignment When Using DSD Format Interface  
Several pins are redefined for DSD mode operation. These include:  
D DATA (pin 5): DSDL as L-channel DSD data input  
D LRCK (pin 4): DSDR as R-channel DSD data input  
D SCK (pin 7): DBCK as bit clock for DSD data  
D BCK (pin 6): Set LOW (N/A)  
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.  
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Requirements for System Clock  
For operation in the DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1796. The frequency of the bit  
clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.  
The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time  
specifications shown in Figure 44.  
t = 1/(64 ×44.1 kHz)  
DBCK  
DSDL  
DSDR  
D0  
D1  
D2  
D3  
D4  
Figure 43. Normal Data Output Form From DSD Decoder  
t
t
(BCL)  
(BCH)  
1.4 V  
1.4 V  
DBCK  
t
(BCY)  
DSDL  
DSDR  
t
t
(DH)  
(DS)  
PARAMETER  
MIN MAX UNITS  
(1)  
t
DBCK pulse cycle time  
DBCK high-level time  
DBCK low-level time  
85  
ns  
ns  
ns  
ns  
ns  
(BCY)  
t
30  
30  
10  
10  
(BCH)  
t
(BCL)  
(DS)  
(DH)  
t
t
DSDL, DSDR setup time  
DSDL, DSDR hold time  
(1)  
2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is  
specified as a sampling rate of DSD.)  
Figure 44. Timing for DSD Audio Interface  
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ANALOG FIR FILTER PERFORMANCE IN DSD MODE  
GAIN  
vs  
GAIN  
vs  
FREQUENCY  
FREQUENCY  
0
−1  
−2  
−3  
−4  
−5  
−6  
0
−10  
−20  
−30  
−40  
−50  
−60  
f
= 185 kHz  
c
(1)  
Gain = −6.6 dB  
0
50  
100  
150  
200  
0
500  
1000  
1500  
f − Frequency − kHz  
f − Frequency − kHz  
Figure 45. DSD Filter-1, Low BW  
Figure 46. DSD Filter-1, High BW  
GAIN  
vs  
GAIN  
vs  
FREQUENCY  
FREQUENCY  
0
−1  
−2  
−3  
−4  
−5  
−6  
0
−10  
−20  
−30  
−40  
−50  
−60  
f
= 90 kHz  
c
(1)  
Gain = 0.3 dB  
0
50  
100  
150  
200  
0
500  
1000  
1500  
f − Frequency − kHz  
f − Frequency − kHz  
Figure 47. DSD Filter-2, Low BW  
Figure 48. DSD Filter-2, High BW  
(1)  
This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.  
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f ), and 50% modulation DSD data input, unless otherwise noted.  
S
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ANALOG FIR FILTER PERFORMANCE IN DSD MODE (CONTINUED)  
GAIN  
vs  
GAIN  
vs  
FREQUENCY  
FREQUENCY  
0
−1  
−2  
−3  
−4  
−5  
−6  
0
−10  
−20  
−30  
−40  
−50  
−60  
f
= 85 kHz  
c
(1)  
Gain = −1.5 dB  
0
50  
100  
150  
200  
0
500  
1000  
1500  
f − Frequency − kHz  
f − Frequency − kHz  
Figure 49. DSD Filter-3, Low BW  
Figure 50. DSD Filter-3, High BW  
GAIN  
vs  
GAIN  
vs  
FREQUENCY  
FREQUENCY  
0
−1  
−2  
−3  
−4  
−5  
−6  
0
−10  
−20  
−30  
−40  
−50  
−60  
f
= 94 kHz  
c
(1)  
Gain = −3.3 dB  
0
50  
100  
150  
200  
0
500  
1000  
1500  
f − Frequency − kHz  
f − Frequency − kHz  
Figure 51. DSD Filter-4, Low BW  
Figure 52. DSD Filter-4, High BW  
(1)  
This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.  
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f ), and 50% modulation DSD data input, unless otherwise noted.  
S
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SLES100 − DECEMBER 2003  
DSD MODE CONFIGURATION AND FUNCTION CONTROLS  
Configuration for the DSD Interface Mode  
The DSD interface mode is selected by setting DSD = 1 (register 20, B5).  
B15 B14 B13 B12 B11 B10  
B9  
0
B8  
0
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
Register 16 R/W  
Register 17 R/W  
Register 18 R/W  
Register 19 R/W  
Register 20 R/W  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
DMF1 DMF0  
1
1
REV  
SRST  
OPE  
0
0
1
MONO CHSL OS1  
OS0  
Register 21  
Register 22  
R
R
0
1
DZ1  
DZ0  
1
0
ZFGR ZFGL  
NOTE: −: Function is disabled. No operation even if data bit is set  
DMF[1:0]: Analog-FIR Performance Selection  
Default value: 00  
DMF[1:0]  
Analog-FIR Performance Select  
00  
01  
10  
11  
FIR-1 (default)  
FIR-2  
FIR-3  
FIR-4  
Plots for the four analog FIR filter responses are shown in the ANALOG FIR FILTER PERFORMANCE IN DSD  
MODE section of this data sheet.  
OS[1:0]: Analog-FIR Operation-Speed Selection  
Default value: 00  
OS[1:0]  
00  
Operation-Speed Select  
f
f
(default)  
/2  
DBCK  
DBCK  
01  
10  
Reserved  
f /4  
DBCK  
11  
The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before  
setting the DSD bit to1.