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产品型号PCM1798DBRG4的Datasheet PDF文件预览

ꢝꢜ  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
D
D
D
5-V Tolerant Digital Inputs  
FEATURES  
Small 28-Lead SSOP Package  
D
24-Bit Resolution  
Pin Assignment Compatible With PCM1794  
D
Analog Performance:  
− Dynamic Range: 123 dB  
− THD+N: 0.0005%  
APPLICATIONS  
D
D
Differential Current Output: 4 mA p-p  
D
D
D
D
D
D
D
A/V Receivers  
8× Oversampling Digital Filter:  
− Stop-Band Attenuation: –98 dB  
− Pass-Band Ripple: 0.0002 dB  
DVD Players  
Musical Instruments  
HDTV Receivers  
D
D
Sampling Frequency: 10 kHz to 200 kHz  
System Clock: 128, 192, 256, 384, 512, or  
Car Audio Systems  
Digital Multitrack Recorders  
Other Applications Requiring 24-Bit Audio  
768 f With Autodetect  
S
D
Accepts 16- and 24-Bit Audio Data  
2
D
PCM Data Formats: Standard, I S, and  
Left-Justified  
DESCRIPTION  
D
Interface Available for Optional External  
Digital Filter or DSP  
The PCM1798 is a monolithic CMOS integrated circuit that  
includes stereo digital-to-analog converters and support  
circuitry in a small 28-lead SSOP package. The data  
converters use TI’s advanced segment DAC architecture  
to achieve excellent dynamic performance and improved  
tolerance to clock jitter. The PCM1798 provides balanced  
current outputs, allowing the user to optimize analog  
performance externally. Sampling rates up to 200 kHz are  
supported.  
D
D
D
D
D
Digital De-Emphasis  
Digital Filter Rolloff: Sharp or Slow  
Soft Mute  
Zero Flag  
Dual-Supply Operation: 5-V Analog, 3.3-V  
Digital  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate  
precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to  
damage because very small parametric changes could cause the device not to meet its published specifications.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢛ ꢚ ꢖꢙ ꢁ ꢌꢋ ꢚꢔ ꢖ ꢒꢌꢒ ꢪꢠ ꢥꢞ ꢝ ꢦꢩ ꢣꢪꢞꢠ ꢪꢤ ꢢꢜ ꢝ ꢝ ꢧꢠꢣ ꢩꢤ ꢞꢥ ꢫꢜꢬ ꢭꢪꢢ ꢩꢣꢪ ꢞꢠ ꢡꢩ ꢣꢧꢮ ꢀꢝ ꢞꢡꢜ ꢢꢣꢤ  
ꢢ ꢞꢠ ꢥꢞꢝ ꢦ ꢣꢞ ꢤ ꢫꢧ ꢢ ꢪ ꢥꢪ ꢢ ꢩ ꢣꢪ ꢞꢠꢤ ꢫ ꢧꢝ ꢣꢯꢧ ꢣꢧ ꢝ ꢦꢤ ꢞꢥ ꢌꢧꢨ ꢩꢤ ꢋꢠꢤ ꢣꢝ ꢜꢦ ꢧꢠꢣ ꢤ ꢤꢣ ꢩꢠꢡ ꢩꢝ ꢡ ꢟ ꢩꢝ ꢝ ꢩ ꢠꢣꢰꢮ  
ꢀꢝ ꢞ ꢡꢜꢢ ꢣ ꢪꢞ ꢠ ꢫꢝ ꢞ ꢢ ꢧ ꢤ ꢤ ꢪꢠ ꢱ ꢡꢞ ꢧ ꢤ ꢠꢞꢣ ꢠꢧ ꢢꢧ ꢤꢤ ꢩꢝ ꢪꢭ ꢰ ꢪꢠꢢ ꢭꢜꢡ ꢧ ꢣꢧ ꢤꢣꢪ ꢠꢱ ꢞꢥ ꢩꢭ ꢭ ꢫꢩ ꢝ ꢩꢦ ꢧꢣꢧ ꢝ ꢤꢮ  
Copyright 2006, Texas Instruments Incorporated  
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ  
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
ORDERING INFORMATION  
OPERATION  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA  
PRODUCT  
PACKAGE  
PACKAGE CODE  
PCM1798DB  
Tube  
PCM1798DB  
28-lead SSOP  
28DB  
–25°C to 85°C  
PCM1798  
PCM1798DBR  
Tape and reel  
ABSOLUTE MAXIMUM RATINGS  
(1)  
over operating free-air temperature range unless otherwise noted  
PCM1798  
V
V
1, V 2L, V 2R  
CC CC  
–0.3 V to 6.5 V  
–0.3 V to 4 V  
0.1 V  
CC  
DD  
Supply voltage  
Supply voltage differences: V 1, V 2L, V 2R  
CC CC CC  
Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND  
0.1 V  
LRCK, DATA, BCK, SCK, FMT1, FMT0, MONO, CHSL, DEM, MUTE, RST,  
ZERO  
–0.3 V to 6.5 V  
Digital input voltage  
Analog input voltage  
–0.3 V to (V  
+ 0.3 V) < 4 V  
DD  
–0.3 V to (V  
+ 0.3 V) < 6.5 V  
CC  
Input current (any pins except supplies)  
Ambient temperature under bias  
Storage temperature  
10 mA  
–40°C to 125°C  
–55°C to 150°C  
150°C  
Junction temperature  
Lead temperature (soldering)  
Package temperature (IR reflow, peak)  
260°C, 5 s  
260°C  
(1)  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V  
= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless  
A
CC  
CC  
CC  
DD  
S
S
otherwise noted  
PCM1798DB  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
TYP  
MAX  
RESOLUTION  
DATA FORMAT  
24  
Bits  
2
Audio data interface format  
Audio data bit length  
Audio data format  
Standard, I S, left-justified  
16-, 24-bit selectable  
MSB first, 2s complement  
f
S
Sampling frequency  
System clock frequency  
10  
200  
kHz  
128, 192, 256, 384, 512, 768 f  
S
DIGITAL INPUT/OUTPUT  
Logic family  
TTL compatible  
V
V
2
IH  
IL  
Input logic level  
Input logic current  
Output logic level  
VDC  
µA  
0.8  
10  
I
IH  
I
IL  
V
V
= V  
DD  
= 0 V  
IN  
IN  
–10  
2.4  
0.4  
V
I
= –2 mA  
= 2 mA  
OH  
OL  
OH  
OL  
VDC  
V
I
2
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
ELECTRICAL CHARACTERISTICS (Continued)  
all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V  
= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless  
A
CC  
CC  
CC  
DD  
S
S
otherwise noted  
PCM1798DB  
TYP  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
MAX  
(1)(2)  
DYNAMIC PERFORMANCE  
f
f
f
= 44.1 kHz  
0.0005% 0.001%  
S
S
S
= 96 kHz  
0.001%  
0.0015%  
123  
THD+N at V  
OUT  
= 0 dB  
= 192 kHz  
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
120  
120  
116  
123  
Dynamic range  
dB  
dB  
EIAJ, A-weighted, f = 192 kHz  
123  
S
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
123  
123  
Signal-to-noise ratio  
EIAJ, A-weighted, f = 192 kHz  
123  
S
f
S
f
S
f
S
= 44.1 kHz  
= 96 kHz  
119  
118  
Channel separation  
Level linearity error  
dB  
dB  
= 192 kHz  
117  
V
= –120 dB  
1
OUT  
(1)(2)(3)  
DYNAMIC PERFORMANCE (MONO MODE)  
f
f
f
= 44.1 kHz  
= 96 kHz  
0.0005%  
0.001%  
0.0015%  
126  
S
S
S
THD+N at V  
OUT  
= 0 dB  
= 192 kHz  
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
126  
Dynamic range  
dB  
dB  
EIAJ, A-weighted, f = 192 kHz  
126  
S
EIAJ, A-weighted, f = 44.1 kHz  
S
EIAJ, A-weighted, f = 96 kHz  
S
126  
126  
Signal-to-noise ratio  
EIAJ, A-weighted, f = 192 kHz  
126  
S
(1)  
Filter condition:  
THD+N: 20-Hz HPF, 20-kHz AES17 LPF  
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted  
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF  
Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precisionin the  
averagingmode.  
(2)  
(3)  
Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 24.  
Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 25.  
Audio Precision and System Two are trademarks of Audio Precision, Inc.  
Other trademarks are the property of their respective owners.  
3
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
ELECTRICAL CHARACTERISTICS (Continued)  
all specifications at T = 25°C, V 1 = V 2L = V 2R = 5 V, V  
= 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless  
A
CC  
CC  
CC  
DD  
S
S
otherwise noted  
PCM1798DB  
TYP  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
MAX  
ANALOG OUTPUT  
Gain error  
–7  
–3  
–2  
2
0.5  
0.5  
4
7
3
2
% of FSR  
% of FSR  
% of FSR  
mA p-p  
mA  
Gain mismatch, channel-to-channel  
Bipolar zero error  
At BPZ  
Output current  
Full scale (0 dB)  
At BPZ  
Center current  
–3.5  
DIGITAL FILTER PERFORMANCE  
De-emphasis error  
0.1  
dB  
FILTER CHARACTERISTICS–1: SHARP ROLLOFF  
0.0002 dB  
–3 dB  
0.454 f  
S
Pass band  
0.49 f  
S
Stop band  
0.546 f  
–98  
S
Pass-band ripple  
0.0002  
dB  
dB  
s
Stop-band attenuation  
Stop band = 0.546 f  
S
Delay time  
38/f  
S
FILTER CHARACTERISTICS–2: SLOW ROLLOFF  
0.001 dB  
–3 dB  
0.21 f  
S
Pass band  
0.448 f  
S
Stop band  
Pass-band ripple  
0.79 f  
–80  
S
0.001  
dB  
dB  
s
Stop-band attenuation  
Delay time  
Stop band = 0.732 f  
S
38/f  
S
POWER SUPPLY REQUIREMENTS  
V
V
V
3
3.3  
5
3.6  
VDC  
VDC  
DD  
CC  
CC  
1
Voltage range  
Supply current  
2L  
4.75  
5.25  
9
V
CC  
2R  
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
= 44.1 kHz  
= 96 kHz  
7
13  
I
mA  
mA  
mW  
DD  
CC  
= 192 kHz  
= 44.1 kHz  
= 96 kHz  
25  
(1)  
18  
23  
19  
I
= 192 kHz  
= 44.1 kHz  
= 96 kHz  
20  
115  
140  
180  
150  
(1)  
Power dissipation  
TEMPERATURE RANGE  
= 192 kHz  
Operation temperature  
Thermal resistance  
–25  
85  
°C  
θ
JA  
28-pin SSOP  
100  
°C/W  
(1)  
Input is BPZ data.  
4
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
PIN ASSIGNMENTS  
PCM1798  
(TOP VIEW)  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
MONO  
CHSL  
DEM  
LRCK  
DATA  
BCK  
V
2L  
CC  
2
AGND3L  
3
I
I
L–  
L+  
OUT  
4
OUT  
5
AGND2  
6
V
V
V
1
CC  
7
SCK  
DGND  
L
R
COM  
COM  
REF  
8
9
V
I
DD  
MUTE  
FMT0  
FMT1  
ZERO  
RST  
10  
11  
12  
13  
14  
AGND1  
I
I
R–  
R+  
OUT  
OUT  
AGND3R  
2R  
V
CC  
5
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ  
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
Terminal Functions  
TERMINAL  
I/O  
DESCRIPTIONS  
NAME  
AGND1  
AGND2  
AGND3L  
AGND3R  
BCK  
PIN  
19  
24  
27  
16  
6
I
Analog ground (internal bias)  
Analog ground (internal bias)  
Analog ground (L-channel DACFF)  
Analog ground (R-channel DACFF)  
(1)  
Bit clock input  
L-, R-channel select  
Serial audio data input  
(1)  
(1)  
(1)  
CHSL  
2
I
DATA  
5
I
DEM  
3
I
De-emphasis enable  
Digital ground  
DGND  
FMT0  
8
I
(1)  
(1)  
11  
12  
25  
26  
17  
18  
20  
4
Audio data format select  
Audio data format select  
FMT1  
I
I
I
I
I
I
L+  
L–  
R+  
R–  
O
O
O
O
I
L-channel analog current output +  
L-channel analog current output –  
R-channel analog current output +  
R-channel analog current output –  
Output current reference bias pin  
OUT  
OUT  
OUT  
OUT  
REF  
(1)  
Left and right clock (f ) input  
S
LRCK  
MONO  
MUTE  
RST  
(1)  
1
I
Monaural mode enable  
(1)  
10  
14  
7
I
Mute control  
(1)  
I
Reset  
System clock input  
Analog power supply, 5 V  
(1)  
SCK  
I
V
V
V
V
V
V
1
23  
28  
15  
22  
21  
9
O
CC  
CC  
CC  
2L  
2R  
Analog power supply (L-channel DACFF), 5 V  
Analog power supply (R-cahnnel DACFF), 5 V  
L-channel internal bias decoupling pin  
R-channel internal bias decoupling pin  
Digital power supply, 3.3 V  
L
COM  
COM  
DD  
R
ZERO  
13  
Zero flag  
(1)  
Schmitt-trigger input, 5-V tolerant  
6
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ  
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
FUNCTIONAL BLOCK DIAGRAM  
I
I
L–  
L+  
OUT  
LRCK  
Audio  
BCK  
Current  
Segment  
DAC  
V
OUT  
L
Data Input  
DATA  
I/F  
OUT  
I/V and Filter  
 8  
Oversampling  
Digital  
Filter  
and  
Function  
Control  
V
I
L
COM  
MUTE  
FMT1  
FMT0  
MONO  
CHSL  
Advanced  
Segment  
DAC  
Bias  
and  
Vref  
REF  
V
COM  
R
Modulator  
Function  
Control  
I/F  
I
R–  
OUT  
OUT  
Current  
Segment  
DAC  
V R  
OUT  
DEM  
RST  
I
R+  
I/V and Filter  
System  
Clock  
Manager  
ZERO  
Zero  
Detect  
Power Supply  
7
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ  
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
TYPICAL PERFORMANCE CURVES  
DIGITAL FILTER  
Digital Filter Response  
AMPLITUDE  
vs  
FREQUENCY  
AMPLITUDE  
vs  
FREQUENCY  
0.0005  
0
−20  
0.0004  
0.0003  
−40  
0.0002  
−60  
0.0001  
0
−80  
−0.0001  
−100  
−120  
−140  
−160  
−0.0002  
−0.0003  
−0.0004  
−0.0005  
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
0
1
2
3
4
Frequency [× f ]  
S
Frequency[× f ]  
S
Figure 1. Frequency Response, Sharp Rolloff  
Figure 2. Pass-Band Ripple, Sharp Rolloff  
AMPLITUDE  
vs  
AMPLITUDE  
vs  
FREQUENCY  
FREQUENCY  
0
−20  
0
−2  
−4  
−40  
−6  
−60  
−8  
−80  
−10  
−12  
−14  
−16  
−18  
−20  
−100  
−120  
−140  
−160  
0
1
2
3
4
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
Frequency[× f ]  
Frequency[× f ]  
S
S
Figure 3. Frequency Response, Slow Rolloff  
Figure 4. Transition Characteristics, Slow Rolloff  
8
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ  
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
De-Emphasis Filter  
DE-EMPHASIS LEVEL  
DE-EMPHASIS ERROR  
vs  
vs  
FREQUENCY  
FREQUENCY  
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
0.5  
0.4  
0.3  
0.2  
0.1  
f
= 44.1 kHz  
f = 44.1 kHz  
S
S
0.0  
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
0
2
4
6
8
10 12 14 16 18 20  
0
2
4
6
8
10 12 14 16 18 20  
f – Frequency – kHz  
f – Frequency – kHz  
Figure 5  
Figure 6  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
ANALOG DYNAMIC PERFORMANCE  
Supply Voltage Characteristics  
TOTAL HARMONIC DISTORTION + NOISE  
DYNAMIC RANGE  
vs  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
126  
124  
122  
120  
118  
116  
0.01  
f
= 96 kHz  
S
f
= 48 kHz  
S
f
= 192 kHz  
S
0.001  
f
S
= 192 kHz  
f
S
= 48 kHz  
f
S
= 96 kHz  
5.25  
0.0001  
4.50  
4.75  
5.00  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
V
CC  
– Supply Voltage – V  
V
CC  
– Supply Voltage – V  
Figure 7  
Figure 8  
SIGNAL-to-NOISE RATIO  
vs  
CHANNEL SEPARATION  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
126  
124  
122  
120  
118  
116  
122  
120  
118  
116  
114  
112  
f
S
= 96 kHz  
f
= 96 kHz  
S
f
S
= 48 kHz  
f
S
= 192 kHz  
f
S
= 48 kHz  
f
= 192 kHz  
S
4.50  
4.75  
5.00  
5.25  
5.50  
4.50  
4.75  
5.00  
5.25  
5.50  
V
CC  
– Supply Voltage – V  
V
CC  
– Supply Voltage – V  
Figure 10  
Figure 9  
NOTE: PCM mode, T = 25°C, V  
= 3.3 V, measurement circuit is Figure 24.  
A
DD  
10  
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Temperature Characteristics  
TOTAL HARMONIC DISTORTION + NOISE  
DYNAMIC RANGE  
vs  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
126  
124  
122  
120  
118  
116  
0.01  
f
= 96 kHz  
S
f
S
= 48 kHz  
f
= 192 kHz  
S
f
= 96 kHz  
S
0.001  
f
= 192 kHz  
S
f
S
= 48 kHz  
0.0001  
−50  
−25  
0
25  
50  
75  
100  
−50  
−25  
0
25  
50  
75  
100  
T
A
– Free-Air Temperature – °C  
T
A
– Free-Air Temperature – °C  
Figure 11  
Figure 12  
SIGNAL-to-NOISE RATIO  
vs  
CHANNEL SEPARATION  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
126  
124  
122  
120  
118  
116  
122  
120  
118  
116  
114  
112  
f
= 96 kHz  
S
f
= 96 kHz  
= 48 kHz  
S
f
= 192 kHz  
S
f
S
f
= 48 kHz  
S
f
= 192 kHz  
S
−50  
−25  
0
25  
50  
75  
100  
−50  
−25  
0
25  
50  
75  
100  
T
A
– Free-Air Temperature – °C  
T
A
– Free-Air Temperature – °C  
Figure 13  
Figure 14  
NOTE: PCM mode, V  
DD  
= 3.3 V, V = 5 V, measurement circuit is Figure 24.  
CC  
11  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
AMPLITUDE  
vs  
AMPLITUDE  
vs  
FREQUENCY  
FREQUENCY  
0
0
−20  
−20  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−160  
−100  
−120  
−140  
−160  
0
2
4
6
8
10 12 14 16 18 20  
0
10 20 30 40 50 60 70 80 90 100  
f – Frequency – kHz  
f – Frequency – kHz  
NOTE: f = 48 kHz, 32768 point 8 average, T = 25°C, V  
= 3.3 V,  
NOTE: f = 96 kHz, 32768 point 8 average, T = 25°C, V  
= 3.3 V,  
S
A
DD  
S
A
DD  
V
CC  
= 5 V, measurement circuit is Figure 24.  
V
CC  
= 5 V, measurement circuit is Figure 24.  
Figure 15. –60-db Output Spectrum, BW = 20 kHz  
Figure 16. –60-db Output Spectrum, BW = 100 kHz  
TOTAL HARMONIC DISTORTION + NOISE  
vs  
INPUT LEVEL  
10  
1
0.1  
0.01  
0.001  
0.0001  
−90 −80 −70 −60 −50 −40 −30 −20 −10  
0
Input Level – dBFS  
NOTE: f = 48 kHz, T = 25°C, V  
DD  
= 3.3 V, V = 5 V,  
CC  
S
A
measurement circuit is Figure 24.  
Figure 17. THD+N vs Input Level, PCM Mode  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
SYSTEM CLOCK AND RESET FUNCTIONS  
System Clock Input  
The PCM1798 requires a system clock for operating the digital interpolation filters and advanced segment DAC  
modulators. The system clock is applied at the SCK input (pin 7). The PCM1798 has a system clock detection circuit  
that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system  
clock frequencies for common audio sampling rates.  
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use  
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators  
is an excellent choice for providing the PCM1798 system clock.  
Table 1. System Clock Rates for Common Audio Sampling Frequencies  
SYSTEM CLOCK FREQUENCY (f  
) (MHz)  
512 f  
SCK  
SAMPLING FREQUENCY  
128 f  
192 f  
256 f  
384 f  
768 f  
S
S
S
S
S
S
32 kHz  
44.1 kHz  
48 kHz  
4.096  
5.6488  
6.144  
6.144  
8.4672  
9.216  
8.192  
11.2896  
12.288  
24.576  
49.152  
12.288  
16.9344  
18.432  
36.864  
73.728  
16.384  
24.576  
33.8688  
36.864  
73.728  
22.5792  
24.576  
49.152  
96 kHz  
12.288  
24.576  
18.432  
36.864  
(1)  
(1)  
192 kHz  
(1)  
This system clock rate is not supported for the given sampling frequency.  
t
(SCKH)  
H
2 V  
System Clock (SCK)  
0.8 V  
L
t
(SCKL)  
t
(SCY)  
PARAMETERS  
MIN  
13  
(SCY)  
0.4t  
MAX UNITS  
t
System clock pulse cycle time  
ns  
ns  
ns  
(SCY)  
t
System clock pulse duration, HIGH  
System clock pulse duration, LOW  
0.4t  
(SCY)  
(SCKH)  
t
(SCKL)  
Figure 18. System Clock Input Timing  
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Power-On and External Reset Functions  
The PCM1798 includes a power-on reset function. Figure 19 shows the operation of this function. With V  
> 2 V,  
DD  
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time  
> 2 V.  
V
DD  
The PCM1798 also includes an external reset capability using the RST input (pin 14). This allows an external  
controller or master reset circuit to force the PCM1798 to initialize to its default reset state.  
Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The  
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock  
periods. The external reset is especially useful in applications where there is a delay between the PCM1798 power  
up and system clock activation.  
V
DD  
2.4 V (Max)  
2 V (Typ)  
1.6 V (Min)  
Reset  
Reset Removal  
Internal Reset  
System Clock  
1024 System Clocks  
Figure 19. Power-On Reset Timing  
RST (Pin 14)  
1.4 V  
t
(RST)  
Reset  
Reset Removal  
Internal Reset  
System Clock  
1024 System Clocks  
PARAMETERS  
Reset pulse duration, LOW  
MIN  
MAX UNITS  
t
20  
ns  
(RST)  
Figure 20. External Reset Timing  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
AUDIO DATA INTERFACE  
Audio Serial Interface  
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the  
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio  
interface. Serial data is clocked into the PCM1798 on the rising edge of BCK. LRCK is the serial audio left/right word  
clock.  
The PCM1798 requires the synchronization of LRCK and the system clock, but does not need a specific phase  
relation between LRCK and the system clock.  
If the relationship between LRCK and the system clock changes more than 6 BCK, internal operation is initialized  
within 1/f and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the  
S
system clock is completed.  
PCM Audio Data Formats and Timing  
2
The PCM1798 supports industry-standard audio data formats, including standard right-justified, I S, and  
left-justified. The data formats are shown in Figure 22. Data formats are selected using FMT0 (pin 11) and FMT1  
(pin 12) as shown in Table 2. All formats require binary twos-complement, MSB-first audio data. Figure 21 shows  
a detailed timing diagram for the serial audio interface.  
1.4 V  
1.4 V  
1.4 V  
LRCK  
t
t
(BCL)  
t
(BCH)  
(LB)  
BCK  
t
t
(BCY)  
(BL)  
DATA  
t
t
(DS)  
(DH)  
PARAMETERS  
MIN MAX UNITS  
t
t
t
t
t
t
t
BCK pulse cycle time  
BCK pulse duration, LOW  
BCK pulse duration, HIGH  
BCK rising edge to LRCK edge  
LRCK edge to BCK rising edge  
DATA setup time  
70  
30  
30  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(BCY)  
(BCL)  
(BCH)  
(BL)  
(LB)  
(DS)  
DATA hold time  
(DH)  
LRCK clock data  
50% 2 bit clocks  
Figure 21. Timing of Audio Interface  
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(1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW  
1/f  
S
LRCK  
R-Channel  
L-Channel  
BCK  
Audio Data Word = 16-Bit  
14 15 16  
1
2
15 16  
LSB  
1
2
15 16  
DATA  
MSB  
Audio Data Word = 24-Bit  
22 23 24  
1
2
23 24  
LSB  
1
2
23 24  
DATA  
MSB  
(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW  
1/f  
S
LRCK  
BCK  
R-Channel  
L-Channel  
Audio Data Word = 24-Bit  
DATA  
1
2
23 24  
LSB  
1
2
23 24  
1
2
MSB  
2
(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH  
1/f  
S
LRCK  
BCK  
L-Channel  
R-Channel  
Audio Data Word = 24-Bit  
DATA  
1
2
23 24  
LSB  
1
2
23 24  
1
2
MSB  
Figure 22. Audio Data Input Formats  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
FUNCTION DESCRIPTIONS  
Audio data format  
Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1798 also supports monaural mode and DF  
bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1798 can select the DF rolloff characteristics.  
Table 2. Audio Data Format Select  
MONO  
CHSL  
FMT1  
FMT0  
FORMAT  
STEREO/MONO  
Stereo  
DF ROLLOFF  
Sharp  
Sharp  
Sharp  
Sharp  
Slow  
2
I S  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Left-justified format  
Standard, 16-bit  
Standard, 24-bit  
Stereo  
Stereo  
Stereo  
2
I S  
Stereo  
Left-justified format  
Standard, 16-bit  
Stereo  
Slow  
Stereo  
Slow  
Digital filter bypass  
Mono  
2
I S  
Mono, L-channel  
Mono, L-channel  
Mono, L-channel  
Mono, L-channel  
Mono, R-channel  
Mono, R-channel  
Mono, R-channel  
Mono, R-channel  
Sharp  
Sharp  
Sharp  
Sharp  
Sharp  
Sharp  
Sharp  
Sharp  
Left-justified format  
Standard, 16-bit  
Standard, 24-bit  
2
I S  
Left-justified format  
Standard, 16-bit  
Standard, 24-bit  
Soft Mute  
The PCM1798 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned  
to the bipolar zero level in –0.5-dB steps with a transition speed of 1/f per step. This system provides pop-free muting  
S
of the DAC output.  
De-Emphasis  
The PCM1798 has a de-emphasis filter for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled  
using DEM (pin 3).  
Zero Detection  
When the PCM1798 detects that the audio input data in the L-channel and the R-channel is continuously zero for  
1024 LRCKs in the PCM mode, or that the audio input data is continuously zero for 1024 WDCKs in the external filter  
mode, the PCM1798 sets ZERO (pin 13) to HIGH.  
17  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
APPLICATION INFORMATION  
TYPICAL CONNECTION DIAGRAM  
C
f
5 V  
R
R
f
0.1 µF  
MONO  
CHSL  
DEM  
V
2L  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
10 µF  
CC  
+
AGND3L  
Differential  
to  
Single  
Converter  
With  
Low-Pass  
Filter  
I L–  
OUT  
3
C
f
V
OUT  
L-Channel  
LRCK  
DATA  
BCK  
I
L+  
4
OUT  
f
PCM  
Audio  
Data  
5 V  
AGND2  
5
+
V
1
CC  
6
Source  
10 µF  
SCK  
V L  
COM  
7
+
C
f
PCM1798  
DGND  
V
COM  
R
8
R
R
0.1 µF  
47 µF  
10 kΩ  
f
V
DD  
I
REF  
9
+
MUTE  
FMT0  
FMT1  
ZERO  
RST  
AGND1  
10  
11  
12  
13  
14  
Differential  
to  
Single  
Converter  
With  
Low-Pass  
Filter  
I
R–  
R+  
C
OUT  
f
V
OUT  
R-Channel  
Controller  
I
OUT  
f
0.1 µF  
5 V  
AGND3R  
+
V
CC  
2R  
10 µF  
3.3 V  
+
10 µF  
Figure 23. Typical Application Circuit  
APPLICATION CIRCUIT  
The design of the application circuit is very important in order to actually realize the high S/N ratio of which the  
PCM1798 is capable. This is because noise and distortion that are generated in an application circuit are not  
negligible.  
In the third-order LPF circuit of Figure 24, the output level is 2.1 V RMS, and 123 dB S/N is achieved.  
I/V Section  
The current of the PCM1798 on each of the output pins (I  
L+, I  
L–, I  
R+, I  
R–) is 4 mA p-p at 0 dB (full  
OUT  
OUT  
OUT  
OUT  
scale). The voltage output level of the I/V converter (Vi) is given by following equation:  
Vi = 4 mA p–p × R (R : feedback resistance of I/V converter)  
f
f
An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic  
performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio  
dynamic performance of the I/V section.  
Differential Section  
The PCM1798 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each  
channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter  
function.  
The operational amplifier recommended for the differential circuit is the low-noise type.  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
C
1
2700 pF  
R
1
820 Ω  
V
CC  
V
CC  
C
3
C
11  
0.1 µF  
8200 pF  
R
200 Ω  
5
C
15  
0.1 µF  
C
22 pF  
17  
C
22 pF  
19  
7
5
R
220 Ω  
R
7
7
2
3
8
6
3
+
I –  
OUT  
5
180 Ω  
R
100 Ω  
2
3
8
6
9
+
C
5
U
1
27000 pF  
NE5534  
U
4
3
NE5534  
4
R
4
R
8
180 Ω  
C
12  
0.1 µF  
220 Ω  
R
6
200 Ω  
C
16  
0.1 µF  
C
4
V
EE  
8200 pF  
V
EE  
C
2
2700 pF  
R
2
820 Ω  
V
CC  
C
13  
0.1 µF  
C
22 pF  
18  
7
5
2
3
8
6
+
I +  
OUT  
U
2
NE5534  
4
V
V
= 15 V  
= –15 V  
= 50 kHz  
CC  
EE  
C
14  
0.1 µF  
f
c
V
EE  
Figure 24. Measurement Circuit  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
I
L– (Pin 26)  
L+ (Pin 25)  
I
I
+
OUT  
OUT  
OUT+  
Figure 24  
Circuit  
I
OUT  
OUT  
3
2
1
I
R– (Pin 18)  
R+ (Pin 17)  
I
I
+
OUT  
OUT  
OUT–  
Figure 24  
Circuit  
Balanced Out  
I
OUT  
OUT  
Figure 25. Measurement Circuit for Monaural Mode  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE  
V
DD  
MONO  
CHSL  
DEM  
V
2L  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CC  
External  
Filter  
Device  
AGND3L  
I
I
L–  
L+  
3
OUT  
WDCK  
LRCK  
DATA  
BCK  
4
OUT  
DATA  
BCK  
SCK  
AGND2  
5
V
1
CC  
6
Analog  
Output Stage  
(See Figure 23)  
SCK  
V L  
COM  
7
PCM1798  
DGND  
V
COM  
R
8
V
DD  
I
REF  
9
MUTE  
FMT0  
FMT1  
ZERO  
RST  
AGND1  
10  
11  
12  
13  
14  
I
R–  
R+  
OUT  
I
OUT  
AGND3R  
V
CC  
2R  
Figure 26. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application  
Application for Interfacing With an External Digital Filter  
For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter  
to perform the interpolation function. The following pin settings enable the external digital filter application mode.  
D MONO (pin 1) = LOW  
D CHSL (Pin 2) = HIGH  
D FMT0 (Pin 11) = HIGH  
D FMT1 (pin 12) = HIGH  
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of  
Figure 26. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, f .  
S
Pin Assignment When Using the External Digital Filter Interface  
D LRCK (pin 4): WDCK as word clock input  
D DATA (pin 5): Monaural audio data input  
D BCK (pin 6): Bit clock input  
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SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
Audio Format  
The PCM1798 in the external digital filter interface mode supports the 24-bit right-justified audio format as shown  
in Figure 27.  
1/4 f or 1/8 f  
S
S
WDCK  
BCK  
Audio Data Word = 24-Bit  
23 24  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24  
LSB  
DATA  
MSB  
Figure 27. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application  
System Clock (SCK) and Interface Timing  
The PCM1798 in an application using an external digital filter requires the synchronization of WDCK and the system  
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, and DATA is  
shown in Figure 28.  
WDCK  
1.4 V  
1.4 V  
1.4 V  
t
t
t
(LB)  
(BCH)  
(BCL)  
BCK  
t
t
(BCY)  
(BL)  
DATA  
t
t
(DS)  
(DH)  
PARAMETER  
MIN  
20  
7
MAX UNITS  
t
t
t
t
t
t
t
BCK pulse cycle time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(BCY)  
(BCL)  
(BCH)  
(BL)  
BCK pulse duration, LOW  
BCK pulse duration, HIGH  
BCK rising edge to WDCK falling edge  
WDCK falling edge to BCK rising edge  
DATA setup time  
7
5
5
(LB)  
5
(DS)  
DATA hold time  
5
(DH)  
Figure 28. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application  
22  
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ  
www.ti.com  
SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006  
ANALOG OUTPUT  
Table 3 and Figure 29 show the relationship between the digital input code and analog output.  
Table 3. Analog Output Current and Voltage  
800000 (–FS)  
–1.5  
000000 (BPZ)  
7FFFFF (+FS)  
I
N [mA]  
P [mA]  
–3.5  
–3.5  
–2.87  
–2.87  
0
–5.5  
OUT  
I
–5.5  
–1.5  
OUT  
V
N [V]  
P [V]  
–1.23  
–4.51  
OUT  
V
–4.51  
–1.23  
2.98  
OUT  
V
[V]  
–2.98  
OUT  
NOTE: V  
N is the output of U1, V  
measurementcircuit of Figure 24.  
P is the output of U2, and V  
OUT  
is the output of U3 in the  
OUT  
OUT  
OUTPUT CURRENT  
vs  
INPUT CODE  
0
−1  
−2  
−3  
−4  
−5  
−6  
I
N
OUT  
I
P
OUT  
800000(–FS)  
000000(BPZ)  
7FFFFF(+FS)  
Input Code – Hex  
Figure 29. The Relationship Between Digital Input and Analog Output  
23  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Dec-2006  
PACKAGING INFORMATION  
Orderable Device  
PCM1798DB  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SSOP  
DB  
28  
28  
28  
28  
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
PCM1798DBG4  
PCM1798DBR  
PCM1798DBRG4  
SSOP  
SSOP  
SSOP  
DB  
DB  
DB  
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
13-Jan-2011  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
PCM1798DBR  
SSOP  
DB  
28  
2000  
330.0  
17.4  
8.5  
10.8  
2.4  
12.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
13-Jan-2011  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SSOP DB 28  
SPQ  
Length (mm) Width (mm) Height (mm)  
336.6 336.6 28.6  
PCM1798DBR  
2000  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
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配单直通车
PCM1798DBRG4产品参数
型号:PCM1798DBRG4
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Obsolete
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SSOP
包装说明:SSOP, SSOP28,.3
针数:28
Reach Compliance Code:compliant
风险等级:5.23
转换器类型:D/A CONVERTER
输入位码:2'S COMPLEMENT BINARY
输入格式:SERIAL
JESD-30 代码:R-PDSO-G28
JESD-609代码:e4
长度:10.2 mm
湿度敏感等级:1
位数:24
功能数量:1
端子数量:28
最高工作温度:85 °C
最低工作温度:-25 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SSOP
封装等效代码:SSOP28,.3
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:3.3,5 V
认证状态:Not Qualified
座面最大高度:2 mm
子类别:Other Converters
最大压摆率:23 mA
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:OTHER
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mm
Base Number Matches:1
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