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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • PCM1808QPWRQ1
  • 数量-
  • 厂家-
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  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • PCM1808QPWRQ1图
  • 集好芯城

     该会员已使用本站13年以上
  • PCM1808QPWRQ1 现货库存
  • 数量14393 
  • 厂家TI(德州仪器) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • PCM1808QPWRQ1图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • PCM1808QPWRQ1 现货库存
  • 数量5300 
  • 厂家TI/德州仪器? 
  • 封装TSSOP-14 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
  • PCM1808QPWRQ1图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • PCM1808QPWRQ1 现货库存
  • 数量6538 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号23+ 
  • 原装现货,实货实报
  • QQ:892152356QQ:892152356 复制
  • 0755-82777852 QQ:892152356
  • PCM1808QPWRQ1图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • PCM1808QPWRQ1 现货库存
  • 数量60030 
  • 厂家BB/TI 
  • 封装TSSOP14 
  • 批号2023+ 
  • 专营原装正品量大可定货
  • QQ:2885134554QQ:2885134554 复制
    QQ:2885134398QQ:2885134398 复制
  • 0755-22669259 QQ:2885134554QQ:2885134398
  • PCM1808QPWRQ1图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • PCM1808QPWRQ1 现货库存
  • 数量23200 
  • 厂家TI 
  • 封装N/A 
  • 批号21+ 
  • 全新原装有现货库存--价格有优势
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • PCM1808QPWRQ1图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • PCM1808QPWRQ1 现货库存
  • 数量36000 
  • 厂家TI 
  • 封装TSSOP-14 
  • 批号新年份 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • PCM1808QPWRQ1图
  • 深圳市正纳电子有限公司

     该会员已使用本站2年以上
  • PCM1808QPWRQ1 现货库存
  • 数量10000 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号22+ 
  • 只做原装 欢迎询价???
  • QQ:2881664480QQ:2881664480 复制
  • 0755-82524192 QQ:2881664480
  • PCM1808QPWRQ1图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • PCM1808QPWRQ1 现货库存
  • 数量2000 
  • 厂家TI 
  • 封装TSSOP (PW) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • PCM1808QPWRQ1图
  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • PCM1808QPWRQ1 现货库存
  • 数量18500 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-14 
  • 批号23+ 
  • ★★全网低价,原装原包★★
  • QQ:1483430049QQ:1483430049 复制
  • 0755-83235525 QQ:1483430049
  • PCM1808QPWRQ1图
  • 深圳市勤思达科技有限公司

     该会员已使用本站14年以上
  • PCM1808QPWRQ1 优势库存
  • 数量6000 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号2021+ 
  • ▉十二年专注▉? 100%全新原装正品 正规渠道订货 长期现货供应
  • QQ:2881910282QQ:2881910282 复制
    QQ:2881239443QQ:2881239443 复制
  • 0755-83268779 QQ:2881910282QQ:2881239443
  • PCM1808QPWRQ1图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • PCM1808QPWRQ1 优势库存
  • 数量6000 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号21 
  • 十年以上分销商原装进口件服务型企业0755-83790645
  • QQ:2881664479QQ:2881664479 复制
  • 755-83790645 QQ:2881664479
  • PCM1808QPWRQ1图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • PCM1808QPWRQ1 优势库存
  • 数量2000 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号23 
  • 全新原装正品 特价热卖
  • QQ:1327510916QQ:1327510916 复制
    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • PCM1808QPWRQ1图
  • 深圳市金亿瑞科技有限公司

     该会员已使用本站8年以上
  • PCM1808QPWRQ1 优势库存
  • 数量8000 
  • 厂家TI 
  • 封装TSSOP-14 
  • 批号21+ 
  • 原装进口假一罚万
  • QQ:2881971192QQ:2881971192 复制
    QQ:3630460351QQ:3630460351 复制
  • 13530074872 QQ:2881971192QQ:3630460351
  • PCM1808QPWRQ1图
  • 深圳市西昂特科技有限公司

     该会员已使用本站13年以上
  • PCM1808QPWRQ1 优势库存
  • 数量30000 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号21+ 
  • 原厂原装现货
  • QQ:2881291855QQ:2881291855 复制
    QQ:1158574719QQ:1158574719 复制
  • 0755-82524647 QQ:2881291855QQ:1158574719
  • PCM1808QPWRQ1图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • PCM1808QPWRQ1
  • 数量8000 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号21+ 
  • 原装正品,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • PCM1808QPWRQ1图
  • 集好芯城

     该会员已使用本站13年以上
  • PCM1808QPWRQ1
  • 数量13974 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • PCM1808QPWRQ1图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • PCM1808QPWRQ1
  • 数量2250 
  • 厂家TI 
  • 封装TSSOP-14 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
  • PCM1808QPWRQ1图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • PCM1808QPWRQ1
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • PCM1808QPWRQ1图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • PCM1808QPWRQ1
  • 数量18803 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • PCM1808QPWRQ1图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • PCM1808QPWRQ1
  • 数量16851 
  • 厂家TI/德州仪器 
  • 封装TI-2019 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • PCM1808QPWRQ1图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • PCM1808QPWRQ1
  • 数量28620 
  • 厂家TI 
  • 封装14-TSSOP 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • PCM1808QPWRQ1图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • PCM1808QPWRQ1
  • 数量9048 
  • 厂家TI(德州仪器) 
  • 封装TSSOP14 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • PCM1808QPWRQ1图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • PCM1808QPWRQ1
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装贴/插片 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104891 QQ:857273081QQ:1594462451
  • PCM1808QPWRQ1图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • PCM1808QPWRQ1
  • 数量5600 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • PCM1808QPWRQ1图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • PCM1808QPWRQ1
  • 数量7536 
  • 厂家TEXAS 
  • 封装TSSOP-14 
  • 批号23+ 
  • 音频转换器进口原装代理销售
  • QQ:892152356QQ:892152356 复制
  • 0755-82777852 QQ:892152356
  • PCM1808QPWRQ1图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • PCM1808QPWRQ1
  • 数量8281 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • PCM1808QPWRQ1图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • PCM1808QPWRQ1
  • 数量865000 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • PCM1808QPWRQ1图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • PCM1808QPWRQ1
  • 数量28000 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • PCM1808QPWRQ1图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • PCM1808QPWRQ1
  • 数量9328 
  • 厂家TI-德州仪器 
  • 封装TSSOP-14 
  • 批号▉▉:2年内 
  • ▉▉¥18.9元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • PCM1808QPWRQ1图
  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • PCM1808QPWRQ1
  • 数量14500 
  • 厂家TI/德州仪器 
  • 封装TSSOP-14 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
  • PCM1808QPWRQ1图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • PCM1808QPWRQ1
  • 数量3577 
  • 厂家TI 
  • 封装14-TSSOP(0.173,4.40mm 宽) 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • PCM1808QPWRQ1图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • PCM1808QPWRQ1
  • 数量12300 
  • 厂家BB/TI 
  • 封装TSSOP14 
  • 批号24+ 
  • ★原装真实库存★13点税!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
  • PCM1808QPWRQ1图
  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • PCM1808QPWRQ1
  • 数量5280 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-14 
  • 批号23+ 
  • ▉原装正品▉力挺实单可含税可拆样
  • QQ:3003797048QQ:3003797048 复制
    QQ:3003797050QQ:3003797050 复制
  • 0755-82779553 QQ:3003797048QQ:3003797050
  • PCM1808QPWRQ1图
  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • PCM1808QPWRQ1
  • 数量32000 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-14 
  • 批号2年内 
  • 原厂渠道 长期供应
  • QQ:2355734291QQ:2355734291 复制
  • -0755-88604592 QQ:2355734291
  • PCM1808QPWRQ1图
  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • PCM1808QPWRQ1
  • 数量99000 
  • 厂家BB/TI 
  • 封装TSSOP14 
  • 批号23+ 
  • 一级代理进口原装现货、假一罚十价格合理
  • QQ:1157099927QQ:1157099927 复制
    QQ:2039672975QQ:2039672975 复制
  • 0755-2870-8773手机微信同号13430772257 QQ:1157099927QQ:2039672975
  • PCM1808QPWRQ1图
  • 北京顺科电子科技有限公司

     该会员已使用本站8年以上
  • PCM1808QPWRQ1
  • 数量5500 
  • 厂家TI/德州仪器 
  • 封装SSOP-14 
  • 批号21+ 
  • 进口品牌//国产品牌代理商18911556207
  • QQ:729566152QQ:729566152 复制
    QQ:1138731127QQ:1138731127 复制
  • 18911556207 QQ:729566152QQ:1138731127
  • PCM1808QPWRQ1图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • PCM1808QPWRQ1
  • 数量8800 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
  • QQ:840638855QQ:840638855 复制
  • 0755-84876394 QQ:840638855
  • PCM1808QPWRQ1图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • PCM1808QPWRQ1
  • 数量5300 
  • 厂家TI 
  • 封装TSSOP14 
  • 批号21+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • PCM1808QPWRQ1图
  • 深圳市聚利源实业有限公司

     该会员已使用本站1年以上
  • PCM1808QPWRQ1
  • 数量2590 
  • 厂家TI/德州仪器 
  • 封装TSSOP14 
  • 批号 
  • 只售正品 原装现货
  • QQ:2881504303QQ:2881504303 复制
  • 0755-33037976 QQ:2881504303

产品型号PCM1808QPWRQ1的概述

PCM1808QPWRQ1 概述 PCM1808QPWRQ1 是一款高性能的音频模数转换器(ADC),被广泛应用于音频处理及相关领域。它属于德州仪器(Texas Instruments, TI)产品线,专为高精度音频设备而设计。该芯片能够将模拟音频信号转换为数字信号,使得这些信号可以在数字设备中进行处理、存储和传输。 PCM1808QPWRQ1 的设计考虑了低功耗和高动态范围,使得其在涵盖家庭音响、专业录音设备和多媒体应用方面都具有广泛的适用性。它支持多种采样频率和分辨率,并具备低失真、高信噪比的特性,从而确保了音频质量的优越性。 详细参数 PCM1808QPWRQ1 的主要参数包括: - 采样频率:支持48 kHz、96 kHz、192 kHz等多种速率; - 分辨率:具有24位分辨率,满足高保真音频的需求; - 信噪比:高达105 dB,保证了转换过程中的音质; - 总谐波失真(T...

产品型号PCM1808QPWRQ1的Datasheet PDF文件预览

PCM1808-Q1  
www.ti.com  
SLES265A MARCH 2011REVISED AUGUST 2012  
SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER  
Check for Samples: PCM1808-Q1  
1
FEATURES  
Package: 14-Pin TSSOP  
23  
Qualified for Automotive Applications  
24-Bit Delta-Sigma Stereo A/D Converter  
Single-Ended Voltage Input: 3 Vp-p  
High Performance:  
DESCRIPTION  
The PCM1808-Q1 is high-performance, low-cost,  
single-chip, stereo analog-to-digital converter with  
single-ended analog voltage input. The PCM1808-Q1  
uses  
a
delta-sigma modulator with 64-times  
THD + N: –93 dB (Typical)  
SNR: 99 dB (Typical)  
oversampling and includes a digital decimation filter  
and high-pass filter that removes the dc component  
of the input signal. For various applications, the  
PCM1808-Q1 supports master and slave mode and  
two data formats in serial audio interface.  
Dynamic Range: 99 dB (Typical)  
Oversampling Decimation Filter:  
Oversampling Frequency: ×64  
Pass-Band Ripple: ±0.05 dB  
The PCM1808-Q1 supports the power-down and  
reset function by means of halting the system clock.  
Stop-Band Attenuation: –65 dB  
On-Chip High-Pass Filter: 0.91 Hz (48 kHz)  
The PCM1808-Q1 is suitable for wide variety of cost-  
sensitive consumer applications where good  
performance and operation with a 5-V analog supply  
and 3.3-V digital supply is required. The PCM1808-  
Q1 is fabricated using a highly advanced CMOS  
process and is available in a small, 14-pin TSSOP  
package.  
Flexible PCM Audio Interface  
Master/Slave Mode Selectable  
Data Formats: 24-Bit I2S, 24-Bit Left-  
Justified  
Power Down and Reset by Halting System  
Clock  
Analog Antialias LPF Included  
Sampling Rate: 8 kHz–96 kHz  
System Clock: 256 fS, 384 fS, 512 fS  
Dual Power Supplies:  
5-V for Analog  
3.3-V for Digital  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
System Two, Audio Precision are trademarks of Audio Precision, Inc.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011–2012, Texas Instruments Incorporated  
PCM1808-Q1  
SLES265A MARCH 2011REVISED AUGUST 2012  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
(1)  
PCM1808-Q1  
Analog supply voltage, VCC  
–0.3 V to 6.5 V  
–0.3 V to 4 V  
Digital supply voltage, VDD  
Ground voltage differences, AGND, DGND  
Digital input voltage, LRCK, BCK, DOUT  
Digital input voltage, SCKI, MD0, MD1, FMT  
Analog input voltage, VINL, VINR, VREF  
Input current (any pins except supplies)  
Ambient temperature under bias, TA  
Storage temperature, Tstg  
±0.1 V  
–0.3 V to (VDD + 0.3 V) < 4 V  
–0.3 V to 6.5 V  
–0.3 V to (VCC + 0.3 V) < 6.5 V  
±10 mA  
–40°C to 125°C  
–55°C to 150°C  
150°C  
Junction temperature, TJ  
Lead temperature (soldering)  
260°C, 5 s  
Package temperature (reflow, peak)  
260°C  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating  
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
over operating free-air temperature range (unless otherwise noted)  
MIN  
4.5  
NOM  
MAX  
5.5  
UNIT  
V
Analog supply voltage, VCC  
5
Digital supply voltage, VDD  
2.7  
3.3  
3
3.6  
V
Analog input voltage, full scale (–0 dB)  
Digital input logic family  
VCC = 5 V  
2.93  
3.23  
Vp-p  
TTL compatible  
Digital input clock frequency, system clock  
Digital input clock frequency, sampling clock  
Digital output load capacitance  
Operating free-air temperature, TA  
2.048  
8
49.152  
96  
MHz  
kHz  
pF  
20  
–40  
125  
°C  
2
Copyright © 2011–2012, Texas Instruments Incorporated  
 
PCM1808-Q1  
www.ti.com  
SLES265A MARCH 2011REVISED AUGUST 2012  
ELECTRICAL CHARACTERISTICS  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless  
otherwise noted  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Resolution  
24  
Bits  
DATA FORMAT  
Audio data interface format  
Audio data bit length  
Audio data format  
I2S, left-justified  
24  
Bits  
kHz  
MHz  
MSB-first, 2s complement  
fS  
Sampling frequency  
8
2.048  
3.072  
4.096  
48  
12.288  
18.432  
24.576  
96  
24.576  
36.864  
49.152  
256 fS  
384 fS  
512 fS  
System clock frequency,  
–40°C TA 125°C(1)  
INPUT LOGIC  
(2)  
VIH  
2
0
2
0
VDD  
0.8  
(2)  
VIL  
VIH  
VIL  
IIH  
Input logic level,  
VDC  
–40°C TA 125°C(3)  
(4) (5)  
(4) (5)  
5.5  
0.8  
(4)  
VIN = VDD  
VIN = 0 V  
±10  
±10  
100  
150  
±10  
(4)  
IIL  
IIH  
IIL  
Input logic current  
at 25°C  
65  
65  
μA  
(2) (5)  
(2) (5)  
VIN = VDD  
VIN = 0 V  
–40°C TA 125°C  
OUTPUT LOGIC  
at 25°C  
2.8  
2.7  
(6)  
VOH  
IOUT = –4 mA  
Output logic level(3)  
–40°C TA 125°C  
VDC  
(6)  
VOL  
IOUT = 4 mA, –40°C TA 125°C  
0.5  
DC ACCURACY, –40°C TA 125°C  
Gain mismatch, channel-to-  
channel  
% of  
FSR  
±1  
±3  
±3  
±6  
% of  
FSR  
Gain error  
(7)  
DYNAMIC PERFORMANCE  
at 25°C  
–93  
–93  
–87  
–37  
–39  
99  
–87  
–85  
VIN = –0.5 dB, fS = 48 kHz  
–40°C TA 125°C  
Total harmonic distortion +  
(8)  
THD + N  
noise  
VIN = –0.5 dB, fS = 96 kHz  
VIN = –60 dB, fS = 48 kHz  
VIN = –60 dB, fS = 96 kHz  
dB  
(8)  
at 25°C  
95  
93  
fS = 48 kHz, A-weighted  
Dynamic range  
–40°C TA 125°C  
99  
dB  
dB  
(8)  
fS = 96 kHz, A-weighted  
fS = 48 kHz, A-weighted  
fS = 96 kHz, A-weighted  
101  
99  
at 25°C  
95  
93  
S/N  
Signal-to-noise ratio  
–40°C TA 125°C  
99  
(8)  
101  
(1) 384 fs where fs = 96kHz, and 512 where fs = 48 kHz and 96kHz are functionally tested. Other options are specified by design.  
(2) Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-ktypical pulldown resistor, in slave mode)  
(3) Specified by design  
(4) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant)  
(5) Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-ktypical pulldown resistor, 5-V tolerant)  
(6) Pins 7–9: LRCK, BCK (in master mode), DOUT  
(7) Analog performance specifications are tested using a System Two™ audio measurement system by Audio Precision™ with 400-Hz HPF  
and 20-kHz LPF in RMS mode.  
(8) fS = 96 kHz, system clock = 256 fS.  
Copyright © 2011–2012, Texas Instruments Incorporated  
3
 
 
 
 
 
PCM1808-Q1  
SLES265A MARCH 2011REVISED AUGUST 2012  
www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless  
otherwise noted  
PARAMETER  
TEST CONDITIONS  
MIN  
93  
TYP  
97  
MAX  
UNIT  
at 25°C  
fS = 48 kHz  
fS = 96 kHz  
Channel separation  
–40°C TA 125°C  
91  
97  
dB  
(8)  
91  
ANALOG INPUT  
Input voltage,  
–40°C TA 125°C  
0.58 VCC  
0.2 VCC  
0.6 VCC 0.65 VCC  
Vp-p  
Center voltage input range,  
–40°C TA 125°C  
0.5 VCC  
60  
0.8 VCC  
V
Input impedance  
kΩ  
Antialiasing filter frequency  
response  
–3 dB  
1.3  
MHz  
(3)  
DIGITAL FILTER PERFORMANCE, –40°C TA 125°C  
Pass band  
0.454 fS  
±0.05  
Hz  
Hz  
dB  
dB  
Stop band  
0.583 fS  
–65  
Pass-band ripple  
Stop-band attenuation  
Delay time  
17.4/fS  
0.019  
fS/1000  
HPF frequency response  
–3 dB  
POWER SUPPLY REQUIREMENTS  
VCC  
VDD  
4.5  
2.7  
5
3.3  
8.6  
1
5.5  
3.6  
11  
Voltage range,  
–40°C TA 125°C  
VDC  
(10)  
fS = 48 kHz, 96 kHz, –40°C TA 125°C  
mA  
ICC  
(11)  
Powered down  
μA  
at 25°C  
5.9  
5.9  
10.2  
150  
62  
8
(9)  
Supply current  
fS = 48 kHz  
mA  
–40°C TA 125°C  
10  
IDD  
(10)  
fS = 96 kHz  
mA  
(11)  
(11)  
Powered down  
fS = 48 kHz  
μA  
81  
mW  
(9)  
(10)  
Power dissipation  
fS = 96 kHz  
77  
Powered down  
500  
μW  
TEMPERATURE RANGE  
TA  
Operation temperature  
Thermal resistance  
–40  
125  
°C  
θJA  
170  
°C/W  
(9) Minimum load on LRCK (pin 7), BCK (pin 8), DOUT (pin 9)  
(10) fS = 96 kHz, system clock = 256 fS.  
(11) Power-down and reset functions enabled by halting SCKI, BCK, LRCK.  
4
Copyright © 2011–2012, Texas Instruments Incorporated  
 
 
 
 
PCM1808-Q1  
www.ti.com  
SLES265A MARCH 2011REVISED AUGUST 2012  
PIN ASSIGNMENTS  
PW PACKAGE  
(TOP VIEW)  
VREF  
AGND  
VCC  
1
2
3
4
5
6
7
VINR  
VINL  
FMT  
MD1  
MD0  
14  
13  
12  
11  
10  
9
VDD  
DGND  
SCKI  
LRCK  
DOUT  
BCK  
8
P0032-02  
TERMINAL FUNCTIONS  
TERMINAL  
NAME  
AGND  
I/O  
DESCRIPTION  
PIN  
2
I/O  
O
I
Analog GND  
(1)  
BCK  
DGND  
DOUT  
FMT  
LRCK  
MD0  
MD1  
SCKI  
VCC  
8
Audio data bit clock input/output  
Digital GND  
5
9
Audio data digital output  
(2)  
12  
7
Audio interface format select  
(1)  
I/O  
I
Audio data latch enable input/output  
(2)  
10  
11  
6
Audio interface mode select 0  
(2)  
I
Audio interface mode select 1  
(3)  
I
System clock input; 256 fS, 384 fS or 512 fS  
Analog power supply, 5-V  
3
I
VDD  
4
Digital power supply, 3.3-V  
Analog input, L-channel  
VINL  
13  
14  
1
VINR  
I
Analog input, R-channel  
VREF  
Reference voltage decoupling (= 0.5 VCC)  
(1) Schmitt-trigger input with internal pulldown (50-k, typical)  
(2) Schmitt-trigger input with internal pulldown (50-k, typical), 5-V tolerant  
(3) Schmitt-trigger input, 5-V tolerant  
Copyright © 2011–2012, Texas Instruments Incorporated  
5
PCM1808-Q1  
SLES265A MARCH 2011REVISED AUGUST 2012  
www.ti.com  
Functional Block Diagram  
Antialias  
LPF  
Delta-Sigma  
Modulator  
BCK  
LRCK  
DOUT  
FMT  
V
L
IN  
Serial  
Interface  
×1/64  
Decimation  
Filter  
with  
High-Pass Filter  
V
REF  
Reference  
Mode/  
Format  
Control  
MD1  
Antialias  
LPF  
Delta-Sigma  
Modulator  
MD0  
V R  
IN  
Clock and Timing Control  
SCKI  
Power Supply  
V
CC  
AGND DGND  
V
DD  
B0004-10  
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless  
otherwise noted.  
DECIMATION FILTER FREQUENCY RESPONSE  
OVERALL CHARACTERISTICS  
STOP-BAND ATTENUATION CHARACTERISTICS  
50  
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
−100  
0
−50  
−100  
−150  
−200  
0
8
16  
24  
32  
0.00  
0.25  
0.50  
0.75  
1.00  
Normalized Frequency [× f ]  
Frequency [× f ]  
S
S
G001  
G002  
Figure 1.  
Figure 2.  
6
Copyright © 2011–2012, Texas Instruments Incorporated  
PCM1808-Q1  
www.ti.com  
SLES265A MARCH 2011REVISED AUGUST 2012  
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (Continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless  
otherwise noted.  
DECIMATION FILTER FREQUENCY RESPONSE (Continued)  
PASS-BAND RIPPLE CHARACTERISTICS  
TRANSITION BAND CHARACTERISTICS  
0.2  
0.0  
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
−0.2  
−0.4  
−0.6  
−0.8  
−1.0  
–4.13 dB at 0.5 f  
S
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55  
Normalized Frequency [× f ]  
Normalized Frequency [× f ]  
S
S
G003  
G004  
Figure 3.  
Figure 4.  
HIGH-PASS FILTER FREQUENCY RESPONSE  
HPF STOP-BAND CHARACTERISTICS  
HPF PASS-BAND CHARACTERISTICS  
0.2  
0.0  
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
−100  
−0.2  
−0.4  
−0.6  
−0.8  
−1.0  
0.0  
0.1  
0.2  
0.3  
0.4  
0
1
2
3
4
Normalized Frequency [× f /1000]  
Normalized Frequency [× f /1000]  
S
S
G005  
G006  
Figure 5.  
Figure 6.  
Copyright © 2011–2012, Texas Instruments Incorporated  
7
PCM1808-Q1  
SLES265A MARCH 2011REVISED AUGUST 2012  
www.ti.com  
TYPICAL PERFORMANCE CURVES  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless  
otherwise noted.  
THD + N  
vs  
DYNAMIC RANGE AND SNR  
vs  
TEMPERATURE  
TEMPERATURE  
−87  
−88  
−89  
−90  
−91  
−92  
−93  
−94  
−95  
−96  
−97  
105  
104  
103  
102  
101  
100  
99  
Dynamic Range  
SNR  
98  
97  
96  
95  
−50  
−50  
−25  
0
25  
50  
75  
100  
−25  
0
25  
50  
75  
100  
T
A
− Free-Air Temperature − °C  
T
A
− Free-Air Temperature − °C  
G007  
G008  
Figure 7.  
Figure 8.  
THD + N  
vs  
DYNAMIC RANGE AND SNR  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
−87  
−88  
−89  
−90  
−91  
−92  
−93  
−94  
−95  
−96  
−97  
105  
104  
103  
102  
101  
100  
99  
Dynamic Range  
SNR  
98  
97  
96  
95  
4.25  
4.50  
4.75  
5.00  
5.25  
5.50  
5.75  
4.25  
4.50  
4.75  
5.00  
5.25  
5.50  
5.75  
V
CC  
− Supply Voltage − V  
V
CC  
− Supply Voltage − V  
G009  
G010  
Figure 9.  
Figure 10.  
8
Copyright © 2011–2012, Texas Instruments Incorporated  
PCM1808-Q1  
www.ti.com  
SLES265A MARCH 2011REVISED AUGUST 2012  
TYPICAL PERFORMANCE CURVES (Continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless  
otherwise noted.  
THD + N  
vs  
DYNAMIC RANGE AND SNR  
vs  
fSAMPLE CONDITION  
fSAMPLE CONDITION  
−87  
−88  
−89  
−90  
−91  
−92  
−93  
−94  
−95  
−96  
−97  
105  
104  
103  
102  
101  
100  
99  
Dynamic Range  
SNR  
98  
97  
(1)  
(2)  
(3)  
(1)  
(2)  
(3)  
System Clock = 384 f  
System Clock = 512 f  
System Clock = 256 f  
System Clock = 384 f  
System Clock = 512 f  
System Clock = 256 f  
S
S
96  
S
S
S
S
95  
(1)  
(2)  
(3)  
(1)  
(2)  
(3)  
44.1  
f
48  
96  
44.1  
f
48  
96  
Condition − kHz  
Condition − kHz  
SAMPLE  
SAMPLE  
G011  
G012  
Figure 11.  
Figure 12.  
OUTPUT SPECTRUM  
OUTPUT SPECTRUM (–0.5 dB, N = 8192)  
OUTPUT SPECTRUM (–60 dB, N = 8192)  
0
−20  
0
−20  
Input Level = −0.5 dB  
Data Points = 8192  
Input Level = −60 dB  
Data Points = 8192  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
0
5
10  
15  
20  
0
5
10  
15  
20  
f − Frequency − kHz  
f − Frequency − kHz  
G013  
G014  
Figure 13.  
Figure 14.  
Copyright © 2011–2012, Texas Instruments Incorporated  
9
PCM1808-Q1  
SLES265A MARCH 2011REVISED AUGUST 2012  
www.ti.com  
TYPICAL PERFORMANCE CURVES (Continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless  
otherwise noted.  
OUTPUT SPECTRUM (Continued)  
THD + N  
vs  
SIGNAL LEVEL  
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
−100  
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10  
0
Signal Level − dB  
G015  
Figure 15.  
SUPPLY CURRENT  
SUPPLY CURRENT  
vs  
fSAMPLE CONDITION  
15  
I
I
CC  
DD  
10  
5
(1)  
(2)  
(3)  
System Clock = 384 f  
System Clock = 512 f  
System Clock = 256 f  
S
S
S
0
(1)  
(2)  
(3)  
44.1  
f
48  
96  
Condition − kHz  
SAMPLE  
G016  
Figure 16.  
10  
Copyright © 2011–2012, Texas Instruments Incorporated  
PCM1808-Q1  
www.ti.com  
SLES265A MARCH 2011REVISED AUGUST 2012  
SYSTEM CLOCK  
The PCM1808-Q1 supports 256 fS, 384 fS and 512 fS as system clock, where fS is the audio sampling frequency.  
The system clock must be supplied on SCKI (pin 6).  
The PCM1808-Q1 has a system clock detection circuit which automatically senses if the system clock is  
operating at 256 fS, 384 fS, or 512 fS in slave mode. In master mode, the system clock frequency must be  
controlled through the serial control port, which uses MD1 (pin 111) and MD0 (pin 10). The system clock is  
divided down automatically to generate frequencies of 128 fS and 64 fS, which are used to operate the digital filter  
and the delta-sigma modulator, respectively.  
Table 1 shows some typical relationships between sampling frequency and system clock frequency, and  
Figure 17 shows system clock timing.  
Table 1. Sampling Frequency and System Clock Frequency  
SAMPLING FREQUENCY (kHz)  
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)  
256 fS  
2.048  
384 fS  
3.072  
512 fS  
4.096  
8
16  
4.096  
6.144  
8.192  
32  
8.192  
12.288  
16.9344  
18.432  
24.576  
33.8688  
36.864  
16.384  
22.5792  
24.576  
32.768  
45.1584  
49.152  
44.1  
48  
11.2896  
12.288  
16.384  
22.5792  
24.576  
64  
88.2  
96  
t
t
w(SCKL)  
w(SCKH)  
SCKI  
2 V  
SCKI  
0.8 V  
T0005B07  
SYMBOL  
PARAMETER  
MIN  
8
MAX  
UNIT  
ns  
tw(SCKH)  
tw(SCKL)  
System clock pulse duration, HIGH  
System clock pulse duration, LOW  
System clock duty cycle  
8
ns  
40%  
60%  
Figure 17. System Clock Timing  
FADE-IN AND FADE-OUT FUNCTIONS  
The PCM1808-Q1 has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions  
come into operation in some cases as described in several following sections. The level changes from 0 dB to  
mute or mute to 0 dB are performed using calculated pseudo S-shaped characteristics with zero-cross detection.  
Because of the zero-cross detection, the time needed for the fade in and fade out depends on the analog input  
frequency (fin). It takes 48/fin until processing is completed. If there is no zero cross during 8192/fS, DOUT is  
faded in or out by force during 48/fS (TIME OUT). Figure 18 illustrates the fade-in and fade-out operation  
processing.  
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Fade-In Complete  
Fade-In Start  
Fade-Out Start  
Fade-Out Complete  
DOUT  
(Contents)  
BPZ  
48/f or 48/f  
48/f or 48/f  
in S  
in  
S
T0080-01  
Figure 18. Fade-In and Fade-Out Operations  
POWER ON  
The PCM1808-Q1 has an internal power-on-reset circuit, and initialization (reset) is performed automatically  
when the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock  
counts after VDD > 2.2 V (typical), the PCM1808-Q1 stays in the reset state and the digital output is forced to  
zero. The digital output is valid after the reset state is released and the time of 8960/fS has elapsed. Because the  
fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the data corresponding to the analog  
input signal is obtained. Figure 19 illustrates the power-on timing and the digital output.  
2.6 V  
2.2 V  
1.8 V  
V
DD  
Reset  
Reset Release  
Operation  
Internal  
Reset  
1024 System Clocks  
8960/f  
S
System  
Clock  
DOUT  
Zero Data  
Normal Data  
Fade-In Complete  
Fade-In Start  
DOUT  
(Contents)  
BPZ  
48/f or 48/f  
in  
S
T0014-09  
Figure 19. Power-On Timing  
12  
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CLOCK-HALT POWER-DOWN AND RESET FUNCTION  
The PCM1808-Q1 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both  
master and slave modes. The function is available anytime after power on. Reset and power down are performed  
automatically 4 μs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808-Q1 stays  
in the reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release the  
reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024  
SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS  
until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt reset  
timing.  
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI  
within 4480/fS after SCKI is resumed. If it takes more than 4480/fS for BCK and LRCK to synchronize with SCKI,  
SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See the  
typical circuit connection diagram, Figure 26.  
To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIor  
the audio interface clocks BCK and LRCK (sampling rate fS) are changed on the fly.  
SCKI Halt  
SCKI Resume  
Fixed to Low or High  
SCKI  
t
Reset: t  
(RST)  
(CKR)  
Clock-Halt Reset  
Reset Release: t  
(REL)  
Internal  
Reset  
Operation  
Operation  
DOUT  
Normal Data  
Zero Data  
Normal Data  
Fade-In Complete  
Fade-In Start  
Normal Data  
DOUT  
(Contents)  
BPZ  
48/f or 48/f  
in  
S
T0081-01  
SYMBOL  
PARAMETER  
MIN  
MAX  
UNIT  
μs  
t(CKR)  
t(RST)  
t(REL)  
Delay time from SCKI halt to internal reset  
Delay time from SCKI resume to reset release  
Delay time from reset release to DOUT output  
4
1024 SCKI  
8960/fS  
μs  
μs  
Figure 20. Clock-Halt Power-Down and Reset Timing  
Copyright © 2011–2012, Texas Instruments Incorporated  
13  
 
PCM1808-Q1  
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SERIAL AUDIO DATA INTERFACE  
The PCM1808-Q1 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9).  
INTERFACE MODE  
The PCM1808-Q1 supports master mode and slave mode as interface modes, which are selected by MD1 (pin  
11) and MD0 (pin 10), as shown in Table 2. MD1 and MD0 must be set prior to power on.  
In master mode, the PCM1808-Q1 provides the timing of serial audio data communications between the  
PCM1808-Q1 and the digital audio processor or external circuit. While in slave mode, the PCM1808-Q1 receives  
the timing for data transfer from an external controller.  
Table 2. Interface Modes  
MD1 (Pin 11)  
Low  
MD0 (Pin 10)  
Low  
INTERFACE MODE  
Slave mode (256 fS, 384 fS, 512 fS autodetection)  
Master mode (512 fS)  
Low  
High  
High  
Low  
Master mode (384 fS)  
High  
High  
Master mode (256 fS)  
Master mode  
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated  
in the clock circuit of the PCM1808-Q1. The frequency of BCK is fixed at 64 BCK/frame.  
Slave mode  
In slave mode, BCK and LRCK work as input pins. The PCM1808-Q1 accepts 64-BCK/frame or 48-BCK/frame  
format (only for a 384-fS system clock), not 32-BCK/frame format.  
DATA FORMAT  
The PCM1808-Q1 supports two audio data formats in both master and slave modes. The data formats are  
selected by FMT (pin 12), as shown in Table 3. Figure 21 illustrates the data formats in slave mode and master  
mode.  
Table 3. Data Format  
FORMAT NO.  
FMT (Pin 12)  
Low  
FORMAT  
0
1
I2S, 24-bit  
High  
Left-justified, 24-bit  
14  
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FORMAT 0: FMT = LOW  
2
24-Bit, MSB-First, I S  
Left-Channel  
Right-Channel  
LRCK  
BCK  
DOUT  
1
2
3
22 23 24  
LSB  
1
2
3
22 23 24  
LSB  
MSB  
MSB  
FORMAT 1: FMT = HIGH  
24-Bit, MSB-First, Left-Justified  
Left-Channel  
Right-Channel  
LRCK  
BCK  
DOUT  
1
1
2
3
22 23 24  
LSB  
1
2
3
22 23 24  
LSB  
MSB  
MSB  
T0016-17  
Figure 21. Audio Data Format (LRCK and BCK Work as Inputs in Slave Mode  
and as Outputs in Master Mode)  
Copyright © 2011–2012, Texas Instruments Incorporated  
15  
PCM1808-Q1  
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INTERFACE TIMING  
Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively.  
t
(LRCP)  
1.4 V  
LRCK  
t
t
(BCKL)  
(LRSU)  
t
(LRHD)  
t
(BCKH)  
1.4 V  
BCK  
t
t
(LRDO)  
t
(CKDO)  
(BCKP)  
0.5 V  
DOUT  
DD  
T0017-02  
SYMBOL  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
ns  
t(BCKP)  
BCK period  
1/(64 fS)  
t(BCKH)  
t(BCKL)  
t(LRSU)  
t(LRHD)  
t(LRCP)  
t(CKDO)  
t(LRDO)  
tr  
BCK pulse duration, HIGH  
BCK pulse duration, LOW  
LRCK setup time to BCK rising edge  
LRCK hold time to BCK rising edge  
LRCK period  
1.5 × t(SCKI)  
ns  
1.5 × t(SCKI)  
ns  
50  
10  
ns  
ns  
10  
μs  
ns  
Delay time, BCK falling edge to DOUT valid  
Delay time, LRCK edge to DOUT valid  
Rise time of all signals  
–10  
–10  
40  
40  
20  
20  
ns  
ns  
tf  
Fall time of all signals  
ns  
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are from 10% to  
90% of the input/output signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) is the SCKI period.  
Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs)  
16  
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t
(LRCP)  
0.5 V  
LRCK  
DD  
t
(BCKL)  
t
t
(CKLR)  
(BCKH)  
0.5 V  
BCK  
DD  
t
t
t
(CKDO)  
(LRDO)  
(BCKP)  
0.5 V  
DOUT  
DD  
T0018-02  
SYMBOL  
t(BCKP)  
t(BCKH)  
t(BCKL)  
t(CKLR)  
t(LRCP)  
t(CKDO)  
t(LRDO)  
tr  
PARAMETER  
MIN  
150  
65  
TYP  
MAX  
2000  
1200  
1200  
20  
UNIT  
ns  
BCK period  
1/(64 fS)  
BCK pulse duration, HIGH  
BCK pulse duration, LOW  
ns  
65  
ns  
Delay time, BCK falling edge to LRCK valid  
LRCK period  
–10  
10  
ns  
1/fS  
125  
20  
μs  
Delay time, BCK falling edge to DOUT valid  
Delay time, LRCK edge to DOUT valid  
Rise time of all signals  
–10  
–10  
ns  
20  
ns  
20  
ns  
tf  
Fall time of all signals  
20  
ns  
NOTE: Timing measurement reference level is 0.5 VDD. Rise and fall times are from 10% to 90% of the input/output signal  
swing. Load capacitance of all signals is 20 pF.  
Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)  
1.4 V  
SCKI  
t
t
(SCKBCK)  
(SCKBCK)  
0.5 V  
BCK  
DD  
T0074-01  
SYMBOL  
PARAMETER  
Delay time, SCKI rising edge to BCK edge  
MIN  
TYP  
MAX  
UNIT  
ns  
t(SCKBCK)  
5
30  
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This  
timing is applied when SCKI frequency is less than 25 MHz.  
Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output)  
Copyright © 2011–2012, Texas Instruments Incorporated  
17  
PCM1808-Q1  
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www.ti.com  
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM  
In slave mode, the PCM1808-Q1 operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6).  
The PCM1808-Q1 does not require a specific phase relationship between LRCK and SCKI, but does require the  
synchronization of LRCK and SCKI.  
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48  
BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS  
and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI is  
established.  
In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization  
does not occur and the previously described digital output control and discontinuity do not occur.  
Figure 25 illustrates the digital output response for loss of synchronization and resynchronization. During  
undefined data, the PCM1808-Q1 can generate some noise in the audio signal. Also, the transition of normal  
data to undefined data creates a discontinuity in the digital output data, which can generate some noise in the  
audio signal. The digital output is valid after resynchronization completes and the time of 32/fS has elapsed.  
Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding  
to the analog input signal is obtained. If synchronization is lost during the fade-in or fade-out operation, the  
operation stops and DOUT (pin 9) is forced to zero data immediately. The fade-in operation resumes from mute  
after the time of 32/fS following resynchronization.  
Resynchronization  
Resynchronization  
Synchronization Lost  
Synchronization Lost  
State of  
Synchronization  
Synchronous  
Asynchronous  
Synchronous  
Asynchronous  
Synchronous  
1/f  
S
32/f  
S
Undefined  
Data  
DOUT  
Normal Data  
Zero Data  
Normal Data  
Zero Data  
Normal Data  
Fade-In Complete  
Fade-In Start  
Fade-In Restart  
Normal Data  
DOUT  
BPZ  
(Contents)  
32/f  
S
48/f or 48/f  
48/f or 48/f  
in S  
in  
S
T0082-01  
Figure 25. ADC Digital Output for Loss of Synchronization and Resynchronization  
18  
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APPLICATION INFORMATION  
TYPICAL CIRCUIT CONNECTION DIAGRAM  
Figure 26 is a typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analog  
inputs, VINL and VINR. If the performance of these filters is not adequate for an application, appropriate external  
antialiasing filters are needed. A passive RC filter (100 and 0.01 μF to 1 kand 1000 pF) generally is used.  
PCM1808  
(5)  
(1)  
(1)  
(3)  
C
C
C
+
+
1
5
+
R-ch IN  
L-ch IN  
1
2
3
4
5
6
7
V
V
R
14  
13  
12  
11  
10  
9
REF  
IN  
2
AGND  
V L  
IN  
(2)  
C
4
+
+
5 V  
V
CC  
V
DD  
FMT  
MD1  
4 µs (min)  
High/Low  
Pin  
Setting  
3.3 V  
(2)  
C
3
DGND  
SCKI  
MD0  
Mask  
DOUT  
BCK  
(4)  
X1  
8
LRCK  
PLL170x  
DSP  
or  
Audio  
Processor  
S0113-02  
(1) C1, C2: A 1-μF electrolytic capacitor gives 2.7 Hz (τ = 1 μF × 60 k) cutoff frequency for the input HPF in normal  
operation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period.  
(2) C3, C4: Bypass capacitors, 0.1-μF ceramic and 10-μF electrolytic, depending on layout and power supply  
(3) C5: 0.1-μF ceramic and 10-μF electrolytic capacitors are recommended.  
(4) X1: X1 masks the system clock input when using the clock-halt reset function with external control.  
(5) Optional external antialiasing filter could be required, depending on the application.  
Figure 26. Typical Circuit Connection Diagram  
BOARD DESIGN AND LAYOUT CONSIDERATIONS  
VCC, VDD PINS  
The digital and analog power supply lines to the PCM1808-Q1 should be bypassed to the corresponding ground  
pins with both 0.1-μF ceramic and 10-μF electrolytic capacitors as close to the pins as possible to maximize the  
dynamic performance of the ADC.  
AGND, DGND PINS  
To maximize the dynamic performance of the PCM1808-Q1, the analog and digital grounds are not internally  
connected. These grounds should have low impedance to avoid digital noise feedback into the analog ground.  
They should be connected directly to each other under the PCM1808-Q1 package to reduce potential noise  
problems.  
VINL, VINR PINS  
VINL and VINR are single-ended inputs. The antialias low-pass filters are integrated on these inputs to remove the  
high-frequency noise outside the audio band. If the performance of these filters is not adequate for an  
application, appropriate external antialiasing filters are required. A passive RC filter (100 and 0.01 μF to 1 kΩ  
and 1000 pF) is generally used.  
Copyright © 2011–2012, Texas Instruments Incorporated  
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PCM1808-Q1  
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VREF PIN  
To ensure low source impedance of the ADC references, 0.1-μF ceramic and 10-μF electrolytic capacitors are  
recommended between VREF and AGND. These capacitors should be located as close as possible to the VREF  
pin to reduce dynamic errors on the ADC references.  
DOUT PIN  
The DOUT pin has a large load-drive capability, but if the DOUT line is long, locating a buffer near the  
PCM1808-Q1 and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and  
maximize the dynamic performance of the ADC.  
SYSTEM CLOCK  
The quality of the system clock can influence dynamic performance, as the PCM1808-Q1 operates based on a  
system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference  
between system clock transition and BCK or LRCK transition in slave mode.  
20  
Copyright © 2011–2012, Texas Instruments Incorporated  
PCM1808-Q1  
www.ti.com  
SLES265A MARCH 2011REVISED AUGUST 2012  
REVISION HISTORY  
Changes from Original (March, 2011) to Revision A  
Page  
ROC CHANGES: Added 2.93 min and 3.23 max to analog input voltage row .................................................................... 2  
ELEC CHAR CHANGES: Added -40°C TA 125°C to the header for DC accuracy and the rows for system clock  
frequency, input logic level, and output logic level ............................................................................................................... 3  
Added test condition row to VIN = VDD (input logic current) at -40°C TA 125°C with typ value 65 and max value  
150 ........................................................................................................................................................................................ 3  
Added test condition row to IOUT = –4 mA (output logic level) at -40°C TA 125°C with a min value of 2.7; added  
test condition of 25°C with min value of 2.8 ......................................................................................................................... 3  
Added test condition of 25°C to VIN = –0.5 dB, fS = 48 kHz (THD + N) with max value of –87, and added row with  
test condition of -40°C TA 125°C and max value –85 ..................................................................................................... 3  
Added test condition 25°C and min value of 95; added test condition row for -40°C TA 125°C with min value of  
93 to fS = 48 kHz, A-weighted row (dynamic range and signal-to-noise) ............................................................................. 3  
Added test condition 25°C and min value of 93; added test condition row for -40°C TA 125°C with min value of  
91 to fS = 48 kHz (channel separation) ................................................................................................................................. 4  
Added min value 0.58 VCC and max value 0.65 VCC to input voltage; added 0.2 VCC min and 0.8 VCC max to center  
voltage; changed center voltage Vref to center voltage input range .................................................................................... 4  
Added -40°C TA 125°C to input voltage, center voltage, digital filter performance header, supply current, and  
voltage range rows ............................................................................................................................................................... 4  
Added test condition row with -40°C TA 125°C to fS = 48 kHz (supply current) with a typ value of 5.9 and a max  
value of 10 ............................................................................................................................................................................ 4  
Copyright © 2011–2012, Texas Instruments Incorporated  
21  
PACKAGE OPTION ADDENDUM  
www.ti.com  
31-Jul-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
PCM1808QPWRQ1  
ACTIVE  
TSSOP  
PW  
14  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF PCM1808-Q1 :  
Catalog: PCM1808  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
31-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
PCM1808QPWRQ1  
TSSOP  
PW  
14  
2000  
330.0  
12.4  
6.9  
5.6  
1.6  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
31-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
TSSOP PW 14  
SPQ  
Length (mm) Width (mm) Height (mm)  
367.0 367.0 35.0  
PCM1808QPWRQ1  
2000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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配单直通车
PCM1808QPWRQ1产品参数
型号:PCM1808QPWRQ1
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25
针数:14
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:6 weeks
风险等级:1.74
最大模拟输入电压:3 V
最小模拟输入电压:
转换器类型:ADC, DELTA-SIGMA
JESD-30 代码:R-PDSO-G14
JESD-609代码:e4
长度:5 mm
湿度敏感等级:3
模拟输入通道数量:2
位数:24
功能数量:1
端子数量:14
最高工作温度:125 °C
最低工作温度:-40 °C
输出位码:2'S COMPLEMENT BINARY
输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:3.3,5 V
认证状态:Not Qualified
采样速率:0.096 MHz
筛选级别:AEC-Q100
座面最大高度:1.2 mm
子类别:Analog to Digital Converters
最大压摆率:11 mA
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm
Base Number Matches:1
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