PCM1851PJT原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

Burr-Brown Products

from Texas Instruments

PCM1850

PCM1851

SLES108 − MARCH 2004

24-BIT, 96-kHz STEREO A/D CONVERTER

WITH 6 y 2-CHANNEL MUX AND PGA

− Master/Slave Mode Selectable

FEATURES

− Data Formats: 24-Bit Left Justified,

D

Multiplexer and Programmable-Gain Amplifier

(PGA)

− 6×2-Channel Single-Ended Inputs

− Multiplexed Output

2

24-Bit I S, 16-, 24-Bit Right Justified

D

Mode Control by Serial Interface:

− With SPI Control (PCM1850)

2

− With I C Control (PCM1851)

− Maximum Input Level: 2.4 V rms

− Input Resistance: 50 kΩ, Minimum

− PGA Gain: 11 to –11 dB Range,

0.5 dB/Step

D

Sampling Rate: 16–96 kHz

System Clock: 256 f , 384 f , 512 f , 768 f

s

Dual Power Supplies:

5 V for Analog, 3.3 V for Digital

Package: 32-Pin TQFP

Lead-Free Product

D

24-Bit Delta-Sigma Stereo A/D Converter

Antialiasing Filter Included

D

Oversampling Decimation Filter

− Oversampling Frequency: ×64

− Pass-Band Ripple: 0.05 dB

APPLICATIONS

− Stop-Band Attenuation: –65 dB

− On-Chip High-Pass Filter: 0.91 Hz (48 kHz)

D

DVD/HDD/DVD+HDD Recorder

AV Amplifier Receiver

CD Recorder

D

High Performance

− THD+N: 0.0023% (Typically)

− SNR: 101 dB (Typically)

− Dynamic Range: 102 dB (Typically)

MD Recorder

Multi-Track Recorder

Electric Musical Instrument

PCM Audio Interface

DESCRIPTION

The PCM1850/1851 is a high-performance, low-cost, single-chip stereo analog-to-digital converter with a single-ended

analog front end that consists of a 6-stereo-input multiplexer and wide-range PGA. The PCM1850/1851 includes a

delta-sigma modulator with 64-times oversampling, a digital decimation filter and a low-cut filter that removes the dc

component of the input signal. For various applications, the PCM1850/1851 supports two modes (master and slave) and

four data formats through a serial control interface, SPI for the PCM1850 and I²C for the PCM1851, respectively. The

PCM1850/1851 is suitable for a wide variety of cost-sensitive DVD/CD/MD recorder and receiver applications where good

performance and operation from a 5-V analog supply and 3.3-V digital supply is required. The PCM1850/1851 is fabricated

using a highly advanced CMOS process and is available in a small 32-pin TQFP package.

ORDERING INFORMATION

OPERATION

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

PRODUCT

PACKAGE

PACKAGE CODE

PCM1850PJT

PCM1850PJTR

PCM1851PJT

PCM1851PJTR

Tray

PCM1850PJT

PCM1851PJT

32-Lead TQFP

32PJT

–40°C to 85°C

PCM1850

PCM1851

Tape and reel

Tray

Tape and reel

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to

damage because very small parametric changes could cause the device not to meet its published specifications.

BLOCK DIAGRAM

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

L1

L2

L3

L4

L5

L6

BCK

Single-Ended

MUX and PGA

Delta-Sigma

Modulator

LRCK

DOUT

MOUTL

Audio

Data

OVER

Decimation

Filter

with

High-Pass Filter

Interface

V

1

REF

Reference

V

REF

S

2

V

REF

Control

Data

Interface

(1)

MS (ADR)

MD (SDA)

(1)

V

R1

R2

R3

R4

R5

R6

MC (SCL)

IN

Single-Ended

MUX and PGA

Delta-Sigma

Modulator

TEST0

TEST1

MOUTR

RST

Clock and Timing Control

Power Supply

SCKI

V

CC

AGND DGND

V

DD

(1)

PCM1850 (PCM1851)

PIN ASSIGNMENTS

PCM1850

PCM1851

(TOP VIEW)

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

V

V_REF

V_cc

AGND

MS

_REFS

V_INR2

V_INL2

V_INR1

V_INL1

MOUTL

MOUTR

RST

V

V_REF

V_cc

AGND

ADR

_REFS

V_INR2

V_INL2

V_INR1

V_INL1

MOUTL

MOUTR

RST

1

2

1

2

MC

MD

SCL

SDA

TEST1

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7 8

2

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

Terminal Functions

PCM1850

TERMINAL

I/O

DESCRIPTIONS

NAME

AGND

BCK

29

2

—

Analog GND

(1)

I/O Bit clock input/output

DGND

DOUT

LRCK

MC

5

—

O

Digital GND

3

Audio data output

(1)

1

I/O Sampling clock input/output

(2)

31

32

12

11

30

4

I

Mode control clock input

(2)

MD

Mode control data input

MOUTL

MOUTR

MS

O

I

Multiplexer output, L-channel

Multiplexer output, R-channel

(3)

Mode control select input

OVER

RST

O

I

Overflow flag

(3)

10

7

Reset, active LOW

(2)

SCKI

I

System clock input; 256 f , 384 f , 512 f or 768 f

S S S S

(3)

TEST0

TEST1

8

I

Test 0, must be connected to GND

Test 1, must be connected to GND

Analog power supply, 5-V

Digital power supply, 3.3-V

Analog input 1, L-channel

Analog input 2, L-channel

Analog input 3, L-channel

Analog input 4, L-channel

Analog input 5, L-channel

Analog input 6, L-channel

Analog input 1, R-channel

Analog input 2, R-channel

Analog input 3, R-channel

Analog input 4, R-channel

Analog input 5, R-channel

Analog input 6, R-channel

(3)

9

I

V

CC

V

DD

28

6

—

I

V

L1

13

15

17

19

21

23

14

16

18

20

22

24

25

26

27

IN

V

L2

L3

L4

L5

L6

I

V

R1

R2

R3

R4

R5

R6

I

IN

I

IN

I

IN

I

IN

I

IN

I

IN

V S

REF

—

Reference S decoupling capacitor (= 0.5 V

)

CC

V

1

2

Reference 1 decoupling capacitor (= 0.5 V

)

REF

CC

Reference 2 decoupling capacitor (= V

)

CC

REF

(1)

(2)

(3)

Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically)

Schmitt-trigger input, 5-V tolerant

Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically), 5-V tolerant

3

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

Terminal Functions

PCM1851

TERMINAL

NAME

ADR

I/O

DESCRIPTIONS

30

29

2

(1)

I

—

I/O

—

O

I/O

O

I

Mode control address select input

Analog GND

AGND

BCK

(2)

Bit clock input/output

DGND

DOUT

LRCK

5

Digital GND

3

Audio data output

(2)

1

Sampling clock input/output

MOUTL

MOUTR

OVER

RST

12

11

4

Multiplexer output, L-channel

Multiplexer output, R-channel

Overflow flag

(1)

10

7

Reset, active LOW

(3)

SCKI

I

System clock input; 256 f , 384 f , 512 f or 768 f

S

(3)

SCL

31

32

8

I

Mode control clock input

(4)

SDA

I/O

I

Mode control data input/output

(1)

TEST0

TEST1

Test 0, must be connected to GND

Test 1, must be connected to GND

Analog power supply, 5-V

Digital power supply, 3.3-V

Analog input 1, L-channel

Analog input 2, L-channel

Analog input 3, L-channel

Analog input 4, L-channel

Analog input 5, L-channel

Analog input 6, L-channel

Analog input 1, R-channel

Analog input 2, R-channel

Analog input 3, R-channel

Analog input 4, R-channel

Analog input 5, R-channel

Analog input 6, R-channel

9

I

V

CC

V

DD

28

6

—

I

V

L1

13

15

17

19

21

23

14

16

18

20

22

24

25

26

27

IN

V

L2

L3

L4

L5

L6

I

V

R1

R2

R3

R4

R5

R6

I

IN

I

IN

I

IN

I

IN

I

IN

I

IN

V S

REF

—

Reference S decoupling capacitor (= 0.5 V

)

CC

V

1

2

Reference 1 decoupling capacitor (= 0.5 V

)

REF

CC

Reference 2 decoupling capacitor (= V

)

CC

REF

(1)

(2)

(3)

(4)

Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically), 5-V tolerant

Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically)

Schmitt-trigger input, 5-V tolerant

Schmitt-trigger input/open-drain LOW output, 5-V tolerant

4

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

Supply voltage: V

–0.3 V to 6.5 V

–0.3 V to 4 V

0.1 V

CC

DD

Ground voltage differences: AGND, DGND

Digital input voltage: LRCK, BCK, DOUT, OVER

–0.3 V to (V + 0.3 V) < 4 V

DD

(2)

Digital input voltage: RST, SCKI, MS (ADR) , MC (SCL) , MD (SDA) , TEST0, TEST1

–0.3 V to 6.5 V

Analog input voltage: V L1–6, V R1–6

–3 V to (V + 3 V) < 9 V

CC

IN

Analog input voltage: MOUTL, MOUTR, V

Input current (any pins except supplies)

Ambient temperature under bias

Storage temperature

1, V 2, V S

REF REF REF

–0.3 V to (V + 0.3 V) < 6.5 V

CC

10 mA

–40°C to 125°C

–55°C to 150°C

150°C

Junction temperature

Lead temperature (soldering)

Package temperature (IR reflow, peak)

260°C, 5 s

260°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PCM1850 (PCM1851)

(2)

ELECTRICAL CHARACTERISTICS

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

PCM1850PJT, PCM1851PJT

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

DIGITAL INPUT/OUTPUT

DATA FORMAT

2

Audio data interface format

Left-justified, I S, right-justified

16, 24

Audio data bit length

Audio data format

Sampling frequency

bits

MSB-first, 2s complement

f

S

16

48

96

kHz

256 f

384 f

512 f

768 f

4.096

6.144

8.192

12.288

18.432

24.576

36.864

24.576

36.864

49.152

—

S

System clock frequency

MHz

INPUT LOGIC

(1)

V

2

0

2

0

V

DD

IH

IL

IH

IL

(1)

0.8

5.5

0.8

10

Input logic level

VDC

(2) (3)

(2)

I

IH

I

IL

I

IH

I

IL

V

= V

IN

DD

(2)

V

= 0

10

IN

Input logic current

µA

(1) (3)

V

IN

= V

65

100

10

V

= 0

IN

(1)

(2)

(3)

Pins 1, 2: LRCK, BCK (In slave mode, Schmitt-trigger input, with 50-kΩ typical pulldown resistor)

Pins 7, 31, 32: SCKI, MC/SCL (PCM1850/1851), MD/SDA (PCM1850/1851) (Schmitt-trigger input, 5-V tolerant)

Pins 8–10, 30: TEST0, TEST1, RST, MS/ADR (PCM1850/1851) (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)

5

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

ELECTRICAL CHARACTERISTICS (Continued)

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

PCM1850PJT, PCM1851PJT

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

OUTPUT LOGIC

(1)

V

I

= –4 mA

= 4 mA

2.8

OH

OUT

Output logic level

VDC

(1) (2)

OL

V

I

0.5

OUT

AFE MULTIPLEXER

Input channels

Input level for full scale

6

2

2.4

Vrms

V

Center voltage (V

1)

Selected channel

Unselected channel

Selected channel

Unselected channel

0.5 V

REF

CC

S)

REF

V

CC

50

169

57

Input impedance

kΩ

AFE PGA

Gain range

Gain step

–11

0

0.5

11

dB

Monotonicity

Specified

300

Antialiasing filter frequency response

MONITOR OUTPUT

Output level for full scale

Output load

–3 dB, PGA gain = –5.5 dB

kHz

AC-coupled, >10 kΩ

AC-coupled

0.6 V

Vp-p

CC

10

kΩ

(3) (4)

THD+N

AC-coupled, 10 kΩ, 3 Vp-p output,

AC-coupled, 10 kΩ

0.0016%

104

(3) (4)

S/N ratio

dB

% of FSR

V

(3) (4)

Gain error

AC-coupled, 10 kΩ

–3

Center voltage

0.5 V

CC

ADC

Resolution

24

bits

Full scale input voltage

0.6 V

Vp-p

CC

ACCURACY

Gain mismatch, channel-to-channel

1

2

3

5

% of FSR

Gain error

Bipolar zero error

High-pass filter bypass

(1)

(2)

(3)

Pins 1–4: LRCK, BCK (in master mode), DOUT, OVER

Pin 32: SDA (PCM1851) (open-drain LOW output)

Analog performance specifications are tested with the System Two™ audio measurement system by Audio Precision™, using a 400-Hz HPF and

20-kHz LPF in the RMS mode at f = 1 kHz.

IN

(4)

Reference level (0 dB) is specified as 2-V rms input on V L[1:6] and V R[1:6] pins with PGA gain of –5.5 dB.

IN

Audio Precision and System Two are trademarks of Audio Precision, Inc.

6

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

ELECTRICAL CHARACTERISTICS (Continued)

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

PCM1850PJT, PCM1851PJT

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

(1) (2)

DYANAMIC PEFORMANCE

f

S

= 48 kHz, V = –0.5 dB (1.89 Vrms)

0.0023% 0.004%

0.0027%

IN

(3)

(4),

THD+N

f

S

= 96 kHz

V

IN

= –0.5 dB (1.89

Vrms)

f

= 48 kHz, V = –60 dB (2 mVrms)

1%

102

101

102

98

S

IN

(4),

f

= 96 kHz

V

IN

= –60 dB (2 mVrms)

S

f

S

= 48 kHz, A-weighted

96

92

90

(3)

Dynamic range

dB

(4)

f

S

= 96 kHz , A-weighted

f

S

= 48 kHz, A-weighted

(3)

S/N ratio

(4)

f

S

= 96 kHz , A-weighted

f

S

= 48 kHz

Channel separation (between L-ch and

(3)

(4)

R-ch)

f

= 96 kHz

100

96

S

f

= 48 kHz

S

(5)

Channel separation (among channels)

(4)

= 96 kHz

96

S

DIGITAL FILTER PERFORMANCE

Pass band

0.454 f

Hz

dB

s

S

Stop band

0.583 f

–65

S

Pass-band ripple

0.05

Stop-band attenuation

Delay time

17.4/f

S

HPF frequency response

POWER SUPPLY REQUIREMENTS

–3 dB

0.019 f

mHz

S

V

4.5

2.7

5

5.5

3.6

35

VDC

mA

CC

DD

Voltage range

Supply current

3.3

28

Operation

I

CC

(7)

Power down

= 48 kHz

190

6

µA

f

10

S

(6)

mA

(4)

f

= 96 kHz

12

S

I

DD

(7)

Power down , PCM1850

80

µA

(7)

Power down , PCM1851

280

160

180

1.2

1.9

f

= 48 kHz

208

S

Power dissipation, operation

(4)

f

= 96 kHz

PCM1850

PCM1851

S

mW

(7)

Power dissipation, power down

TEMPERATURE RANGE

Operation temperature

Thermal resistance (θ

–40

85

°C

)

JA

80

°C/W

(1)

Analog performance specifications are tested with the System Two™ audio measurement system by Audio Precision™, using a 400-Hz HPF and

20-kHz LPF in the RMS mode at f = 1 kHz.

IN

(2)

(3)

(4)

(5)

(6)

(7)

Reference level (0 dB) is specified as 2-V rms input on V L[1:6] and V R[1:6] pins with PGA gain of –5.5 dB.

IN

Unselected channel inputs are terminated to AGND with 0.33 µF.

f

S

= 96 kHz, system clock = 256 f .

S

2-V rms input is applied to all unselected channels, and input of selected channel is terminated to AGND with 0.33 µF.

Minimum load on DOUT (pin 3), BCK (pin 2), LRCK (pin 1)

Halt SCKI, BCK, LRCK.

7

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER

DIGITAL FILTER

Decimation Filter Frequency Response

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

50

0

−50

−100

−150

−200

0.00

0.25

0.50

0.75

1.00

0

8

16

24

32

Frequency[× f ]

S

Frequency[× f ]

S

Figure 1. Overall Characteristics

Figure 2. Stop-Band Attenuation Characteristics

AMPLITUDE

vs

FREQUENCY

AMPLITUDE

vs

FREQUENCY

0

0.2

0.0

–4.13 dB at 0.5×

−1

−2

−3

−0.2

−0.4

−0.6

−0.8

−1.0

−4

−5

−6

−7

−8

−9

−10

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.45

0.47

0.49

0.51

0.53

0.55

Frequency[× f ]

S

Frequency[× f ]

S

Figure 3. Pass-Band Ripple Characteristics

Figure 4. Transition-Band Characteristics

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

8

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

High-Pass Filter Frequency Response

AMPLITUDE

vs

FREQUENCY

AMPLITUDE

vs

FREQUENCY

0.2

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

0.0

−0.2

−0.4

−0.6

−0.8

−1.0

0.0

0.1

0.2

0.3

0.4

0

1

2

3

4

Frequency [× f /1000]

S

Figure 5. HPF Pass-Band Characteristics

Figure 6. HPF Stop-Band Characteristics

ANALOG FILTER

Antialiasing Filter Frequency Response (at PGA gain = –5.5 dB)

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

0

−5

−5.5

−5.6

−5.7

−5.8

−5.9

−6.0

−6.1

−6.2

−6.3

−6.4

−6.5

f

= 300 kHz

–3dB

−10

−15

−20

−25

−30

−35

−40

−45

−50

0.1

1

10

100

1k

1

10

100

1k

10k

f – Frequency – kHz

Figure 7. Antialiasing Filter Pass-Band

Characteristics

Figure 8. Antialiasing Filter Stop-Band

Characteristics

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

9

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB

TOTAL HARMONIC DISTORTION + NOISE

vs

FREE-AIR TEMPERATURE

DYNAMIC RANGE and SNR

vs

FREE-AIR TEMPERATURE

0.004

0.003

0.002

0.001

107

106

105

104

103

102

101

100

99

Dynamic Range

SNR

98

97

−40

−15

10

35

60

85

−40

−15

10

35

60

85

T – Free-Air Temperature – °C

A

T – Free-Air Temperature – °C

A

Figure 9

Figure 10

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE and SNR

vs

SUPPLY VOLTAGE

0.004

0.003

0.002

0.001

107

106

105

104

103

102

101

100

99

Dynamic Range

SNR

98

97

4.5

4.7

4.9

5.1

5.3

5.5

4.7

4.9

5.1

5.3

5.5

V

CC

– Supply Voltage – V

V

CC

– Supply Voltage – V

Figure 11

Figure 12

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

10

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE and SNR

vs

f_SAMPLECONDITION

0.004

0.003

0.002

0.001

107

106

105

104

103

102

101

100

99

Dynamic Range

SNR

98

97

16

36

56

76

96

16

36

56

76

96

f

Condition – kHz

f

Condition – kHz

SAMPLE

Figure 14

Figure 13

OUTPUT SPECTRUM

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

0

Input Level = –60 dB

Data Points = 8192

Input Level = –0.5 dB

Data Points = 8192

−20

−40

−20

−40

−60

−80

−100

−120

−140

−100

−120

−140

0

5

10

15

20

0

5

10

f – Frequency – kHz

15

20

f – Frequency – kHz

Figure 15

Figure 16

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

11

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TOTAL HARMONIC DISTORTION + NOISE

vs

SIGNAL LEVEL

100

10

1

0.1

0.01

0.001

−100 −90 −80 −70 −60 −50 −40 −30 −20 −10

0

Signal Level – dB

Figure 17

SUPPLY CURRENT

PGA GAIN LINEARITY

SUPPLY CURRENT

vs

OVERALL GAIN

vs

f_SAMPLECONDITION

GAIN SETTING

30

25

20

15

10

5

11

9

I

CC

7

5

3

1

−1

−3

−5

−7

−9

−11

I

DD

0

16

36

f

56

76

96

−11 −9 −7 −5 −3 −1

1

3

5

7

9

11

Condition – kHz

Gain Setting – dB

SAMPLE

Figure 18

Figure 19

All specifications at T = 25°C, V = 5 V, V = 3.3 V, master mode, f = 48 kHz, system clock = 256 f , 24-bit data, unless otherwise noted

A

CC

DD

S

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SYSTEM CLOCK

The PCM1850/1851 supports 256 f_S, 384 f_S, 512 f_S,and 768 f_Sas the system clock, where f_Sis the audio sampling

frequency. The system clock must be supplied on SCKI (pin 7).

The PCM1850/1851 has a system clock detection circuit which automatically senses if the system clock is operating at

256 f_S, 384 f_S, 512 f_Sor 768 f_Sin slave mode. In master mode, the system clock frequency must be selected by mode control

via the serial port. The 768-f_Ssystem clock is not available in master mode or for f_S= 88.2 kHz and 96 kHz in the slave

mode. The system clock is divided into 128 f_Sand 64 f_Sautomatically, and these frequencies are used to operate the digital

filter and the delta-sigma modulator, respectively.

Table 1 shows the relationship of typical sampling frequency to system clock frequency, and Figure 20 shows system clock

timing.

Table 1. Sampling Frequency and System Clock Frequency

SAMPLING RATE FREQUENCY

(kHz)

SYSTEM CLOCK FREQUENCY (MHz)

384 f 512 f

(1)

256 f

768 f

S

32

8.192

11.2896

12.288

16.384

22.5792

24.576

12.288

16.9344

18.432

24.576

33.8688

36.864

16.384

22.5792

24.576

32.768

45.1584

49.152

24.576

33.8688

36.864

49.152

—

44.1

48

64

88.2

96

—

(1)

Slave mode only

t

(SCKH)

H

2.0 V

0.8 V

SCKI

L

t

(SCKL)

SYMBOL

PARAMETER

MIN

8

MAX

UNIT

ns

t

System clock pulse duration, HIGH

System clock pulse duration, LOW

SCKH

t

8

ns

SCKL

Figure 20. System Clock Timing

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POWER-ON RESET SEQUENCE

The PCM1850/1851 has an internal power-on reset circuit, and initialization (reset) is performed automatically at the time

that the power supply (V_DD) exceeds 2.2 V (typ). While V_DD< 2.2 V (typ) and for 1024 system clocks after V_DD> 2.2 V (typ),

the PCM1850/1851 stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset

state is released and the time of 4500/f_Shas passed. At the moment of the power-on reset release, the PCM1850/1851

does not need a system clock. Figure 21 illustrates the internal power-on reset timing and the digital output for power-on

reset.

2.6 V

2.2 V

1.8 V

V

DD

Reset

Release From Reset

Internal Reset

1024 System Clocks

4500/f

S

System Clock

DOUT

Zero Data

Normal Data

Figure 21. Internal Power-On Reset Timing

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ANALOG FRONT END

The PCM1850/1851 has a built-in analog front-end circuit, which is shown in the block diagram of Figure 22. Selection of

the multiplexer input and PGA gain is controlled by mode control via the serial port as shown in Table 2 and Table 3. The

change of the input selection and the gain selection is performed immediately after the serial control packet for the change

is sent. A popping noise or other unexpected transient response could be generated in the audio signal during channel and

gain change. Because the PCM1850/1851 has no zero-cross detection and no other buffering capability for channel and

gain change, appropriate data handling in the digital domain is recommended to control transients.

The PCM1850/1851 analog front end permits only ac input via an input capacitor; dc input is prohibited. A signal source

resistance of less than 1 kΩ is recommended for the V_INxx pins.

All unselected channel inputs are terminated V_REFS (= 0.5 V_CC) using a resistor, typically 57 kΩ.

The PCM1850/1851 employs MOUTL/R pins (pins 12 and 11) to monitor the multiplexer output. The load on these pins

must be ac-coupled and not less than 10 kΩ. The full-scale output level is typically 0.6 V_CC

.

V

L1

R

IN

R

V

L2

PGA

R

(11 dB to –11 dB)

with MUX

G = –1

LIN+

LIN–

V L6

IN

R

V S

REF

V

REF

1

MOUTL

(= 0.5 V )

CC

(= 0.5 V )

CC

Figure 22. Analog Front-End Block Diagram (L-channel)

Table 2. Multiplexer Input Selection

CH2

0

CH1

0

CH0

0

CHANNEL

Mute

0

1

Channel 1 (default)

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Mute

0

1

0

1

0

1

0

1

0

1

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Table 3. PGA Gain Selection

PG5

PG4

0

1

0

1

PG3

1

0

1

0

1

0

PG2

0

1

0

1

0

1

0

1

0

1

0

1

PG1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PG0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

PGA GAIN [dB]

R

IN

[kΩ, Typical]

201

199

196

193

190

188

185

181

178

175

172

169

165

162

158

155

151

147

144

140

136

133

129

125

122

118

114

111

107

103

100

96

0

1

–11 (default)

–10.5

–10

–9.5

–9

–8.5

–8

–7.5

–7

–6.5

–6

–5.5

–5

–4.5

–4

–3.5

–3

–2.5

–2

–1.5

–1

–0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

93

5.5

6

89

86

6.5

7

83

80

7.5

8

77

73

8.5

9

70

68

9.5

10

65

62

10.5

11

59

57

258

:

R_IN(kW, typical) +

NOTE

Ǔ

1 ) 10^ǒ^GAINń20

The PCM1850/1851 becaomes mute for PG[5:0] values other than those listed.

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SERIAL AUDIO DATA INTERFACE

The PCM1850/1851 interfaces with the audio system through BCK (pin 2), LRCK (pin 1), and DOUT (pin 3).

Interface Mode

The PCM1850/1851 supports both master and slave modes as interface modes, and they are selected by mode control

via the serial port as shown in Table 4.

In master mode, the PCM1850/1851 provides the timing for serial audio data communications between the PCM1850/1851

and the digital audio processor or external circuit. While in slave mode, the PCM1850/1851 receives the timing for data

transfer from an external controller.

Table 4. Interface Mode

MD1

MD0

INTERFACE MODE

Slave mode (256 f , 384 f , 512 f , 768 f ) (default)

0

1

0

1

0

1

S

Master mode (256 f )

S

Master mode (384 f )

S

Master mode (512 f )

S

Master Mode

In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated in the

clock and timing control circuit of the PCM1850/1851. The frequency of BCK is fixed at 64 × LRCK. A 768-f_Ssystem clock

is not available in master mode.

Slave Mode

In slave mode, BCK and LRCK work as input pins. The PCM1850/1851 accepts the 64 BCK/LRCK or 48 BCK/LRCK (only

for 384 f_SSCKI) format. A 768-f_Ssystem clock is not available for f_S= 88.2 kHz and 96 kHz in slave mode.

Data Format

The PCM1850/1851 supports four audio data formats in both master and slave modes, and they are selected by mode

control via the serial port as shown in Table 5. Figure 23 illustrates the data formats in both slave and master modes.

Table 5. Data Format

FORMAT NO.

FMT2

FMT1

FMT0

FORMAT

0

1

2

3

1

0

1

0

1

Left-justified, 24-bit

2

I S, 24-bit, (default)

Right-justified, 24-bit

Right-justified, 16-bit

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FORMAT 0: FMT[2:0] = 101b

24-Bit, MSB-First, Left-Justified

LRCK

BCK

Left-Channel

Right-Channel

DOUT

1

2

3

22 23 24

LSB

1

2

3

22 23 24

LSB

1

MSB

FORMAT 1: FMT[2:0] = 100b

2

24-Bit, MSB-First, I S

LRCK

BCK

Left-Channel

Right-Channel

DOUT

1

2

3

22 23 24

LSB

1

2

3

22 23 24

LSB

MSB

FORMAT 2: FMT[2:0] = 000b

24-Bit, MSB-First, Right-Justified

Left-Channel

Right-Channel

LRCK

BCK

DOUT

24

1

2

3

22 23 24

1

2

3

22 23 24

MSB

LSB

FORMAT 3: FMT[2:0] = 011b

16-Bit, MSB-First, Right-Justified

Left-Channel

Right-Channel

LRCK

BCK

DOUT

16

1

2

3

14 15 16

LSB

1

2

3

14 15 16

LSB

MSB

Figure 23. Audio Data Format

(LRCK, BCK Work as Inputs in Slave Mode and Outputs in Master Mode)

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Interface Timing

Figure 24 and Figure 25 illustrate the interface timing in slave and master modes, respectively.

t

(LRCP)

1.4 V

LRCK

t

(BCKL)

(LRSU)

t

(LRHD)

t

(BCKH)

BCK

t

(LRDO)

t

(CKDO)

(BCKP)

0.5 V

DOUT

DD

SYMBOL

PARAMETER

MIN

150

60

TYP

MAX

UNIT

t

BCK period

ns

µs

ns

(BCKP)

(BCKH)

t

BCK pulse duration, HIGH

BCK pulse duration, LOW

t

60

(BCKL)

(LRSU)

(LRHD)

(LRCP)

t

LRCK setup time to BCK rising edge

LRCK hold time to BCK rising edge

LRCK period

20

10

t

Delay time, BCK falling edge to DOUT valid

Delay time, LRCK edge to DOUT valid

Rise time of all signals

–10

20

10

(CKDO)

t

(LRDO)

t

r

t

f

Fall time of all signals

:

NOTE Timing measurement reference level is (V + V ) / 2. Rise and fall times are measured

IH

IL

from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT is 20 pF.

Figure 24. Audio Data Interface Timing (Slave Mode: LRCK, BCK Work as Inputs)

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t

(LRCP)

0.5 V

LRCK

DD

t

(BCKL)

t

(CKLR)

(BCKH)

0.5 V

BCK

DD

t

(LRDO)

t

(CKDO)

(BCKP)

0.5 V

DOUT

DD

SYMBOL

PARAMETER

MIN

TYP

1/(64 f )

MAX

UNIT

t

BCK period

150

1000

400

20

ns

µs

ns

(BCKP)

S

BCK pulse duration, HIGH

60 0.5 t

(BCKP)

60 0.5 t

(BCKP)

(BCKH)

t

BCK pulse duration, LOW

(BCKL)

(CKLR)

(LRCP)

t

Delay time, BCK falling edge to LRCK valid

LRCK period

–10

10

1/f

S

60

t

Delay time, BCK falling edge to DOUT valid

Delay time, LRCK edge to DOUT valid

Rise time of all signals

–10

20

(CKDO)

t

20

(LRDO)

t

r

10

t

Fall time of all signals

10

f

:

NOTE Timing measurement reference level is (V + V ) / 2. Rise and fall times are measured from 10%

IH

IL

to 90% of IN/OUT signal swing. Load capacitance of all signals is 20 pF.

Figure 25. Audio Data Interface Timing (Master Mode: LRCK, BCK Work as Outputs)

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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM

In slave mode, the PCM1850/1851 operates under LRCK, synchronized with system clock SCKI. The PCM1850/1851

does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and

SCKI.

If the relationship between LRCK and SCKI changes more than 6 BCKs for 64 BCKs/frame ( 5 BCKs for 48 BCKs/frame)

during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f_Sand digital output is

forced into the BPZ code until resynchronization between LRCK and SCKI is completed.

In the case of changes less than 5 BCKs for 64 BCKs/frame ( 4BCKs for 48BCK/frame), resynchronization with

simultaneous discontinuity in the digital output does not occur.

Figure 26 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data,

the PCM1850/1851 might generate some noise in the audio signal. Also, the transition of normal to undefined data and

undefined or zero data to normal creates a discontinuity of data in the digital output, which could generate some noise in

the audio signal.

It is recommended to set RST (pin 10) to LOW to get stable analog performance when the sampling rate, interface mode,

or data format is changed.

Resynchronization

Synchronization Lost

State of

Synchronization

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

1/f

S

32/f

S

UNDEFINED

DATA

DOUT

NORMAL DATA

ZERO DATA

NORMAL DATA

Figure 26. ADC Digital Output for Loss of Synchronization and Resynchronization

Power-Down Control

RST(pin 10) controls the entire ADC operation. During reset mode, the supply current of the analog section is shut off and

the digital section is initialized. DOUT (pin 3) is also disabled. Halting SCKI, BCK, and LRCK is recommended to minimize

power dissipation.

RST

LOW

HIGH

POWER-DOWN MODE

Reset and power-down modes

Normal operation mode

Overflow Flag Output

The PCM1850/1851 has an output flag (pin 4) that indicates when overflow occurs in the L-channel or R-channel, and this

flag remains HIGH at least during the 8192/f_Stime for a momentary overflow occurrence.

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HPF Bypass Control

The built-in HPF function for dc component rejection can be bypassed via the serial port. In bypass mode, the dc component

of the analog input signal, the internal dc offset, etc., are converted and included in the digital output data.

BYP

HPF (HIGH-PASS FILTER) MODE

Normal (no dc component on DOUT) mode (default)

Bypass (dc component on DOUT) mode

0

1

System Reset Control

The system reset control is used to resynchronize the system via the serial port when the system clock frequency, interface

mode, and data format are changed. Change them while SRST = LOW. If they are changed during normal operation, analog

performance can be degraded.

SRST

SYSTEM RESET

Resynchronization

Normal operation (default)

0

1

Mode Register Reset Control

The MRST bit is used to reset the mode control register to its default settings via the serial port.

MRST

MODE REGISTER RESET

Set default value

Normal operation (default)

0

1

SPI SERIAL CONTROL PORT FOR MODE CONTROL (PCM1850)

The user-programmable built-in functions of the PCM1850 can be controlled through a serial control port with the SPI

format. All operations for the serial control port use 16-bit data words. Figure 27 shows the control data word format. The

most significant bit must be set to 0. There are seven bits, labeled IDX[6:0], that set the register index (or address) for write

operations. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].

Figure 28 shows the functional timing diagram for writing to the serial control port. MS (pin 30) is held at a logic 1 state until

a register needs to be written. To start the register write cycle, MS is set to logic 0. Sixteen clocks are then provided on MC

(pin 31), corresponding to the 16 bits of the control data word on MD (pin 32). After the sixteenth clock cycle has completed,

the data is latched into the indexed mode control register in the write operation. To write the next data word, MS must be

set to 1 once.

LSB

D0

MSB

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0

D7

D6

D5

D4

D3

D2

D1

Register Index (or Address)

Register Data

Figure 27. Control Data Word Format for MD

MS

MC

MD

X

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7

D6

D5

D4

D3

D2

D1

D0

X

0

IDX6

Figure 28. Serial Control Format

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CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850)

Figure 29 shows a detailed timing diagram for the serial control interface of the PCM1850. These timing parameters are

critical for proper control port operation.

t

(MHH)

MS

1.4 V

t

(MCL)

(MSS)

t

(MSH)

(MCH)

MC

MD

1.4 V

t

(MCY)

LSB

t

(MDS)

t

(MDH)

SYMBOL

PARAMETERS

MIN

100

40

MAX UNITS

t

MC pulse cycle time

MC LOW level time

MC HIGH level time

MS HIGH level time

ns

(MCY)

t

(MCL)

(MCH)

(MHH)

t

40

80

t

MS falling edge to MC rising edge

15

(MSS)

(MSH)

(MDH)

(MDS)

(1)

t

MS hold time

15

MD hold time

MD setup time

15

(1)

MC rising edge for LSB to MS rising edge.

Figure 29. PCM1850 Control Interface Timing

I²C SERIAL CONTROL PORT FOR MODE CONTROL (PCM1851)

The user-programmable built-in function of the PCM1851 can be controlled through the I²C-format serial control port, SDA

(pin 32) and SCL (pin 31). The PCM1851 supports the I²C serial bus and the data transmission protocol for standard mode

as a slave device. This protocol is explained in the I²C specification 2.0.

Slave Address

MSB

1

LSB

0

1

0

1

ADR

R/nW

The PCM1851 has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to

100101. The last bit of the address byte is the device select bit, which can be user-defined by the ADR pin (pin 30). A

maximum of two PCM1851s can be connected on the same bus at one time. Each PCM1851 responds when it receives

its own slave address.

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Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address with read/write bit, data if

write or acknowledgement if read, and stop condition. The PCM1851 supports only slave receivers, so the R/W bit must

be set to 0.

SDA

SCL

St

1−7

8

9

1−8

9

1−8

9

Sp

Slave Address R/W

ACK

DATA

ACK

DATA

ACK

Start

Condition

R/W: Read Operation if 1; Otherwise, Write Operation

ACK: Acknowledgement of a Byte if 0

DATA: 8 Bits (Byte)

Stop

Condition

Transmitter

Data Type

M

S

M

S

M

S

M

St

Slave Address

R/W

ACK

DATA

ACK

DATA

ACK

Sp

M: Master Device

S: Slave Device

St: Start Condition

Sp: Stop Condition

2

Figure 30. Basic I C Framework

Write Operation

The PCM1851 has only the write mode. A master can write to any PCM1851 registers using single or multiple accesses.

The master sends a PCM1851 slave address with a write bit, a register address, and the data. If multiple access is required,

the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the

index register is incremented by 1 automatically. When the index register reaches 33h, the next value is 31h. When

undefined registers are accessed, the PCM1851 does not send an acknowledgement. Figure 31 is a diagram of the write

operation. The register address and the write data are 8 bits and MSB-first format.

Transmitter

Data Type

M

S

M

S

M

S

M

S

M

St

Slave Address

W

ACK Reg Address ACK

Write Data 1

ACK Write Data 2

ACK

Sp

M: Master Device

St: Start Condition

S: Slave Device

ACK: Acknowledge

W: Write

Sp: Stop Condition

Figure 31. Framework for Write Operation

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TIMING DIAGRAM

Start

Repeated Start

Stop

t

(SDA-F)

(D-HD)

t

(P-SU)

(BUF)

(D-SU)

(SDA-R)

SDA

t

(RS-HD)

(SCL-R)

t

(LOW)

SCL

t

(RS-SU)

(S-HD)

(HI)

t

(SCL-F)

SYMBOL

PARAMETER

MIN

MAX

UNIT

kHz

µs

f

t

SCL clock frequency

100

(SCL)

Bus free time between STOP and START condition

Low period of the SCL clock

4.7

4

(BUF)

t

µs

(LOW)

t

High period of the SCL clock

µs

(HI)

t

Setup time for START/repeated START condition

4.7

µs

(RS-SU)

t

(S-HD)

(RS-HD)

Hold time for START/repeated START condition

4

µs

t

Data setup time

250

0

ns

µs

pF

V

(D-SU)

(D-HD)

(SCL-R)

Data hold time

900

t

Rise time of SCL signal

Fall time of SCL signal

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

Capacitive load for SDA and SCL line

20 + 0.1C

4

1000

B

t

(SCL-F)

t

(SDA-R)

t

(SDA-F)

t

(P-SU)

C

B

400

V

NH

Noise margin at HIGH level for each connected device (including hysteresis)

0.2 V

DD

Figure 32. PCM1851 Control Interface Timing Requirements

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MODE CONTROL REGISTERS

User-Programmable Mode Control Functions

The PCM1850/1851 has several user-programmable functions which are accessed via control registers. The registers are

programmed using the serial control port which is discussed in the SPI Serial Control Port for Mode Control (PCM1850)

and I²C Serial Control Port for Mode Control (PCM1851) sections of this data sheet. Table 6 lists the available mode control

functions, along with their reset default conditions and associated register index.

Register Map

The mode control register map is shown in Table 7. Each register includes an index (or address) indicated by the IDX[6:0]

bits B[14:8].

Table 6. User-Programmable Mode Control Functions

FUNCTION

Mode register reset

RESET DEFAULT

Normal operation

–11 dB

REGISTER

BIT(S)

MRST

31

32

33

PGA gain control

PG[5:0]

CH[2:0]

BYP

Multiplexer input channel control

HPF bypass control

Channel 1

HPF enable

Normal operation

Slave

System reset

SRST

Audio interface mode control

Audio interface format control

MD[1:0]

FMT[2:0]

2

I S

Table 7. Mode Control Register Map

HEX

B15

0

B14

0

B13

1

B12

1

B11

0

B10

0

B9

0

B8

1

B7

B6

B5

B4

B3

B2

B1

B0

Register 31

Register 32

RSV MRST PG5

PG4

RSV

PG3

RSV

PG2

CH2

PG1

CH1

PG0

CH0

0

1

0

1

0

RSV

BYP

RSV

Register 33

0

1

0

1

SRST RSV

MD1 MD0 FMT2 FMT1 FMT0

:

NOTE RSV bit must be always written as 0. No values can be written in address 30h.

26

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

TYPICAL CIRCUIT CONNECTION DIAGRAM

The following figure illustrates a typical circuit connection diagram for six stereo inputs and an analog monitor.

Analog Input/Output

C

17

C

16

C

15

C

14

C

13

C

12

C

11 10

+

24 23 22 21 20 19 18 17

+

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

V

S

V R2

IN

REF

cc

C

5

4

3

9

1

2

V L2

IN

8

V R1

IN

7

+5 V

0 V

V L1

IN

+

C

1

6

PCM1850/1851

AGND

MOUTL

MOUTR

RST

19

18

(1)

MS (ADR)

(1)

MC (SCL)

(1)

MD (SDA)

TEST1

Control

1

2

3

4

5

6

7

8

C

2

+

3.3 V

Audio Data Processor

(1)

PCM1850 (PCM1851)

:

NOTE C , C : 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended, depending on layout and power supply.

1

2

C , C , C : 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended.

3

4

5

C – C : A 0.33-µF capacitor gives a 2.9-Hz (τ = 0.33 µF × 169 kΩ) typical cutoff frequency at the HPF input in normal operation, and it

6

17

requires power-on settling time with a 56-ms time constant in the power-on initialization period. Cutoff frequency and time constant depend

on PGA gain. Cutoff frequency varies from 2.4 Hz to 8.5 Hz for 0.33 µF. Dc-coupled input is inhibited for the analog input, V L[1:6] and

IN

V R[1:6].

IN

C

18

–C : A 2.2-µF capacitor with a 10-kΩ load gives a 7.2-Hz cutoff frequency.

19

27

PCM1850

PCM1851

www.ti.com

SLES108 − MARCH 2004

BOARD DESIGN AND LAYOUT CONSIDERATIONS

V

, V Pins

DD

CC

The digital and analog power supply lines to the PCM1850/1851 must be bypassed to the corresponding ground pins with

0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance

of the ADC.

AGND, DGND Pins

To maximize the dynamic performance of the PCM1850/1851, the analog and digital grounds are not connected internally.

These grounds must have low impedance to avoid digital noise feeding back into the analog ground. Therefore, they should

be connected directly to each other under the parts to reduce the potential of a noise problem.

V L[1:6], V R[1:6] Pins

IN

A 0.33-µF capacitor is recommended as the ac-coupling capacitor, which gives a 2.4- to 8.5-Hz cutoff frequency. If higher

full-scale input voltage is required, it can be adjusted by adding only one series resistor to each V_INxx pin, but a signal source

resistance less than 1 kΩ is recommended for these pins in order to keep accuracy of the gain control command and to

maintain crosstalk performance.

MOUTL, MOUTR Pins

An ac-coupled light load is recommended; a 2.2-µF capacitor with a 10-kΩ load gives a 7.2-Hz cutoff frequency.

V

1, V

2, V S Pins

REF

Between V_REF1 and AGND, V_REF2 and AGND, and V_REFS and AGND, 0.1-µF ceramic and 10-µF electrolytic capacitors

are recommended to ensure low source impedance of the ADC references. These capacitors should be located as close

as possible to the V_REF1, V_REF2, and V_REFS pins to reduce dynamic errors on the ADC references. The differential voltage

between V_REF2 and AGND sets the analog input full-scale range.

BCK and LRCK Pins (in Master Mode), DOUT Pin

These pins have enough load driving capability. However, if the output line is long, locating a buffer near the PCM1850/1851

and minimizing load capacitance is recommended in order to minimize the digital-analog crosstalk and maximize the

dynamic performance of the ADC.

System Clock

Because the PCM1850/1851 operates based on a system clock, the quality of the system clock can influence dynamic

performance. Therefore, it is recommended to consider the system clock duty, jitter, and the time difference between the

system clock transition and the BCK or LRCK transition in slave mode.

28

MECHANICAL DATA

MPQF112 – NOVEMBER 2001

PJT (S-PQFP–N32)

PLASTIC QUAD FLATPACK

0,45

0,30

0,80

M

0,20

0,09

Gage Plane

32

0,15

0,05

0,25

1

0°– 7°

7,00

9,00

SQ

0,75

0,45

1,05

0,95

Seating Plane

0,10

1,20

1,00

4203540/A 11/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265

型号:	PCM1851PJT
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Not Recommended
零件包装代码：	QFP
包装说明：	TQFP, TQFP32,.35SQ,32
针数：	32
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.43
最大模拟输入电压：	5.5 V
转换器类型：	ADC, DELTA-SIGMA
JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e4
长度：	7 mm
湿度敏感等级：	1
模拟输入通道数量：	2
位数：	24
功能数量：	1
端子数量：	32
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出位码：	2'S COMPLEMENT BINARY
输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY
封装代码：	TQFP
封装等效代码：	TQFP32,.35SQ,32
封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：	260
电源：	3.3,5 V
认证状态：	Not Qualified
采样速率：	0.096 MHz
座面最大高度：	1.2 mm
子类别：	Analog to Digital Converters
最大压摆率：	10 mA
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm
Base Number Matches：	1

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