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产品型号PGA204AP的概述

芯片PGA204AP的概述 PGA204AP是一款高性能的模拟信号处理芯片，主要用于对模拟信号的放大和优化。它广泛应用于各种电子设备中，如音频设备、传感器接口以及工控设备等。该芯片由于其高增益、低噪声特性以及高输入阻抗，成为了许多高要求信号处理场合的理想选择。 PGA204AP的核心特点包括可调的增益特性，使得用户能够灵活设计电路以适应不同的应用需求。该芯片支持多种增益设置，提供了广泛的动态范围，能有效抑制信号中的噪声，提高系统的整体性能。这些特性使得PGA204AP在工业控制、医疗设备、通信系统等领域得到了广泛的应用。芯片PGA204AP的详细参数 PGA204AP的主要参数包括： - 增益范围：0 dB至20 dB可调线上，并提供多个增益设置选项，以满足不同信号强度的需求。 - 输入阻抗：高输入阻抗（通常在几百千欧姆级别），有效降低信号源对电路的负担。 - 输出阻抗：低输出阻抗，...

产品型号PGA204AP的Datasheet PDF文件预览

PGA204

PGA205

Programmable Gain

INSTRUMENTATION AMPLIFIER

FEATURES

● DIGITALLY PROGRAMMABLE GAIN:

DESCRIPTION

The PGA204 and PGA205 are low cost, general pur-

pose programmable-gain instrumentation amplifiers

offering excellent accuracy. Gains are digitally se-

lected: PGA204—1, 10, 100, 1000, and PGA205—1,

2, 4, 8V/V. The precision and versatility, and low cost

of the PGA204 and PGA205 make them ideal for a

wide range of applications.

PGA204: G=1, 10, 100, 1000V/V

PGA205: G=1, 2, 4, 8V/V

● LOW OFFSET VOLTAGE: 50µV max

● LOW OFFSET VOLTAGE DRIFT: 0.25µV/°C

● LOW INPUT BIAS CURRENT: 2nA max

● LOW QUIESCENT CURRENT: 5.2mA typ

● NO LOGIC SUPPLY REQUIRED

Gain is selected by two TTL or CMOS-compatible

address lines, A₀and A₁. Internal input protection can

withstand up to ±40V on the analog inputs without

damage.

● 16-PIN PLASTIC DIP, SOL-16 PACKAGES

The PGA204 and PGA205 are laser trimmed for very

low offset voltage (50µV), drift (0.25µV/°C) and high

common-mode rejection (115dB at G=1000). They op-

erate with power supplies as low as ±4.5V, allowing use

in battery operated systems. Quiescent current is 5mA.

APPLICATIONS

● DATA ACQUISITION SYSTEM

● GENERAL PURPOSE ANALOG BOARDS

● MEDICAL INSTRUMENTATION

The PGA204 and PGA205 are available in 16-pin

plastic DIP, and SOL-16 surface-mount packages, speci-

fied for the –40°C to +85°C temperature range.

V_O1V+

PGA204

PGA205

–

V_IN

Over-Voltage

Protection

Feedback

A₁

25kΩ

A₁

A₀

Digitally Selected

Feedback Network

A₃

V_O

Digital

Ground

A₂

Ref

V_IN

Over-Voltage

Protection

25kΩ

V_OSAdj

V_O2

V–

International Airport Industrial Park

•

Mailing Address: PO Box 11400

Cable: BBRCORP

•

Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd.

• Tucson, AZ 85706

Tel: (520) 746-1111

•

Twx: 910-952-1111

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1176A

Printed in U.S.A. October, 1993

PGA204/205

SPECIFICATIONS

ELECTRICAL

PGA204 G=1, 10, 100, 1000V/V

At T_A= +25°C, V_S= ±15V, and R_L= 2kΩ unless otherwise noted.

PGA204BP, BU

TYP

PGA204AP, AU

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

INPUT

Offset Voltage, RTI

vs Temperature

T_A=+25°C

T_A=T_MINto T_MAX

V_S=±4.5V to ±18V

±10+20/G ±50+100/G

±0.1+0.5/G ±0.25+5/G

±25+30/G ±125+500/G

µV

µV/°C

µV/V

µV/mo

Ω || pF

±0.25+5/G

±1+10/G

vs Power Supply

0.5+2/G

±0.2+0.5/G

10¹⁰||6

3+10/G

Long-Term Stability

Impedance, Differential

Common-Mode

Input Common-Mode Range

Safe Input Voltage

Common-Mode Rejection

10¹⁰||6

V_O=0V (see text)

±10.5

±12.7

±40

_CM=±10V, ∆R_S=1kΩ

G=1

110

115

106

G=10

G=100

G=1000

114

123

106

110

BIAS CURRENT

vs Temperature

Offset Current

±0.5

±8

±0.5

±8

±2

±5

pA/°C

vs Temperature

pA/°C

NOISE, Voltage, RTI⁽¹⁾: f=10Hz

f=100Hz

G≥100, R_S=0Ω

0.4

nV/√Hz

µVp-p

f=1kHz

f_B=0.1Hz to 10Hz

Noise Current

f=10Hz

0.4

0.2

pA/√Hz

pAp-p

f=1kHz

f_B=0.1Hz to 10Hz

GAIN, Error

G=1

G=10

G=100

G=1000

G=1 to 1000

G=1

G=10

G=100

G=1000

±0.005

±0.01

±0.02

±2.5

±0.0004

±0.0008

±0.024

±0.05

±0.1

Gain vs Temperature

Nonlinearity

±10

ppm/°C

% of FSR

±0.001

±0.002

±0.01

±0.002

±0.004

±0.02

OUTPUT

Voltage, Positive⁽²⁾

Negative⁽²⁾

Load Capacitance Stability

Short Circuit Current

I_O=5mA, T_MINto T_MAX

I_O=–5mA, T_MINto T_MAX

(V+)–1.5

(V–)+1.5

(V+)–1.3

(V–)+1.3

1000

+23/–17

FREQUENCY RESPONSE

Bandwidth, –3dB

G=1

G=10

G=100

0.7

MHz

kHz

V/µs

µs

G=1000

V_O=±10V, G=10

G=1

Slew Rate

Settling Time⁽³⁾, 0.1%

0.3

G=10

G=100

G=1000

G=1

G=10

100

1000

0.01%

µs

G=100

G=1000

50% Overdrive

140

1300

Overload Recovery

DIGITAL LOGIC

Digital Ground Voltage, V_DG

Digital Low Voltage

Digital Input Current

Digital High Voltage

V–

(V+)–4

_DG+0.8V

µA

_DG+2

V+

POWER SUPPLY, Voltage

±4.5

±15

+5.2/–4.2

±18

±6.5

Current

V_IN=0V

±7.5

TEMPERATURE RANGE

Specification

Operating

–40

+85

+125

°C

θ_JA

°C/W

* Specification same as PGA204BP.

NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes

time to switch to a new gain.

PGA204/205

SPECIFICATIONS

ELECTRICAL

PGA205 G=1, 2, 4, 8V/V

At T_A= +25°C, V_S= ±15V, and R_L= 2kΩ unless otherwise noted.

PGA205BP, BU

TYP

PGA205AP, AU

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

INPUT

Offset Voltage, RTI

vs Temperature

vs Power Supply

Long-Term Stability

Impedance, Differential

Common-Mode

Input Common-Mode Range

Safe Input Voltage

T_A=+25°C

T_A=T_MINto T_MAX

V_S=±4.5V to ±18V

±10+20/G ±50+100/G

±0.1+0.5/G ±0.25+5/G

±25+30/G ±125+500/G

µV

µV/°C

µV/V

µV/mo

Ω||pF

±0.25+5/G

±1+10/G

0.5+2/G

±0.2+0.5/G

10¹⁰||6

3+10/G

10¹⁰||6

V_O=0V (see text)

±10.5

±12.7

±40

Common-Mode Rejection

_CM=±10V, ∆R_S=1kΩ

G=1

G=2

G=4

G=8

100

106

100

106

112

BIAS CURRENT

vs Temperature

Offset Current

±0.5

±8

±0.5

±8

±2

±5

pA/°C

vs Temperature

pA/°C

Noise Voltage, RTI⁽¹⁾: f=10Hz

f=100Hz

G=8, R_S=0Ω

0.5

nV/√Hz

µVp-p

f=1kHz

f_B=0.1Hz to 10Hz

Noise Current

f=10Hz

0.4

0.2

pA/√Hz

pAp-p

f=1kHz

f_B=0.1Hz to 10Hz

GAIN, Error

G=1

G=2

G=4

G=8

G=1 to 8

G=1

G=2

G=4

G=8

±0.005

±0.01

±2.5

±0.00024

±0.024

±10

±0.001

±0.002

±0.05

±0.002

±0.004

Gain vs Temperature

Nonlinearity

ppm/°C

% of FSR

OUTPUT

Voltage, Positive⁽²⁾

Negative⁽²⁾

Load Capacitance Stability

Short Circuit Current

I_O=5mA, T_MINto T_MAX

I_O=–5mA, T_MINto T_MAX

(V+)–1.5

(V–)+1.5

(V+)–1.3

(V–)+1.3

1000

+23/–17

FREQUENCY RESPONSE

Bandwidth, –3dB

G=1

G=2

G=4

MHz

kHz

V/µs

µs

400

200

100

0.7

G=8

Slew Rate

Settling Time⁽³⁾, 0.1%

V_O=±10V, G=8

G=1

0.3

G=2

G=4

G=8

G=1

G=2

G=4

G=8

0.01%

µs

Overload Recovery

50% overdrive

DIGITAL LOGIC INPUTS

Digital Ground Voltage, V_DG

Digital Low Voltage

V–

(V+)–4

_DG+0.8V

Digital Low Current

Digital High Voltage

µA

_DG+2

V+

POWER SUPPLY, Voltage

±4.5

±15

+5.2/–4.2

±18

±6.5

Current

V_IN=0V

±7.5

TEMPERATURE RANGE

Specification

Operating

–40

+85

+125

°C

θ_JA

°C/W

* Specification same as PGA204BP.

NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes

time to switch to a new gain.

PGA204/205

PACKAGE INFORMATION

ABSOLUTE MAXIMUM RATINGS

PACKAGE DRAWING

NUMBER⁽¹⁾

Supply Voltage .................................................................................. ±18V

Analog Input Voltage Range ............................................................. ±40V

Logic Input Voltage Range .................................................................. ±V_S

Output Short-Circuit (to ground) .............................................. Continuous

Operating Temperature ................................................. –40°C to +125°C

Storage Temperature..................................................... –40°C to +125°C

Junction Temperature .................................................................... +150°C

Lead Temperature (soldering –10s) .............................................. +300°C

MODEL

PACKAGE

PGA204AP

PGA204BP

PGA204AU

PGA204BU

16-Pin Plastic DIP

SOL-16 Surface Mount

180

211

PGA205AP

PGA205BP

PGA205AU

PGA205BU

16-Pin Plaseic DIP

16-Pin Plastic DIP

SOL-16 Surface Mount

180

211

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

ORDERING INFORMATION

MODEL

GAINS

PACKAGE

TEMPERATURE RANGE

PGA204AP

PGA204BP

1, 10, 100, 1000V/V

16-Pin Plastic DIP

–40 to +85°C

PGA204AU

PGA204BU

1, 10, 100, 1000V/V

SOL-16 Surface-Mount

–40 to +85°C

PGA205AP

PGA205BP

1, 2, 4, 8V/V

16-Pin Plastic DIP

–40 to +85°C

PGA205AU

PGA205BU

1, 2, 4, 8V/V

SOL-16 Surface-Mount

–40 to +85°C

PGA204/205

DICE INFORMATION

PAD

FUNCTION

PAD

FUNCTION

V_O2

Ref

V_O1

—

V_O

Feedback

V+

Dig. Ground

A₀

V^–

V⁺

FPO

V_OSAdj

_OSAdj

V–

A₁

Substrate Bias: Internally connected to V– power supply.

MECHANICAL INFORMATION

MILS (0.001")

MILLIMETERS

Die Size

Die Thickness

Min. Pad Size

186 x 130 ±5

20 ±3

4.72 x 3.30 ±0.13

0.51 ±0.08

4 x 4

0.1 x 0.1

Backing

Gold

PGA204/205 DIE TOPOGRAPHY

PIN CONFIGURATION

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with ap-

propriate precautions. Failure to observe proper handling and

installation procedures can cause damage.

Top View

V_O1

16 A₁

15 A₀

14 Dig. Ground

13 V+

V^–

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

V⁺

12 Feedback

11 V_O

V_OSAdjust

V–

10 Ref

V_O2

NC: No Internal Connection.

PGA204/205

TYPICAL PERFORMANCE CURVES

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

GAIN vs FREQUENCY

COMMON-MODE REJECTION vs FREQUENCY

140

120

100

G = 1k,100

G = 10

G=1k

“B” Grade

G = 1

G=100

100

G = 1k

G=10

G = 100

G=1

G = 10

G = 1

100k

100

10k

100

10k

100k

Frequency (Hz)

INPUT COMMON-MODE VOLTAGE RANGE

vs OUTPUT VOLTAGE

POSITIVE POWER SUPPLY REJECTION

vs FREQUENCY

140

120

100

–

G = 1k

V_D/2

V_O

–

V_D/2

G = 100

V_CM

(Any Gain)

G = 10

G = 1

A₃+ Output

Swing Limit

A₃– Output

Swing Limit

–5

–10

–15

–10

–5

100

10k

100k

Output Voltage (V)

Frequency (Hz)

NEGATIVE POWER SUPPLY REJECTION

vs FREQUENCY

INPUT- REFERRED NOISE VOLTAGE

vs FREQUENCY

140

100

120

100

G = 1k

G = 100

G = 10

G = 1

G = 10

G = 1

G = 100, 1k

G = 1k

BW Limit

100

10k

100k

100

10k

Frequency (Hz)

PGA204/205

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

INPUT-REFERRED

OFFSET VOLTAGE WARM-UP vs TIME

INPUT BIAS AND INPUT OFFSET CURRENT

vs TEMPERATURE

100

±I_B

–2

–4

–6

I_OS

–1

–2

105

120

–75

–50

–25

100

125

Time from Power Supply Turn-on (s)

Temperature (°C)

INPUT BIAS CURRENT

vs DIFFERENTIAL INPUT VOLTAGE

vs COMMON-MODE INPUT VOLTAGE

Both Inputs

One Input

|I_b1| + |I_b2

Over-Voltage

Protection

Over-Voltage

Protection

Normal

Operation

–1

–2

–3

–1

–2

–3

G = 1

G = 10

One Input

G = 100, 1k

–30

Both Inputs

–30 –15

–45

–15

–45

Common-Mode Voltage (V)

Differential Overload Voltage (V)

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

SLEW RATE vs TEMPERATURE

1.0

0.8

0.6

0.4

0.2

G ≤ 10

G=8 or 10

100

10k

100k

–75

–50

–25

100

125

Frequency (Hz)

Temperature (°C)

PGA204/205

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

QUIESCENT CURRENT vs TEMPERATURE

OUTPUT CURRENT LIMIT vs TEMPERATURE

6.0

5.5

5.0

4.5

4.0

+|I_CL

–|I_CL

–75

–50

–25

100

125

–40

–15

Temperature (°C)

QUIESCENT CURRENT

vs POWER SUPPLY VOLTAGE

POSITIVE OUTPUT SWING vs TEMPERATURE

V_S= ±15V

5.2

5.0

4.5

4.0

3.5

V+

V_S= 11.4

V_S= ±4.5

V–

±5

±10

±15

±20

–75

–50

–25

100

125

Power Supply Voltage (V)

Temperature (°C)

NEGATIVE OUTPUT SWING vs TEMPERATURE

V_S= ±15V

–16

–14

–12

–10

–8

V_S= 11.4

V_S= ±4.5

–6

–4

–2

–75

–50

–25

100

125

Temperature (°C)

PGA204/205

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

SMALL-SIGNAL RESPONSE, G = 1

LARGE-SIGNAL RESPONSE, G = 1

+200mV

–200mV

+10V

–10V

SMALL-SIGNAL RESPONSE, G = 10

LARGE-SIGNAL RESPONSE, G = 10

+200mV

–200mV

+10V

–10V

SMALL-SIGNAL RESPONSE, G = 1000

LARGE-SIGNAL RESPONSE, G = 1000

+10V

–10V

+200mV

–200mV

PGA204/205

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

INPUT-REFERRED NOISE,

0.1 TO 10Hz, G = 1000

NOISE, 0.1 TO 10Hz, G = 1

0.5µV/Div

0.2µV/Div

1s/Div

be used to sense the output voltage directly at the load for

best accuracy.

APPLICATION INFORMATION

Figure 1 shows the basic connections required for operation

of the PGA204/205. Applications with noisy or high imped-

ance power supplies may require decoupling capacitors

close to the device pins as shown.

The output is referred to the output reference (Ref) terminal

which is normally grounded. This must be a low-impedance

connection to assure good common-mode rejection. A resis-

tance of 5Ω in series with the Ref pin will cause a typical

device to degrade to approximately 80dB CMR (G=1).

DIGITAL INPUTS

The digital inputs A₀and A₁select the gain according to the

logic table in Figure 1. Logic “1” is defined as a voltage

greater than 2V above digital ground potential (pin 14).

Digital ground can be connected to any potential from the

V– power supply to 4V less than V+. Digital ground is

normally connected to ground. The digital inputs interface

directly CMOS and TTL logic components.

The PGA204/205 has an output feedback connection (pin

12). Pin 12 must be connected to the output terminal (pin 11)

for proper operation. The output Feedback connection can

Approximately 1µA flows out of the digital input pins when

a logic “0” is applied. Logic input current is nearly zero with

a logic “1” input. A constant current of approximately

+15V

1µF

V_O1

PGA204

PGA205

–

V_IN

Over-Voltage

Protection

Feedback

A₁

25kΩ

Digitally Selected

Feedback Network

A₃

V_O

_O= G (V_I⁺_N– V_I^–_N

)

Ref

A₂

V_IN

Over-Voltage

Protection

25kΩ

Sometimes shown in simplified form:

1µF

V_OS

Adj

V_O2

GAIN

–

V_IN

PGA204 PGA205 A₁A₀

PGA204

V_O

+15V

V_IN

100

1000

A₁A₀

FIGURE 1. Basic Connections.

PGA204/205

Some applications select gain of the PGA204/205 with

switches or jumpers. Figure 2 shows pull-up resistors con-

nected to assure a noise-free logic “1” when the switch,

jumper or open-collector logic is open or off. Fixed-gain

applications can connect the logic inputs directly to V+ or

V– (or other valid logic level); no resistor is required.

V+

Over-Voltage

Protection

–

A₁

V_IN

100kΩ

Digitally Selected

Feedback Network

OFFSET VOLTAGE

Voltage offset of the PGA204/205 consists of two compo-

nents—input stage offset and output stage offset. Both

components are specified in the specification table in equa-

tion form:

A₂

V_IN

Over-Voltage

Protection

Switches, jumpers

or open-collector

logic output.

Digital ground can

alternatively be connected

to V– power supply.

V_OS= V_OSI+ V_OSO/ G

where:

(1)

V_OS

Adj

V_O2

V_OStotal is the combined offset, referred to the input.

FIGURE 2. Switch or Jumper-Selected Digital Inputs.

V_OSIis the offset voltage of the input stage, A₁and A₂.

V_OSOis the offset voltage of the output difference

amplifier, A₃.

1.3mA flows in the digital ground pin. It is good practice to

return digital ground through a separate connection path so

that analog ground is not affected by the digital ground

current.

V_OSIand V_OSOdo not change with gain. The composite

offset voltage V_OSchanges with gain because of the gain

term in equation 1. Input stage offset dominates in high gain

(G≥100); both sources of offset may contribute at low gain

(G=1 to 10).

The digital inputs, A₀and A₁, are not latched; a change in

logic inputs immediately selects a new gain. Switching time

of the logic is approximately 1µs. The time to respond to

gain change is effectively the time it takes the amplifier to

settle to a new output voltage in the newly selected gain (see

settling time specifications).

OFFSET TRIMMING

Both the input and output stages are laser trimmed for very

low offset voltage and drift. Many applications require no

external offset adjustment.

Many applications use an external logic latch to access gain

control data from a high speed data bus (see Figure 7). Using

an external latch isolates the high speed digital bus from

sensitive analog circuitry. Locate the latch circuitry as far as

practical from analog circuitry.

Figure 3 shows an optional input offset voltage trim circuit.

This circuit should be used to adjust only the input stage

offset voltage of the PGA204/205. Do this by programming

V_O1V+

PGA204

PGA205

–

V_IN

Over-Voltage

Protection

Feedback

A₁

25kΩ

Resistors can be substituted

for REF200. Power supply

rejection will be degraded.

A₁

A₀

Digitally Selected

Feedback Network

A₃

V_O= G (V_I⁺_N– V_I^–_N) + V_REF

V+

Digital

Ground

100µA

V_REF

A₂

1/2 REF200

V_IN

Over-Voltage

Protection

25kΩ

100Ω

OPA177

10kΩ

±10mV

Adjustment Range

V_O2

V–

Input Offset

200kΩ

to 1MΩ

Output Offset

Adjustment

Trim Range

≈ ±250µV

100µA

1/2 REF200

V+

V–

FIGURE 3. Optional Offset Voltage Trim Circuit.

PGA204/205

it to its highest gain and trimming the output voltage to zero

with the inputs grounded. Drift performance usually im-

proves slightly when the input offset is nulled with this

procedure.

Microphone,

Hydrophone

etc.

PGA204

Do not use the input offset adjustment to trim system offset

or offset produced by a sensor. Nulling offset that is not

produced by the input amplifiers will increase temperature

drift by approximately 3.3µV/°C per 1mV of offset adjust-

ment.

47kΩ

Many applications that need input stage offset adjustment do

not need output stage offset adjustment. Figure 3 also shows

a circuit for adjusting output offset voltage. First, adjust the

input offset voltage as discussed above. Then program the

device for G=1 and adjust the output to zero. Because of the

interaction of these two adjustments at G=8, the PGA205

may require iterative adjustment.

Thermocouple

PGA204

10kΩ

The output offset adjustment can be used to trim sensor or

system offsets without affecting drift. The voltage applied to

the Ref terminal is summed with the output signal. Low

impedance must be maintained at this node to assure good

common-mode rejection. This is achieved by buffering the

trim voltage with an op amp as shown.

PGA204

V_R

Center-tap provides

bias current return.

NOISE PERFORMANCE

The PGA204/205 provides very low noise in most applica-

tions. Low frequency noise is approximately 0.4µVp-p mea-

sured from 0.1 to 10Hz. This is approximately one-tenth the

noise of “low noise” chopper-stabilized amplifiers.

Bridge

PGA204

Bias current return

INPUT BIAS CURRENT RETURN PATH

inherrently provided by source.

The input impedance of the PGA204/205 is extremely high—

approximately 10¹⁰Ω. However, a path must be provided for

the input bias current of both inputs. This input bias current

is typically less than ±1nA (it can be either polarity due to

cancellation circuitry). High input impedance means that

this input bias current changes very little with varying input

voltage.

FIGURE 4. Providing an Input Common-Mode Current

Path.

INPUT COMMON-MODE RANGE

The linear common-mode range of the input op amps of the

PGA204/205 is approximately ±12.7V (or 2.3V from the

power supplies). As the output voltage increases, however,

the linear input range will be limited by the output voltage

swing of the input amplifiers, A₁and A₂. The common-

mode range is related to the output voltage of the complete

amplifier—see performance curve “Input Common-Mode

Range vs Output Voltage”.

Input circuitry must provide a path for this input bias current

if the PGA204/205 is to operate properly. Figure 4 shows

provisions for an input bias current path. Without a bias

current return path, the inputs will float to a potential which

exceeds the common-mode range of the PGA204/205 and

the input amplifiers will saturate. If the differential source

resistance is low, bias current return path can be connected

to one input (see thermocouple example in Figure 4). With

higher source impedance, using two resistors provides a

balanced input with possible advantages of lower input

offset voltage due bias current and better common-mode

rejection.

A combination of common-mode and differential input

voltage can cause the output of A₁or A₂to saturate. Figure

5 shows the output voltage swing of A₁and A₂expressed in

terms of a common-mode and differential input voltages.

Output swing capability of these internal amplifiers is the

same as the output amplifier, A₃. For applications where

input common-mode range must be maximized, limit the

output voltage swing by selecting a lower gain of the

PGA204/205 (see performance curve “Input Common-Mode

Voltage Range vs Output Voltage”). If necessary, add gain

after the PGA204/205 to increase the voltage swing.

Many sources or sensors inherently provide a path for input

bias current (e.g. the bridge sensor shown in Figure 4).

These applications do not require additional resistor(s) for

proper operation.

PGA204/205

V_O1V+

G • V_D

V_CM

–

PGA204

PGA205

Over-Voltage

Protection

Feedback

A₁

25kΩ

V_D

A₁

A₀

Digitally Selected

Feedback Network

A₃

V_O

Digital

Ground

V_D

A₂

Ref

Over-Voltage

Protection

V_CM

25kΩ

G • V_D

V_CM

V_O2

V–

FIGURE 5. Voltage Swing of A₁and A₂.

Input-overload often produces an output voltage that appears

normal. For example, consider an input voltage of +20V on

one input and +40V on the other input will obviously exceed

the linear common-mode range of both input amplifiers.

Since both input amplifiers are saturated to the nearly the

same output voltage limit, the difference voltage measured

by the output amplifier will be near zero. The output of the

PGA204/205 will be near 0V even though both inputs are

overloaded.

V+

47kΩ

–

V_IN

A₁

A₀

PGA204

PGA205

V_IN

INPUT PROTECTION

The inputs of the PGA204/205 are individually protected for

voltages up to ±40V. For example, a condition of –40V on

one input and +40V on the other input will not cause

damage. Internal circuitry on each input provides low series

impedance under normal signal conditions. To provide

equivalent protection, series input resistors would contribute

excessive noise. If the input is overloaded, the protection

circuitry limits the input current to a safe value (approxi-

mately 1.5mA). The typical performance curve “Input Bias

Current vs Common-Mode Input Voltage” shows this input

current limit behavior. The inputs are protected even if no

power supply voltage is present.

D1, D2: IN4148, IN914, etc.

GAIN

PGA204 PGA205

SWITCH

POSITION

100

1000

FIGURE 6. Switch-Selected PGIA.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

PGA204/205

+15V

V_O1V+

HI-509

PGA204

PGA205

Over-Voltage

Protection

Feedback

A₁

–

V_IN

25kΩ

A₁16

Digitally Selected

Feedback Network

A₃

A₀

V_O

V_IN

A₂

Ref

Over-Voltage

Protection

25kΩ

A₀A₁

1 16

V_OS

Adj

V_O2

V–

–15V

Data Out

74HC574

Data In

To Address

Decoding Logic

Data Bus

FIGURE 7. Multiplexed-Input Programmable Gain IA.

A₀A₁

V_O1

V_I^–_N

V_I⁺_N

PGA204

PGA205

V_O

Ref

V_O2

A₁A₀

220Ω

20kΩ

OPA177

FIGURE 8. Shield Drive Circuit.

V_IN

A₁

PGA205

A_O

V_O

–

A_O

V_O

PGA204

PGA205

–

V_IN

Ref

R₁

1MΩ

C₁

0.1µF

A₁A₀

GAIN A₃

A₂

A₁A₀

f_–3dB

2πR₁C₁

OPA602

= 1.59Hz

FIGURE 9. Binary Gain Steps, G=1 to G=64.

FIGURE 10. AC-Coupled PGIA.

PGA204/205

PGA204AP相关文章

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PGA204AP产品参数

型号:	PGA204AP
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	PLASTIC, DIP-16
Reach Compliance Code：	unknown
风险等级：	5.7
Is Samacsys：	N
放大器类型：	INSTRUMENTATION AMPLIFIER
最大平均偏置电流 (IIB)：	0.005 µA
标称带宽 (3dB)：	1 MHz
最小共模抑制比：	75 dB
最大输入失调电流 (IIO)：	0.002 µA
最大输入失调电压：	625 µV
JESD-30 代码：	R-PDIP-T16
JESD-609代码：	e0
长度：	19.305 mm
负供电电压上限：	-18 V
标称负供电电压 (Vsup)：	-15 V
最大非线性：	0.02%
功能数量：	1
端子数量：	16
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
电源：	+-15 V
认证状态：	Not Qualified
座面最大高度：	5.08 mm
标称压摆率：	0.7 V/us
子类别：	Instrumentation Amplifiers
最大压摆率：	7.5 mA
供电电压上限：	18 V
标称供电电压 (Vsup)：	15 V
表面贴装：	NO
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
最大电压增益：	1000
最小电压增益：	1
标称电压增益：	100
Base Number Matches：	1

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产品型号PGA204AP的概述

产品型号PGA204AP的Datasheet PDF文件预览

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